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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02612—Formation types
  • H01L21/02617—Deposition types
  • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02524—Group 14 semiconducting materials
  • H01L21/02529—Silicon carbide
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/02521—Materials
  • H01L21/02524—Group 14 semiconducting materials
  • H01L21/02532—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02518—Deposited layers
  • H01L21/0257—Doping during depositing
  • H01L21/02573—Conductivity type
  • H01L21/02576—N-type
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  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
  • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
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  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
  • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/01—Manufacture or treatment
  • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/82—Heterojunctions
  • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions

Definitions

• This invention relates generally to the deposition of silicon- containing materials in semiconductor processing, and relates more specifically to selective formation of silicon-containing materials on semiconductor windows.
• epitaxial layers are often desired in selected locations, such as active area mesas among field isolation regions, or even more particularly over defined source and drain regions. While non- epitaxial (amorphous or polycrystalline) material can be selectively removed from over the field isolation regions after deposition, it is typically considered more efficient to simultaneously provide chemical vapor deposition (CVD) and etching chemicals, and to tune conditions to result in zero net deposition over insulative regions and net epitaxial deposition over exposed semiconductor windows.
• CVD chemical vapor deposition
• etching chemicals to tune conditions to result in zero net deposition over insulative regions and net epitaxial deposition over exposed semiconductor windows.
• This process known as selective epitaxial CVD, takes advantage of slow nucleation of typical semiconductor deposition processes on insulators like silicon oxide or silicon nitride.
• Such selective epitaxial CVD also takes advantage of the naturally greater susceptibility of amorphous and polycrystalline materials to etchants, as compared to the susceptibility of epitaxial layers.
• Examples of the many situations in which selective epitaxial formation of semiconductor layers is desirable include a number of schemes for producing strain.
• the electrical properties of semiconductor materials such as silicon, germanium and silicon germanium alloys are influenced by the degree to which the materials are strained. For example, silicon exhibits enhanced electron mobility under tensile strain, and silicon germanium exhibits enhanced hole mobility under compressive strain. Methods of enhancing the performance of semiconductor materials are of considerable interest and have potential applications in a variety of semiconductor processing applications.
• Semiconductor processing is typically used in the fabrication of integrated circuits, which entails particularly stringent quality demands, as well as in a variety of other fields.
• semiconductor processing techniques are also used in the fabrication of flat panel displays using a wide variety & of technologies, as well as in the fabrication of microelectromechanical systems (“MEMS").
• MEMS microelectromechanical systems
• the germanium atoms are slightly larger than the silicon atoms, but the deposited heteroepitaxial silicon germanium is constrained to the smaller lattice constant of the silicon beneath it, the silicon germanium is compressively strained to a degree that varies as a function of the germanium content.
• the band gap for the silicon germanium layer decreases monotonically from 1.12 eV for pure silicon to 0.67 eV for pure germanium as the germanium content in the silicon germanium increases.
• tensile strain is provided in a thin single crystalline silicon layer by heteroepitaxially depositing the silicon layer onto a relaxed silicon germanium layer.
• the heteroepitaxially deposited silicon is strained because its lattice constant is constrained to the larger lattice constant of the relaxed silicon germanium beneath it.
• the tensile strained heteroepitaxial silicon typically exhibits increased electron mobility. In both of these approaches, the strain is developed at the substrate level before the device (for example, a transistor) is fabricated.
• strain is introduced into single crystalline silicon-containing materials by replacing silicon atoms with other atoms in the lattice structure.
• This technique is typically referred to as substitutional doping.
• substitution of germanium atoms for some of the silicon atoms in the lattice structure of single crystalline silicon produces a compressive strain in the resulting substitutional ⁇ doped single crystalline silicon material because the germanium atoms are larger than the silicon atoms that they replace. It is possible to introduce a tensile strain into single crystalline silicon by substitutional doping with carbon, because carbon atoms are smaller than the silicon atoms that they replace.
• electrical dopants should also be substitutional ⁇ incorporated into epitaxial layers in order to be electrically active. Either the dopants are incorporated as deposited or they will need to be annealed to achieve the desired level of substitutionality and dopant activation. In situ doping of either impurities for tailored lattice constant or electrical dopants are often preferred over ex situ doping followed by annealing to incorporate the dopant into the lattice structure because the annealing consumes thermal budget.
• in situ substitutional doping is complicated by the tendency for the dopant to incorporate non-substitutionally during deposition, for example, by incorporating interstitially in domains or clusters within the silicon, rather than by substituting for silicon atoms in the lattice structure.
• Non-substitutional doping complicates, for example, carbon doping of silicon, carbon doping of silicon germanium, and doping of silicon and silicon germanium with electrically active dopants.
• a method for selectively forming semiconductor material in semiconductor windows.
• the method includes providing a substrate within a chemical vapor deposition chamber, where the substrate comprises insulating surfaces and single-crystal semiconductor surfaces.
• Semiconductor material is blanket deposited over the insulating surfaces and the single-crystal semiconductor surfaces of the substrate, such that a thickness ratio of non-epitaxial semiconductor material over the insulating surfaces to epitaxial semiconductor material over the single-crystal semiconductor surfaces is less than about 1.6:1.
• Non-epitaxial semiconductor material is selectively removed from over the insulating surfaces, wherein blanket depositing and selectively removing are conducted within the chemical vapor deposition chamber.
• a method for selectively forming epitaxial semiconductor material.
• Semiconductor material is blanket deposited to form epitaxial material over single-crystal semiconductor regions of a substrate and to form non-epitaxial material over insulating regions of the substrate.
• the non-epitaxial material is selectively removed from over the insulating regions by exposing the blanket deposited semiconductor material to an etch chemistry including a halide source and a germanium source. Blanket depositing and selectively removing are repeated at least once.
• a method for forming silicon-containing material in selected locations on a substrate.
• the method includes providing a substrate having exposed windows of single-crystal semiconductor among field isolation regions. Silicon-containing material is blanket deposited over the windows of single-crystal material and the field isolation regions by flowing trisilane over the substrate. The silicon- containing material is selectively removed from over the field isolation regions. Blanket depositing and selectively removing are repeated in a plurality of cycles.
• a method for selectively forming epitaxial semiconductor material.
• the method includes providing a substrate with insulating regions and semiconductor windows formed therein. Amorphous semiconductor material is deposited over the insulating regions and the epitaxial semiconductor material is deposited over the semiconductor windows. The amorphous semiconductor material is selectively etched from over the insulating regions while leaving at least some epitaxial semiconductor material in the semiconductor windows. Blanket depositing and selectively removing are repeated in a plurality of cycles.
• Figure 1 is a flowchart illustrating a process for selectively forming epitaxial semiconductor layers, using the particular example of depositing a carbon-doped silicon film in recessed source/drain regions of a mixed substrate.
• Figure 2 is a schematic illustration of a partially formed semiconductor structure comprising patterned insulator regions formed in a semiconductor substrate.
• Figure 3 is a schematic illustration of the partially formed semiconductor structure of Figure 2 after performing a blanket deposition of a carbon-doped silicon film over the mixed substrate surface.
• Figure 4 is a schematic illustration of the partially formed semiconductor structure of Figure 3 after performing a selective chemical vapor etch process to remove carbon-doped silicon from oxide regions of the mixed substrate.
• Figures 5A-5D are schematic illustrations of the partially formed semiconductor structure of Figure 4 after performing further cycles of blanket deposition and selective etch.
• Figure 6 shows a graph of etch rate of amorphous regions of a carbon-doped silicon film as a function of HCt partial pressure in the etch chemistry.
• Figure 7 shows a graph of etch rates and ratios amorphous (“a”) and single crystal (“c") etch rates as a function of GeH 4 flow in the etch chemistry for various etch chemistries.
• Figure 8 shows a graph of etch rate of amorphous regions of a carbon-doped silicon film as a function of chamber pressure.
• Figure 9 shows a graph of etch rate of amorphous regions of a carbon-doped silicon film as a function of reciprocal temperature.
• Figure 10 shows a graph of thickness of amorphous regions of a carbon-doped silicon film as a function of accumulated etch time.
• Figure 11 shows a graph of etch rate of amorphous regions of a carbon-doped silicon film deposited on a wafer as a function of radial position on the wafer.
• Figure 12 shows a graph of thickness of amorphous regions of a carbon-doped silicon film deposited on a wafer as a function of radial position on the wafer for various etch cycle durations.
• Figure 13 shows a graph of thickness of amorphous regions of a carbon-doped silicon film deposited of a wafer as a function of radial position of the wafer for various GeH 4 etchant etch chemistries and various etch cycle durations.
• Figure 14 is a micrograph illustrating an example partially formed carbon-doped silicon structure created by performing blanket deposition and a partial etch cycle on a patterned substrate.
• Figure 15 shows a graph of element concentration as a function of depth for an exemplary partially formed carbon-doped silicon film formed using certain of the techniques disclosed herein.
• Figure 16 is a micrograph illustrating an exemplary formed carbon-doped silicon structure created by performing multiple deposition and etch cycles on a patterned substrate.
• Figure 17 illustrates an atomic force microscopy analysis of an epitaxial carbon-doped silicon film that has been selectively formed using certain of the cyclical techniques disclosed herein.
• Figure 18 shows x-ray diffraction rocking curves of carbon- doped silicon films deposited using certain of the cyclical techniques disclosed herein.
• Deposition techniques often attempt to tailor the amount or kind of deposition in different regions of a substrate.
• U.S. Patent No. 6,998,305 recognizes that simultaneous etch and deposition reactions are know for selective deposition on silicon without depositing on silicon oxide.
• the '305 patent teaches cyclically alternating a selective deposition with an etch phase.
• the inventors have recognized that selective deposition chemistries sometimes have undesirably effects on the deposited layers.
• Deposition methods exist that are useful for making a variety of substitutional ⁇ doped single crystalline silicon-containing materials. For example, it is possible to perform in situ substitutional carbon doping of crystalline silicon by performing the deposition at a relatively high rate using trisilane (S1 3 H 8 ) as a silicon source and a carbon-containing gas or vapor as a carbon source. Carbon-doped silicon-containing alloys have a complementary nature to silicon germanium systems. The degree of substitutional doping is 70% or greater, expressed as the weight percentage of substitutional carbon dopant based on the total amount of carbon dopant (substitutional and non- substitutional) in the silicon.
• trisilane S1 3 H 8
• Carbon-doped silicon-containing alloys have a complementary nature to silicon germanium systems.
• the degree of substitutional doping is 70% or greater, expressed as the weight percentage of substitutional carbon dopant based on the total amount of carbon dopant (substitutional and non- substitutional) in the silicon.
• silicon-containing material and similar terms are used herein to refer to a broad variety of silicon-containing materials including without limitation silicon (including crystalline silicon), carbon-doped silicon (Si:C), silicon germanium, and carbon-doped silicon germanium (SiGe:C).
• silicon including crystalline silicon
• carbon-doped silicon Si:C
• silicon germanium silicon germanium
• SiGe:C carbon-doped silicon germanium
• u Si:C and SiGe:C are not stoichiometric chemical formulas per se and thus are not limited to materials that contain particular ratios of the indicated elements. Furthermore, terms such as Si:C and SiGe:C are not intended to exclude the presence of other dopants, such that a phosphorous and carbon-doped silicon material is included within the term Si:C and the term Si:C:P. .
• the percentage of a dopant (such as carbon, germanium or electrically active dopant) in a silicon- containing film is expressed herein in atomic percent on a whole film basis, unless otherwise stated.
• Substrate refers either to the workpiece upon which deposition is desired, or the surface exposed to one or more deposition gases.
• the substrate is a single crystal silicon wafer, a semiconductor-on-insulator ("SOI") substrate, or an epitaxial silicon surface, a silicon germanium surface, or a III— V material deposited upon a wafer.
• Workpieces are not limited to wafers, but also include glass, plastic, or other substrates employed in semiconductor processing.
• a "mixed substrate” is a substrate that has two or more different types of surfaces.
• a mixed substrate comprises a first surface having a first surface morphology and a second surface having a second surface morphology.
• carbon-doped silicon-containing layers are selectively formed over single crystal semiconductor materials while minimizing, and more preferably avoiding, deposition over adjacent dielectrics or insulators.
• dielectric materials include silicon dioxide (including low dielectric constant forms such as carbon-doped and fluorine-doped oxides of silicon), silicon nitride, metal oxide and metal silicate.
• epitaxial epitaxially
• heteroepitaxial heteroepitaxially
• similar terms are used herein to refer to the deposition of a crystalline silicon-containing material onto a crystalline substrate in such a way that the deposited layer adopts or follows the lattice constant of the substrate. Epitaxial deposition is generally considered to be heteroepitaxial when the composition of the deposited layer is different from that of the substrate.
• a mixed substrate comprises a first surface having a first surface morphology and a second surface having a second surface morphology.
• surface morphology refers to the crystalline structure of the substrate surface.
• Amorphous and crystalline are examples of different morphologies.
• Polycrystalline morphology is a crystalline structure that consists of a disorderly arrangement of orderly crystals and thus has an intermediate degree of order.
• Single crystal morphology is a crystalline structure that has a high degree of long range order.
• Epitaxial films are characterized by a crystal structure and orientation that is identical to the substrate upon which they are grown, typically single crystal.
• the atoms in these materials are arranged in a lattice-like structure that persists over relatively long distances (on an atomic scale).
• Amorphous morphology is a non-crystalline structure having a low degree of order because the atoms lack a definite periodic arrangement. Other morphologies include microcrystalline and mixtures of amorphous and crystalline material.
• Non-epitaxial thus encompasses amorphous, polycrystalline, microcrystalline and mixtures of the same.
• single-crystal or “epitaxial” are used to describe a predominantly large crystal structure having a tolerable number of faults therein, as is commonly employed for transistor fabrication.
• the crystallinity of a layer generally falls along a continuum from amorphous to polycrystalline to single-crystal; a crystal structure is often considered single-crystal or epitaxial, despite low density faults.
• mixed substrates include without limitation single crystal/polycrystalline, single crystal/amorphous, epitaxial/polycrystalline, epitaxial/amorphous, single crystal/dielectric, epitaxial/dielectric, conductor/dielectric, and semiconductor/dielectric.
• mixed substrate includes substrates having more than two different types of surfaces. Methods described herein for depositing silicon-containing films onto mixed substrates having two types of surfaces are also applicable to mixed substrates having three or more different types of surfaces.
• tensile strained carbon-doped silicon films provide a tensile strained silicon channel with enhanced electron mobility, particularly beneficial for NMOS devices. This advantageously eliminates the need to provide a relaxed silicon germanium buffer layer to support the strained silicon layer.
• electrically active dopants are advantageously incorporated by in situ doping using dopant sources or dopant precursors. High levels of electrically active substitutional doping using phosphorous also contribute to tensile stress.
• Preferred precursors for electrical dopants are dopant hydrides, including n-type dopant precursors such as phosphine, arsenic vapor, and arsine.
• Silylphosphines for example (H 3 Si) 3 _ x PR x
• Phosphor and arsenic are particularly useful for doping source and drain areas of NMOS devices.
• SbH 3 and trimethylindium are alternative sources of antimony and indium, respectively.
• Such dopant precursors are useful for the preparation of preferred films as described below, preferably boron- , phosphorous-, antimony-, indium-, and arsenic-doped silicon, Si:C, silicon germanium and SiGe:C films and alloys.
• recessed source/drain regions by dry etching with subsequent HF cleaning and in situ anneal.
• deposition of a selectively grown, thin (between approximately 1 nm and approximately 3 nm) silicon seed layer helps reduce etch damage.
• a seed layer also helps to cover damage caused by prior dopant implantation processes.
• such a seed layer might be selectively deposited using simultaneous provision of HCf and dichlorosilane at a deposition temperature between about 700 0 C and about 800 0 C.
• a cyclical blanket deposition and etch process is illustrated in the flowchart provided in Figure 1 , and in the schematic illustrations of the partially formed semiconductor structures illustrated in Figure 2 though Figure 5D. While illustrated for use with Si:C deposition in recessed source/drain regions, it will be appreciated that the techniques described herein are advantageous for selective formation of epitaxial films in other circumstances, such as on active area islands surrounded by field isolation prior to any gate definition and without recessing.
• Figure 1 illustrates that a mixed substrate having insulator regions and recessed source/drain regions is placed in a process chamber in operational block 10.
• Figure 2 provides a schematic illustration of an exemplary mixed substrate that includes a patterned insulator 110 formed in a semiconductor substrate 100, such as a silicon wafer.
• the illustrated insulator 110 in the form of oxide-filled shallow trench isolation (STI), defines field isolation regions 112 and is adjacent recessed source/drain regions 114 shown on either side of a gate electrode 115 structure.
• the gate electrode 115 overlies a channel region 117 of the substrate.
• the channel 117, source and drain regions 114 define a transistor active area, which is typically surrounded by field isolation 112 to prevent cross-talk with adjacent devices.
• multiple transistors can be surrounded by field isolation.
• the top of the gate structure 115 can be capped with dielectric, as illustrated. This surface then behaves similarly to the field regions 110 with respect to the deposition there over, and the conditions that maintain selectivity in the field region will also apply to the top of the gate.
• the gate 115 is not capped with a dielectric, then the surface of the gate has the potential to grow polycrystalline material which then can be removed through in- situ etching of polycrystalline material, but a different set of selectivity conditions (pressure, gas flow, etc) would apply, compared to those used to ensure no residual polycrystalline material on the field 110.
• a blanket Si:C layer is then deposited over the mixed substrate using trisilane as a silicon precursor. This results in amorphous or polycrystalline (non-epitaxial) deposition 120 over oxide regions 112, and lower epitaxial deposition 125 and sidewall epitaxial deposition 130 over the recessed source/drain regions 114.
• bladenket deposition means that net deposition results over both the amorphous insulator 110 and the single crystal regions 114 in each deposition phase.
• etchant e.g., lack of halides
• some amount of etchant might be desirable to tune the ratio of deposited thickness over the various regions, as discussed in more detail below.
• the deposition process may be partially selective but nevertheless blanket, since each deposition phase will have net deposition over both the insulator 110 and single crystal region 114.
• amorphous or polycrystalline deposition 120 and the sidewall epitaxial deposition 130 are then selectively etched in an operational block 30 ( Figure 1 ), thus resulting in the structure that is schematically illustrated in Figure 4.
• the vapor etch chemistry preferably comprises a halide (e.g., fluorine-, bromine- or chlorine-containing vapor compounds), and particularly a chlorine source, such as HCI or CI2.
• the etch chemistry also contains a germanium source (e.g., a germane such as monogermane (GeH 4 ), GeCI 4 , metallorganic Ge precursors, solid source Ge) to improve etch rates.
• a germanium source e.g., a germane such as monogermane (GeH 4 ), GeCI 4 , metallorganic Ge precursors, solid source Ge
• the non-epitaxial material 120 is selectively removed, some epitaxial material is left and some is removed.
• the sidewall epitaxial layer 130 is of a different plane and is also more defective (due to growth rate differential on the two surfaces) than the lower epitaxial layer 125. Accordingly, the sidewall epitaxial layer 130 is more readily removed, along with the non-epitaxial material 120.
• each cycle of the process can be tuned to achieve largely bottom-up filling of the recesses 114.
• epitaxial material can be left by the process even on the sidewalls if it is of good quality and does not hinder the goals of the selective fill.
• This process is repeated until a target thickness of epitaxial Si:C film thickness is achieved over the recessed source/drain regions 114, as indicated by decisional block 40 ( Figure 1 ), and as schematically illustrated in Figure 5A (deposition of second cycle of blanket Si:C layer 120) and Figure 5B (etch of second cycle of SkC layer to leave layer of epitaxial Si:C with increased thickness of epitaxial layer 125 in recessed source/drain regions 114).
• Figure 5C illustrates the result of further cycle(s) to leave epitaxial refilled source/drain regions 114, where the selective epitaxial layers 125 are roughly coplanar with field oxide 110.
• Figure 5D illustrates the result of further cycle(s) to leave epitaxial layers 125 selectively as elevated source/drain regions 114.
• the selective formation process may further include addition cycles of blanket deposition and selective etch back from over dielectric regions, but without carbon doping to form a capping layer.
• the capping layer can be with or without electrical dopants.
• the portion of the elevated source/drain regions 125 of Figure 5D that is above the original substrate surface (i.e., above the channel 117) can be carbon-free, since it does not contribute to the strain on the channel 117.
• the deposited Si:C film optionally includes an electrically active dopant, particularly one suitable for NMOS devices, such as phosphorous or arsenic, thereby allowing phosphorous-doped Si:C films or arsenic doped Si:C films to be deposited (Si:C:P or Si:C:As films, respectively).
• an electrically active dopant particularly one suitable for NMOS devices, such as phosphorous or arsenic, thereby allowing phosphorous-doped Si:C films or arsenic doped Si:C films to be deposited (Si:C:P or Si:C:As films, respectively).
• the Si:C film is preferably deposited with an amorphous-to- epitaxial growth rate ratio that is preferably between about 1.0:1 and about 1.6:1 , more preferably between about 1.0:1 and about 1.3:1 , and most preferably between about 1.0:1 and about 1.1 :1 , such that the film thickness over insulator and over the recessed source/drain regions is about equal.
• Manipulating the amorphous (or more generally non-epitaxial) to epitaxial growth rate ratio advantageously enables manipulation of the facet angle at the interface between the amorphous and crystalline Si:C after the subsequent etch process, and also minimizes etch duration for removal, relative to greater thicknesses over the insulators.
• the amorphous regions of the Si:C deposition have little or no crystallinity (i.e., are predominantly amorphous), thus facilitating the subsequent etch in such regions. Furthermore, minimizing the excess of non- epitaxial deposition by bringing the ratio of thickness close to 1 :1 reduces the length of the etch phase needed to clear non-epitaxial deposition from the field regions (and optionally from the gate).
• the Si:C film is selectively etched from the mixed substrate using an in situ chemical vapor etching technique.
• the chemical vapor etching technique is optionally performed simultaneously with a brief temperature spike.
• the temperature spike is conducted using the process described in U.S. Patent Application Publication 2003/0036268 (filed 29 May 2002; Attorney Docket ASMEX.317A).
• a temperature spike can employ full power to the upper lamps for a short duration (for example, for about 12 to about 15 seconds) while decoupling the power ratio for the lower lamps.
• the wafer temperature can rapidly ramp up while the susceptor temperature lags significantly.
• the wafer temperature preferably increases from the loading temperature by between about 100 0 C and about 400 0 C, and more preferably by between about 200°C and about 350 0 C. Because of the short duration of the temperature spike and etch phase, the wafer is allowed to cool before the susceptor gets a chance to approach the peak temperature. In this way, it takes far less time for the wafer to cycle in temperature, as compared to simultaneously cycling the temperature of a more massive combination of wafer/susceptor together.
• An example reactor for use with this temperature spike technique is the EPSILON ® series of single wafer epitaxial chemical vapor deposition chambers, which are commercially available from ASM America, Inc. (Phoenix, AZ).
• the etch temperature is preferably kept low. Using a low temperature for the etch also reduces the likelihood that electrically active dopant atoms are deactivated during the etch. For example, etching with Ct 2 gas advantageously allows the etch temperature to be reduced, thus helping to maintain the substitutional carbon and electrically active dopants.
• Low temperatures for the etch phase enables roughly matching deposition phase temperatures while taking advantage of the high dopant incorporation achieved at low temperatures. Etch rates can be enhanced to allow these lower temperatures without sacrificing throughput by including a germanium source (e.g.
• Isothermal cyclical blanket deposition and etching means deposition and etching within ⁇ 50°C of one another, preferably within ⁇ 10°C, and most preferably setpoint temperature is within ⁇ 5°C for both steps.
• isothermal processing improves throughput and minimizes time for temperature ramping and stabilization.
• both blanket deposition and etching process are preferably "isobaric," i.e., within ⁇ 50 Torr of one another, preferably within ⁇ 20 Torr. Isothermal and/or isobaric conditions facilitate better throughput for avoiding ramp and stabilization times.
• the two-stage process of performing a blanket deposition followed by a selective etch is optionally repeated cyclically until a target epitaxial film thickness over the recessed source/drain regions is achieved.
• Example process parameters are summarized in Table A below, which lists both preferred operating points as well as preferred operating ranges in parentheses.
• the process conditions such as chamber temperature, chamber pressure and carrier gas flow rates — are preferably substantially similar for the deposition and the etch phases, thereby allowing throughput to be increased.
• the example below employs isothermal and isobaric conditions for both phases of the cycle. Other parameters are used in modified embodiments. TABLE A
• epitaxial Si:C is etched significantly slower than amorphous or polycrystalline Si:C in each etch phase (etch selectivity in the range of 10:1 — 30:1). Defective epitaxial material is also preferentially removed in the etch phases.
• the cyclical deposition and etch process conditions are tuned to reduce or eliminate net growth on the oxide while achieving net growth in each cycle in the epitaxial recessed source/drain regions. This cyclical process is distinguishable from conventional selective deposition processes in which deposition and etching reactions occur simultaneously.
• Tables B and C below give two examples of deposition and etch durations and resultant thicknesses using a recipe similar to that of Table A. The recipes are differently tuned to modulate both deposition and etch rates by increasing the partial pressure of the SiaH ⁇ and optimizing etchant partial pressures.
• the process parameters provided in Table A indicate a C ⁇ /HCt etch chemistry.
• between about 20 seem and about 200 seem of 10% GeH 4 is included in the etch chemistry as an etch catalyst.
• inclusion of a germanium source e.g.. a germane such as GeH 4 , GeCI 4 , metallorganic Ge precursors, solid source Ge
• germanium source e.g. a germane such as GeH 4 , GeCI 4 , metallorganic Ge precursors, solid source Ge
• use of germanium as a catalyst also advantageously allows lower etch temperatures to be used, and allows a temperature spike during etch to be omitted, as noted above in discussion of isothermal processing.
• Figure 6 shows a graph of etch rate of amorphous regions of a carbon-doped silicon film as a function of HCC partial pressure in the etch chemistry, at a constant temperature of 600 0 C.
• HCC partial pressure in the etch chemistry By decreasing the H 2 carrier flow, the partial pressure of HC? and GeH 4 is increased, thereby significantly increasing the amorphous etch rate in certain embodiments.
• Figure 6 indicates that inclusion of 20 seem of 10% GeH 4 in the etch chemistry (symbols T and ⁇ ) results in substantially higher amorphous etch rates.
• Figure 7 shows a graph of etch rate and amorphous/epitaxial etch rate ratio as a function of GeH 4 flow in the etch chemistry, at a constant temperature of 600 0 C, a constant H 2 carrier flow of 2 slm, and a constant chamber pressure of 64 Torr.
• Amorphous etch rates are indicated by the "a-" prefix in the legend
• epitaxial etch rates are indicated by the "c-” prefix in the legend
• etch rate ratios are indicated by "ER” in the legend.
• Increasing the GeH 4 flow causes the amorphous/epitaxial etch rate ratio to increase to a point, beyond which additional GeH 4 reduces etch selectivity.
• Figure 7 indicates that an etch chemistry comprising 200 seem HCt and approximately 30 to 40 seem of 10% GeH 4 produces an amorphous/epitaxial etch rate ratio that cannot be obtained with lower or higher GeH 4 flow rates.
• Figure 8 shows a graph of etch rate of amorphous regions of a Si:C film as a function of chamber pressure for various GeH 4 flow rates in the etch chemistry, at a constant temperature of 550 0 C, a constant H 2 carrier flow of 2 slm, and a constant HCf etchant flow of 200 seem.
• the chamber pressure beyond approximately 80 Torr, the dependence of the etch rate on the GeH 4 flow rate is reduced.
• the amorphous etch rate is increased by a factor of about two.
• Figure 9 shows a graph of etch rate of amorphous regions of a carbon-doped silicon film as a function of reciprocal temperature, at a constant chamber pressure of 64 Torr, a constant H 2 carrier flow of 2 slm, a constant HC£ etchant flow of 200 seem, and a constant GeH 4 etchant flow of 50 seem of 10% GeH/».
• the absolute etch rates are very high for these chemicals even at very low temperatures.
• Figure 10 shows a graph of thickness of amorphous regions of a carbon-doped silicon film as a function of accumulated etch time, at a constant chamber pressure of 64 Ton * , a constant chamber temperature of 550 0 C 1 a constant H2 carrier flow of 2 slm, and a constant HCt etchant flow of 200 seem.
• the slopes of the lines plotted in Figure 10 correspond to the etch rate of the amorphous Si:C film.
• the etch rate in the center of the deposited film is greater than the etch rate at the edge of the deposited film. Therefore, in a preferred embodiment the wafer is "overetched" to increase the likelihood that amorphous Si:C is removed from the slower-etching wafer edges.
• Figure 11 shows a graph of etch rate of amorphous regions of a carbon-doped silicon film deposited on a wafer as a function of radial position on the wafer, at a constant chamber temperature of 550 0 C, a constant chamber pressure of 64 Torr, a constant H 2 carrier flow of 2 slm, and a constant HCl etchant flow of 200 seem.
• Figure 11 indicates that the etch rate is slightly slower at the wafer edge than the wafer center.
• Figure 12 shows a graph of thickness of amorphous regions of a carbon-doped silicon film deposited on a wafer as a function of radial position on the wafer for various etch cycle durations, at a constant chamber temperature of 550 0 C, a constant chamber pressure of 80 Torr, a constant H 2 carrier flow of 2 slm, a constant HCl etchant flow of 200 seem, and a constant GeH 4 etchant flow of 6.5 seem.
• Figure 13 shows a graph of thickness of amorphous regions of a carbon-doped silicon film deposited on a wafer as a function of radial position of the wafer for various GeH 4 etchant etch chemistries and various etch cycle durations. As illustrated in Figure 13, longer etch cycles and higher GeH 4 flow rates leads to more nonuniform etching. In a modified embodiment, this effect is compensated for by providing a final etch cycle of extended duration, thereby providing sufficient "overetch” to remove amorphous Si:C remaining at the center of the wafer.
• each cycle preferably between about 1 nm/cycle and 10 nm/cycle, more preferably between about 2 nm/cycle and 5 nm/cycle.
• conditions similar to Table A have been used to achieve net deposition rates of 4-11 nm/min.
• Figure 14 is a photograph illustrating an example partially formed carbon-doped silicon structure created by performing one deposition cycle and one etch cycle on a patterned substrate. As illustrated, crystalline Si:C:P is present over an epitaxial substrate region, while amorphous Si:C:P is present over oxide. An amorphous pocket is present at the amorphous/epitaxial interface because deposition occurs at different growth rates depending on the exposed crystallographic orientation. In the structure illustrated in Figure 14, the ratio of amorphous etch rate to epitaxial etch rate is over 20.
• Figure 16 is a photograph illustrating an example partially formed carbon-doped silicon structure created by performing multiple deposition and etch cycles on a patterned substrate.
• Figure 17 illustrates an atomic force microscopy analysis of a epitaxial carbon-doped silicon film that has been selectively deposited using certain of the techniques disclosed herein.
• Figure 15 shows a graph of element concentration as a function of depth for an example partially formed carbon-doped silicon film formed using certain of the techniques disclosed herein.
• relatively modest levels of germanium are incorporated into the Si:C film due to GeH 4 use during the etch phase.
• the germanium incorporation is less than about 5 atomic %, more preferably less than about 2 atomic %, and most preferably less than about 1 atomic %.
• Figure 18 shows x-ray diffraction rocking curves of carbon- doped silicon films deposited using certain of the techniques disclosed herein.
• the curves indicate different quantities of deposition/etch cycles, and correspond to increasing monomethylsilane ("MMS”) flow rates, which corresponds to higher substitutional C concentrations in the silicon epitaxial film.
• MMS monomethylsilane
• the techniques disclosed herein for selective epitaxial deposition of Si:C films provide several advantages over conventional techniques. For example, cyclical removal of polycrystalline or amorphous Si:C from insulator regions helps to improve the interface between the amorphous Si:C and the epitaxial Si:C. In particular, the cyclical process allows epitaxial growth to occur in interface regions where non-epitaxial growth would otherwise occur. Furthermore, in embodiments wherein the temperature spike during etch is omitted, such that the etch cycle is conducted at a temperature that is equal to, or only slightly elevated from, the deposition cycle, lower temperatures lead to many advantages. Throughput is improved by minimizing temperature (and/or pressure) ramp and stabilization time.
• Deposition temperatures can still be low enough to achieve high (e.g., 1.0 - 3.6 at C%) substitutional carbon content, and a large portion of the substitutional carbon and electrically active dopants remain in place during the etch, thus resulting in high substitutional carbon and dopant concentrations in the resulting film.

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