CN104465657B - 互补tfet 及其制造方法 - Google Patents

互补tfet 及其制造方法 Download PDF

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CN104465657B
CN104465657B CN201310428652.0A CN201310428652A CN104465657B CN 104465657 B CN104465657 B CN 104465657B CN 201310428652 A CN201310428652 A CN 201310428652A CN 104465657 B CN104465657 B CN 104465657B
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肖德元
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

本发明公开了互补TFET及其制造方法。互补高迁移率TFET包括nTFET和pTFET。nTFET包括：InSb体区上方的第一金属栅，第一掺杂类型的InSb源区，和与第一掺杂类型不同的第二掺杂类型的InSb漏区。pTFET包括：GaSb体区上方的第二金属栅，第一掺杂类型的GaSb漏区，和与第一掺杂类型不同的第二掺杂类型的GaSb源区。

Description

互补TFET及其制造方法
技术领域
本发明涉及半导体器件及其制造方法，特别涉及互补隧穿场效应晶体管(TFET)及其制造方法。
背景技术
为了不断提高大规模集成电路性能并降低成本，传统MOSFET的特征尺寸不断缩小。然而，随着器件尺寸缩小到亚微米甚至纳米尺度，器件的短沟道效应等负面影响也愈加严重。可以通过采用TFET取代传统的MOSFET来减小短沟道效应的影响。
TFET本质上是一个栅控的反偏PIN二极管。一个典型的TFET沿沟道方向的截面图如图1所示，与常规MOSFET不同，TFET的源漏区掺杂类型是不同的，对于这个nTFET来说，N+掺杂区为漏区，P+掺杂区为源区。下面以图1的nTFET为例简要说明TFET的工作原理。开态时，如图2A所示，栅上加正偏压，使得沟道区的电势降低，源区和沟道区之间的势垒层变薄，由此电子可以从TFET的源区隧穿到沟道区，然后在电场作用下漂移到漏区。关态时，如图2B所示，源区和沟道区之间的势垒层较厚，不发生隧穿。
与常规MOSFET相比，TFET能够减小亚阈值摆幅SS(subthreshold swing)，由此能够进一步减小开态/关态电压摆幅。常规MOSFET源区注入基于扩散-漂移机制，载流子的费米-狄拉克分布使得SS与kT/q成正比，室温下SS的最小可能值为60mV/dec；而TFET源区注入基于隧穿机制，能够突破60mV/dec的限制。
TFET具有低漏电流、低SS和低功耗等优异特性。但是，由于现有的TFET多是基于横向隧穿的，受到隧穿面积和隧穿几率的限制，TFET面临着开态电流小的问题，极大地限制了TFET器件的应用。
发明内容
本发明的一个目的在于提供一种同时具备低SS和大开态电流等优点的TFET。本发明通过分别选择具备高电子或空穴迁移率，而同时又具备较窄的禁带宽度的半导体材料分别作为N型和P型隧穿场效应晶体管(TFET)的有源区材料，进而提高器件的开态电流。
根据本发明的第一方面，提供了一种包括nTFET和pTFET的互补TFET。nTFET可以包括InSb体区上方的第一金属栅、第一掺杂类型的InSb源区、和与第一掺杂类型不同的第二掺杂类型的InSb漏区。pTFET可以包括GaSb体区上方的第二金属栅、第一掺杂类型的GaSb漏区、和与第一掺杂类型不同的第二掺杂类型的GaSb源区。
优选地，nTFET还可以包括位于InSb体区与第一金属栅之间的高k氧化物。
优选地，pTFET还可以包括位于GaSb体区与第二金属栅之间的高k氧化物。
优选地，所述互补TFET是高迁移率TFET。
优选地，nTFET还可以包括位于高k氧化物和第一金属栅两侧的间隔物。
优选地，pTFET还可以包括位于高k氧化物和第二金属栅两侧的间隔物。
优选地，nTFET和pTFET可以位于Ge外延层上，SiGe缓冲层可以位于Si衬底和Ge外延层之间。
优选地，第一掺杂类型可以包括n型掺杂，第二掺杂类型可以包括p型掺杂。
优选地，第一掺杂类型可以包括p型掺杂，第二掺杂类型可以包括n型掺杂。
优选地，浅沟槽隔离物可以位于nTFET与pTFET之间，浅沟槽隔离物可以包括氧化物。
优选地，nTFET的源区和漏区的掺杂浓度均不小于1×1019cm-3，pTFET的源区和漏区的掺杂浓度均不小于1×1019cm-3。
根据本发明的第一方面，提供了一种制造互补TFET的方法，包括：提供基板；分别形成nTFET和pTFET的有源区；分别形成nTFET和pTFET的金属栅；以及分别形成nTFET的具有不同掺杂类型的源区和漏区以及pTFET的具有不同掺杂类型的漏区和源区，其中pTFET区的有源区由GaSb形成，nTFET区的有源区由InSb形成。
优选地，所述互补TFET是高迁移率TFET。
优选地，可以在nTFET的金属栅与有源区之间形成高k氧化物。
优选地，可以在pTFET的金属栅与有源区之间形成高k氧化物。
优选地，在nTFET和pTFET的要形成沟道区的区域上方分别形成nTFET和pTFET的金属栅(60a、60b)。
优选地，对nTFET和pTFET的要形成沟道区的区域两侧分别进行第一掺杂类型和与第一掺杂类型不同的第二掺杂类型的掺杂，从而形成nTFET的源区和漏区以及pTFET的漏区和源区(71a、71b；72a、72b)。
优选地，可以在nTFET的高k氧化物和金属栅两侧形成间隔物。
优选地，可以在pTFET的高k氧化物和金属栅两侧形成间隔物。
优选地，所述基板可以是沉积在Si衬底上的Ge外延层，并且在Si衬底和Ge外延层之间可以形成SiGe缓冲层。
优选地，分别通过选择性外延生长nTFET和pTFET的有源区。
优选地，在nTFET与pTFET之间形成浅沟槽隔离物(20)，所述浅沟槽隔离物包括氧化物。
优选地，第一掺杂类型可以包括n型掺杂，第二掺杂类型包括p型掺杂。
优选地，第一掺杂类型可以包括p型掺杂，第二掺杂类型可以包括n型掺杂。
优选地，nTFET的源区和漏区的掺杂浓度均不小于1×1019cm-3，pTFET的源区和漏区的掺杂浓度均不小于1×1019cm-3。
通过以下参照附图对本发明的示例性实施例的详细描述，本发明的其它特征及其优点将会变得清楚。
附图说明
构成说明书的一部分的附图描述了本发明的实施例，并且连同说明书一起用于解释本发明的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本发明，其中：
图1是示意性地示出现有技术中典型的TFET沿沟道方向的截面图。
图2A和2B是示意性地示出图1的nTFET的工作原理的示图。
图3是示出一些半导体材料在室温下载流子的迁移率与最低直接带隙能量E0之间的关系的示图。
图4是示意性地示出根据本发明的实施例的包括nTFET和pTFET的互补高迁移率TFET的示图。
图5是示意性地示出根据本发明的实施例的制造互补TFET的方法的流程图。
图6A至图6G是示意性地示出根据图5的方法在各个阶段得到的图案的截面图。
具体实施方式
现在将参照附图来详细描述本发明的各种示例性实施例。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不限制本发明的范围。
同时，应当明白，为了便于描述，附图中所示出的各个部分的尺寸并不是按照实际的比例关系绘制的。
以下对至少一个示例性实施例的描述实际上仅仅是说明性的，决不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为授权说明书的一部分。
在这里示出和讨论的所有示例中，任何具体值应被解释为仅仅是示例性的，而不是作为限制。因此，示例性实施例的其它示例可以具有不同的值。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步讨论。
图3示出一些半导体材料在室温下载流子的迁移率与最低直接带隙能量E0之间的关系。在图3中，实线为最小二次方拟合得到的关系：lnμ300K＝10.3-1.41E0。
从图3可以看出：GaSb作为一种窄禁带宽度直接带隙半导体材料在低电场下，具备高载流子(空穴)迁移率；而InSb作为一种窄禁带宽度直接带隙半导体材料在低电场下，具备高载流子(电子)迁移率。
因此，可以利用GaSb来形成pTFET，而利用InSb来形成nTFET。
图4示意性地示出根据本发明的实施例的包括nTFET和pTFET的互补高迁移率TFET。在图4中，nTFET和pTFET都处于开态。也就是说，对于nTFET，VG>0，VD>0；而对于pTFET，VG<0，VD<0。
作为一个示例，如图4所示的，nTFET可以包括InSb体区上方的第一金属栅、P+掺杂的InSb源区、和N+掺杂的InSb漏区；而pTFET可以包括GaSb体区上方的第二金属栅、P+掺杂的GaSb漏区、和N+掺杂的GaSb源区。
浅沟槽隔离物STI可以位于nTFET与pTFET之间，从而将nTFET与pTFET隔离。隔离浅沟槽隔离物可以包括氧化物。
第一金属栅和第二金属栅可以由NiAu或CrAu或其他金属形成。
P+掺杂和N+掺杂的掺杂浓度均不小于1×1019cm-3。
作为一个示例，nTFET和pTFET可以形成在由Si衬底/SiGe缓冲层/Ge外延层构成的基板上。
根据器件的设计和工作需要，可以在nTFET和pTFET的体区与金属栅之间形成高k氧化物。还可以根据需要在高k氧化物和金属栅两侧形成间隔物。
图5是示意性地示出根据本发明的实施例的制造互补TFET的方法的流程图。
图6A至图6G是示意性地示出根据图5的方法在各个阶段得到的图案的截面图。
下面参考图5所示出的流程图描述图6A至图6G所示的根据本发明的方法在各个阶段得到的图案的截面图。
首先，在步骤S1，提供基板10。
基板10可以由Si衬底11/SiGe缓冲层12/Ge外延层13构成，其中SiGe缓冲层的厚度可以在1-5μm的范围内，Ge外延层的厚度可以在1-5μm的范围内，如图6A所示。
然后，在步骤S2到S7，可以通过选择性外延生长分别形成nTFET和pTFET的有源区30、50。可以利用浅沟槽隔离物将nTFET与pTFET隔离。
在步骤S2，例如，可以在基板上图案化沉积浅沟槽隔离物20，以遮蔽要形成nTFET和pTFET中的一个的区域，例如遮蔽要形成nTFET的区域(简称nTFET区域)，如图6B所示。浅沟槽隔离物可以是氧化物。
接着，在步骤S3，在未被遮蔽的区域选择性外延生长pTFET和nTFET中的另一个的有源区，例如pTFET的GaSb有源区30，如图6C所示。GaSb有源区的厚度可以在10-1000nm的范围内。可以通过MBE或MOCVD外延生长GaSb有源区。
接下来，在步骤S4，可以利用厚度在10-100nm的氮化物作为遮蔽物40来遮蔽pTFET区域和浅沟槽隔离物的一部分。然后，在步骤S5，移除浅沟槽隔离物的未被遮蔽的部分，以便于生长nTFET的有源区，得到例如图6D所示的图案。
接下来，在步骤S6，在移除了浅沟槽隔离物的未被遮蔽的部分的区域选择性外延生长nTFET的InSb有源区50。InSb有源区的厚度可以在10-1000nm的范围内。可以通过MBE或MOCVD外延生长InSb有源区。
然后，在步骤S7，移除用于遮蔽pTFET区域和浅沟槽隔离物的一部分的遮蔽物40，从而形成通过浅沟槽隔离物STI隔离的GaSb有源区30和InSb有源区50，例如图6E所示。
然后，在步骤S8，在要形成nTFET和pTFET的沟道区的区域上方分别形成nTFET和pTFET的金属栅60a、60b，其中根据器件的设计和工作需要，可以在nTFET和pTFET的体区与金属栅之间形成高k氧化物61a、61b，如图6F所示。nTFET和pTFET的金属栅可以由NiAu或CrAu或其他金属形成。
接下来，在步骤S9，对nTFET和pTFET的沟道区的两侧分别进行不同类型的掺杂，从而形成nTFET和pTFET的漏区和源区71a、72a和71b、72b，其中，在进行掺杂前，可以在高k氧化物和金属栅两侧形成间隔物62a、62b进行保护，如图6G所示。对于P+掺杂，可以利用(Mg+，2-10keV，1×1015cm-2-5×1016cm-2)的离子注入方法；对于N+掺杂，可以利用(Si+，2-50keV，1×1015cm-2-5×1016cm-2)的离子注入方法。由此，可以使得P+掺杂和N+掺杂的掺杂浓度均不小于1×1019cm-3。
另外，在掺杂之后，根据需要还可以进行退火处理，以改善器件的性能。
至此，已经详细描述了根据本发明的互补高迁移率TFET及其制造方法。在本申请文件中，“第一……”和“第二……”可以可互换地设置。为了避免遮蔽本发明的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本发明的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本发明的范围。本领域的技术人员应该理解，可在不脱离本发明的范围和精神的情况下，对以上实施例进行修改。本发明的范围由所附权利要求来限定。

Claims (20)

1.一种互补TFET，包括：
nTFET，包括
InSb体区上方的第一金属栅(60a)，
第一掺杂类型的InSb源区(71a)，和
与第一掺杂类型不同的第二掺杂类型的InSb漏区(72a)；以及
pTFET，包括
GaSb体区上方的第二金属栅(60b)，
第一掺杂类型的GaSb漏区(72b)，和
与第一掺杂类型不同的第二掺杂类型的GaSb源区(71b)。
2.如权利要求1所述的互补TFET，其中，nTFET还包括位于InSb体区与第一金属栅之间的高k氧化物(61a)，pTFET还包括位于GaSb体区与第二金属栅之间的高k氧化物(61b)。
3.如权利要求1所述的互补TFET，其中，所述互补TFET是高迁移率TFET。
4.如权利要求2所述的互补TFET，其中，nTFET还包括位于高k氧化物和第一金属栅两侧的间隔物(62a)，pTFET还包括位于高k氧化物和第二金属栅两侧的间隔物(62b)。
5.如权利要求1所述的互补TFET，其中，nTFET和pTFET位于由Ge外延层(13)/SiGe缓冲层(12)/Si衬底(11)构成的基板上。
6.如权利要求1所述的互补TFET，其中，第一掺杂类型包括n型掺杂，第二掺杂类型包括p型掺杂。
7.如权利要求1所述的互补TFET，其中，第一掺杂类型包括p型掺杂，第二掺杂类型包括n型掺杂。
8.如权利要求1所述的互补TFET，其中，浅沟槽隔离物(20)位于nTFET与pTFET之间，所述浅沟槽隔离物包括氧化物。
9.如权利要求8所述的互补TFET，其中，nTFET的源区和漏区的掺杂浓度均不小于1×1019cm-3，pTFET的源区和漏区的掺杂浓度均不小于1×1019cm-3。
10.一种制造互补TFET的方法，包括：
提供基板(10)；
分别形成nTFET和pTFET的有源区(30、50)；
分别形成nTFET和pTFET的金属栅(60a、60b)；以及
分别形成nTFET的具有不同掺杂类型的源区和漏区以及pTFET的具有不同掺杂类型的漏区和源区(71a、71b；72a、72b)，
其中pTFET区的有源区由GaSb形成，nTFET区的有源区由InSb形成。
11.如权利要求10所述的方法，其中，所述互补TFET是高迁移率TFET。
12.如权利要求10所述的方法，其中，在nTFET的金属栅与有源区之间形成高k氧化物，在pTFET的金属栅与有源区之间形成高k氧化物。
13.如权利要求10所述的方法，其中：
在nTFET和pTFET的要形成沟道区的区域上方分别形成nTFET和pTFET的金属栅(60a、60b)；
对nTFET和pTFET的要形成沟道区的区域两侧分别进行第一掺杂类型和与第一掺杂类型不同的第二掺杂类型的掺杂，从而形成nTFET的源区和漏区以及pTFET的漏区和源区(71a、71b；72a、72b)。
14.如权利要求12所述的方法，其中，在nTFET的高k氧化物和金属栅两侧形成间隔物，在pTFET的高k氧化物和金属栅两侧形成间隔物。
15.如权利要求13所述的方法，其中，分别通过选择性外延生长nTFET和pTFET的有源区(30、50)。
16.如权利要求10所述的方法，其中，所述基板是沉积在Si衬底上的Ge外延层，并且在Si衬底和Ge外延层之间形成SiGe缓冲层。
17.如权利要求13所述的方法，其中，其中，第一掺杂类型包括n型掺杂，第二掺杂类型包括p型掺杂。
18.如权利要求13所述的方法，其中，第一掺杂类型包括p型掺杂，第二掺杂类型包括n型掺杂。
19.如权利要求10所述的方法，其中，其中，nTFET的源区和漏区的掺杂浓度均不小于1×1019cm-3，pTFET的源区和漏区的掺杂浓度均不小于1×1019cm-3。
20.如权利要求10所述的方法，其中，在nTFET与pTFET之间形成浅沟槽隔离物(20)，所述浅沟槽隔离物包括氧化物。
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