WO2018111226A1

WO2018111226A1 - Transistor with asymmetric threshold voltage channel

Info

Publication number: WO2018111226A1
Application number: PCT/US2016/066232
Authority: WO
Inventors: Chen-Guan LEE; Hsu-Yu Chang; Joodong Park; Walid M. Hafez; Chia-Hong Jan
Original assignee: Intel Corporation
Priority date: 2016-12-12
Filing date: 2016-12-12
Publication date: 2018-06-21

Abstract

Embodiments herein describe techniques for a transistor including a drain, a source, and a channel between the drain and the source. The channel may include a first channel portion and a second channel portion adjacent to the first channel portion. The transistor may include a gate, wherein the gate may include a first gate portion and a second gate portion, where the first gate portion may include a first metal, and the second gate portion may include a second metal different from the first metal. The first gate portion may overlap the first channel portion, and the first gate portion and the second gate portion may overlap the second channel portion.

Description

TRANSISTOR WITH ASYMMETRIC THRESHOLD VOLTAGE CHANNEL

Field

Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to transistors.

Background

Device scaling has reduced the channel length of a transistor to increase the operation speed and/or the number of components per chip. As the channel length of a transistor is reduced, the short-channel effects may arise. During the transistor operation, the carrier density and lateral electric field distribution across the channel may determine the device performance and short channel behavior. One undesirable effect of a short channel of a transistor is the reduction in the threshold voltage at which the transistor turns on. The reduced threshold voltage may cause the subthreshold leakage current of the transistor to increase, which may make the transistor difficult to turn off.

Brief Description of the Drawings

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

Figure 1 schematically illustrates a cross-section view of an example transistor having a drain, a source, a channel, and a gate with two portions, in accordance with some embodiments.

Figures 2(a)-2fe) schematically illustrate three-dimensional views of various example transistors having a gate with two portions over a channel, in accordance with some embodiments.

Figures 3fa)~3(d) schematically illustrate cross-section views of example transistors having a gate with multiple portions over a channel, in accordance with some embodiments.

Figure 4 schematically illustrates a process for forming a gate with multiple portions over a channel of a transistor, in accordance with some embodiments.

Figures Sfa)-S(h) schematically illustrate another process for forming a gate with multiple portions over a channel of a transistor, in accordance with some embodiments.

Figures 6(a)-6fh) schematically illustrate another process for forming a gate with multiple portions over a channel of a transistor, in accordance with some embodiments.

Figure 7 schematically illustrates an inferposer implementing one or more embodiments of the disclosure, in accordance with some embodiments.

Figure 8 schematically illustrates a computing device built in accordance with an embodiment of the disclosure, in accordance with some embodiments.

Detaiied Description

Described herein are systems and methods of design and fabrication of various transistors having a gate with multiple portions including different metal stacks. Device scaling has reduced the channel length of a transistor. With reduced channel length, the short channel effects may arise and may result in the reduction in the threshold voltage at which the transistor turns on. The reduced threshold voltage may cause the subthreshold leakage current of the transistor to increase. Lightly doped drain (LDD) approach may dope impurities into the channel region close to the source and/or the drain, to overcome or reduce the short channel effects by changing the composition of the channel. However, by changing the composition of the channel, LDD may degrade the performance of the transistor.

Embodiments of transistors herein may include a gate having multiple portions comprising different metal materials. The different metal materials of the gate portions may result in different work functions of the gate portions, which lead to different threshold voltages for channel portions overlapping with the different gate portions. Hence, the transistors may have different threshold voltages for different channel portions without changing the composition of the channel. As a result, the transistors may have reduced short channel effects without reduced performance.

in embodiments, a transistor may include a drain, a source, and a channel between the drain and the source. The channel may include a first channel portion and a second channel portion adjacent to the first channel portion. The transistor may further include a gate, wherein the gate may include a first gate portion and a second gate portion, where the first gate portion may include a first metal, and the second gate portion may include a second metal different from the first metal. The first gate portion may overlap the first channel portion, and the first gate portion and the second gate portion may overlap the second channel portion, in general, a first component overlaps a second component when the first component is located over the second component (e.g., such that it is possible to draw a straight vertical line connecting one point within the first component to another point within the second component).

In embodiments, the transistor may be any suitable transistor, including but not limited to a PMOS transistor, an NMOS transistor, a tunnel field-effect transistor, a strained silicon transistor, a quantum well or group lll-V transistor, or a dichalcogenide transistor. The gate may be oriented in a planar direction, a vertical direction, or as a gate over a fin.

in embodiments, a method for forming a transistor may include: forming a drain and a source in a substrate; forming a gate dielectric layer over a channel between the drain and the source; and forming a first metal layer for a gate over the gate dielectric layer. After the first metal layer is formed, the method may include removing a portion of the first metal layer with non-uniform metal recess, while leaving a first gate portion of the first metal layer on a side close to the source. The remaining first gate portion may overlap a first channel portion of the channel. The method may include further depositing a second metal layer next to the first gate portion to form a second gate portion of the gate. As a result, the second gate portion may overlap the first channel portion, and also overlap a second channel portion adjacent to the first channel portion.

In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, if will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details, in other instances, weil-known features are omitted or simplified in order not to obscure the illustrative implementations.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure. However, the order of description should not be construed to imply that these operations are necessarily order dependent, in particular, these operations may not be performed in the order of presentation.

For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

The terms "over," "under," "between," "above," and "on" as used herein may refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening features.

The description may use the phrases "in an embodiment," or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous.

The term "coupled with," along with its derivatives, may be used herein.

"Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term "directly coupled" may mean that two or more elements are in direct contact.

in various embodiments, the phrase "a first feature formed, deposited, or otherwise disposed on a second feature" may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

Where the disclosure recites "a" or "a first" element or the equivalent thereof, such disclosure includes one or more such elements, neither requiring nor excluding two or more such elements. Further, ordinal indicators (e.g., first, second, or third) for identified elements are used to distinguish between the elements, and do not indicate or imply a required or limited number of such elements, nor do they indicate a particular position or order of such elements unless otherwise specifically stated.

As used herein, the term "circuitry" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. As used herein, "computer-implemented method" may refer to any method executed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet, a laptop computer, a set-top box, a gaming console, and so forth.

implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate, in one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a siiicon-on-insulator substructure, in other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium anfimonide, lead teiluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lli-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure. A plurality of transistors, such as mefal-oxide-semiconductor field-effect transistors ( OSFET or simply MOS transistors), may be fabricated on the substrate, in various implementations of the disclosure, the OS transistors may be planar transistors, nonpianar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the disclosure may also be carried out using nonpianar transistors.

Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si02) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor, in some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and oxygen-containing metal alloys such as conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a work function that is between about 4.9 eV and about 5.2 eV. For an N OS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbon-containing metal alloys such as metal carbides of these metals, for example hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a work function that is between about 3.9 eV and about 4.2 eV.

in some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a "ΙΓ- shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewali portions that are substantially perpendicular to the top surface of the substrate, in another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewali portions substantially perpendicular to the top surface of the substrate, in further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

in some implementations of the disclosure, a pair of sidewali spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewali spacers may be formed from materials such as silicon, nitrogen, carbon, and oxygen, for example silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewali spacers are well known in the art and generally include deposition and etching process steps, in an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewali spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process, in the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group Nl-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interiayer dielectrics (ILD) are deposited over the OS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. The dielectric materials may contain elements such as silicon, oxygen, carbon, nitrogen, fluorine, and hydrogen. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si02), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfiuorocyclobutane or polytetrafluoroethylene, fiuorosilicate glass (FSG), and organosilicates such as siisesquioxane, siioxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

Figure 1 schematically illustrates a cross-section view of an example transistor 100 having a drain 102, a source 103, a channel 150, and a gate 160 with two portions, in accordance with some embodiments.

in embodiments, the drain 102 and the source 103 may be formed within a substrate 101 , while the channel 1 50 may be formed between the drain 102 and the source 103. The gate 160 may be over the channel 150. in embodiment, the gate 160 may include a first gate portion 161 , and a second gate portion 162, while the channel 150 may include a first channel portion 151 and a second channel portion 152. In embodiments, the transistor 100 may further include a contact 1 1 1 formed on the drain 102 and a contact 121 formed on the source 103. A spacer 109 may separate the gate 160 and the contact 1 1 1 , and a spacer 1 19 may separate the gate 160 and the contact 121 .

In some embodiments, the substrate 101 may be a silicon substrate, or a siiicon-on-insulator (SOI) substrate. In other embodiments, the substrate 101 may be a suitable type of substrate such as a substrate formed from glass, ceramic, or one or more semiconductor materials. The substrate 101 may include the drain

102 and the source 103. in some embodiments, the drain 102 and/or the source

103 may be doped of either an n-type semiconductor or a p-type semiconductor.

The channel 150 may be formed between the drain 102 and the source 103. The channel 150 may include a first channel portion 151 and a second channel portion 152, where the second channel portion 152 may be adjacent to the first channel portion 151 . The first channel portion 151 may be next to the drain 102, and the second channel portion 152 may be next to the source 103. In embodiments, the first channel portion 151 and the second channel portion 152 may include a same or similar channel material, in embodiments, the channel 150 may include Si, GaAs, GaSb, In As, a nanowire, or a X2 material, where M is a transition metal Mo, W, or Ti, and X is a chaicogenide S or Se. With a same material in the first channel portion 151 and the second channel portion 152, embodiments herein may avoid the problems associated with LDD where the channel may have different materials in different channel regions.

The gate 160 may be located above the channel 150. In embodiments, the gate 160 may be oriented in a planar direction, a vertical direction, or over a fin. More details of a gate in different orientations are shown in Figures 2(a)-2(c). The gate 160 may include a first gate portion 161 and a second gate portion 162. The first gate portion 161 may include a first metal, while the second gate portion 162 may include a second metal different from the first metal, in embodiments, the first metal of the first gate portion 161 and/or the second metal of the second gate portion 162 may include any suitable metal material, for example, nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), tantalum (Ta), ruthenium, platinum, cobalt, hafnium, zirconium, titanium, aluminum, conductive metal oxides, e.g., ruthenium oxide, carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide, alloys of these metals, and/or combinations thereof.

in embodiments, the first gate portion 161 may overlap the first channel portion 151 and the second channel portion 1 52. On the other hand, the second gate portion 162 may overlap the second channel portion 152 without overlapping the first channel portion 151 , As a result, the first channel portion 151 may overlap with the first gate portion 161 but not the second gate portion 162, while the second channel portion 152 may overlap with the first gate portion 161 and the second gate portion 162. Hence, the metal stack overlapping the second channel portion 152 is different from the metal stack overlapping the first channel portion 151 . The threshold voltage of a channel or a portion of a channel may be related to the work function of the metal stack overlapping the channel or the channel portion. Accordingly, the first channel portion 151 may have a threshold voltage different from a threshold voltage of the second channel portion 152, due to the difference of the metal stack overlapping the two channel portions. In embodiments, a threshold voltage of the first channel portion 151 may be lower than a threshold voltage of the second channel portion 152. In some other embodiments, a threshold voltage of the first channel portion 151 may be higher than a threshold voltage of the second channel portion 152.

In addition, the transistor 100 may further include the spacer 109 around the gate 160, separating the gate 160 from the contact 1 1 1 for the drain 103 and the source 105.

in embodiments, the transistor 100 may be a transistor that uses an electric field to control the shape and hence the electrical conductivity of the channel 150 of one type of charge carrier in a semiconductor material. In embodiments, the transistor 100 may be a tunnel field-effect transistor, a strained silicon transistor, an lll-V transistor, a dichalcogenide transistor, a junctionless nanowire transistor, and/or another type of transistors.

Figures 2fa)-2(c) schematically illustrate three-dimensional views of various example transistors having a gate with two portions over a channel, in accordance with some embodiments. In embodiments, a gate may include multiple gates oriented in a planar direction (gate 261 ), a vertical direction (gate 263), and/or over a fin (gate 266). To have a better view, layers may be drawn in Figures 2fa)~2(c) with space in between. However, in embodiments, the layers may be in contact or there may be one or more layers between them, e.g., spacers, dielectrics, as appropriate.

Figure 2fa) illustrates a transistor 291 including a drain 202, a source 203, a channel 250, a gate 281 on top of the channel 250, and a gate 262 under the channel 250. In some other embodiments, the gate 262 may not exist and the transistor 291 may have only one gate 261 on top of the channel 250. In embodiments, the transistor 291 may be similar in function to the transistor 100 in Figure 1 . For example, the drain 202 may be similar in function to the drain 102, the source 203 may be similar in function to the source 103, the channel 250 may be similar in function to the channel 150, and the gate 261 may be similar in function to the gate 160.

In embodiments, the transistor 291 may be a strained silicon transistor and the channel 250 may be a strained silicon channel including Si (1 1 1 ). The gate 261 and the gate 262 may be oriented in a planar direction. Furthermore, the gate 261 may include a first gate portion 271 and a second gate portion 281 , where the first gate portion 271 may include a first metal, and the second gate portion 281 may include a second metal different from the first metal. The gate 262 may also include multiple gate portions, not shown. The number of portions of the gate 262 may be different from the number of portions of the gate 261 .

Accordingly, the channel 250 may include a first channel portion 251 overlapping with the first gate portion 271 only (e.g., not overlapping with the second gate portion 281 ), and a second channel portion 252 overlapping with both the first gate portion 271 and the second gate portion 281 . Due to the difference in the metal stack overlapping with the two channel portions, the first channel portion 251 and the second channel portion 252 may have different threshold voltages.

In addition, the transistor 291 may include a substrate, a buried oxide layer, a spacer, a contact, and/or other components, not shown.

Figure 2(b) illustrates a transistor 293 including a drain 204, a source 205, a channel 253, a gate 263 at one side of the channel 253, and a gate 264 at the other side of the channel 253. In embodiments, the transistor 293 may be similar in function to the transistor 100 in Figure 1 . For example, the drain 204 may be similar in function to the drain 102, the source 205 may be similar in function to the source 103, the channel 253 may be similar in function to the channel 150, and the gate 263 may be similar in function to the gate 160.

In embodiments, the transistor 293 may be an lil-V silicon transistor and the channel 253 may include GaAs. The gate 263 and the gate 264 may be oriented in a vertical direction. The gate 283 may include a first gate portion 273 and a second gate portion 283, where the first gate portion 273 may include a first metal, and the second gate portion 283 may include a second metal different from the first metal. The gate 264 may also include multiple gate portions, not shown, in some embodiments, the number of portions of the gate 264 may be different from the number of portions of the gate 263.

Accordingly, the channel 253 may include a first channel portion 254 overlapping with the first gate portion 273 only, and a second channel portion 255 overlapping with both the first gate portion 273 and the second gate portion 283. Due to the difference in the metal stack overlapping with the two channel portions, the first channel portion 254 and the second channel portion 255 may have different threshold voltages.

In addition, the transistor 293 may include a substrate, a buried oxide layer, a spacer, a contact, and other components, not shown.

Figure 2(c) illustrates a transistor 296 including a drain 206, a source 207, a channel 256, and a gate 266 which may be over a fin. In embodiments, the transistor 296 may be similar in function to the transistor 100 in Figure 1 . For example, the drain 206 may be similar in function to the drain 102, the source 207 may be similar in function to the source 103, the channel 256 may be similar in function to the channel 150, and the gate 266 may be similar in function to the gate 160.

in embodiments, the transistor 298 may be a Fin Field Effect Transistor (FinFET). Additionally, or alternatively, the channel 250 may include Germanium (Ge) or indium-gallium-arsenide (InGaAs). The gate 266 may include a first gate portion 278 and a second gate portion 286, where the first gate portion 276 may include a first metal, and the second gate portion 288 may include a second metal different from the first metal.

Accordingly, the channel 256 may include a first channel portion 257 overlapping with the first gate portion 276 only, and a second channel portion 258 overlapping with both the first gate portion 278 and the second gate portion 286. Due to the difference in the metal stack overlapping with the two channel portions, the first channel portion 257 and the second channel portion 258 may have different threshold voltage as well. in addition, the transistor 296 may include a substrate, a buried oxide layer, a spacer, a contact, and/or other components, not shown.

Figures 3fa)~3(d) schematically illustrate cross-section views of example transistors having a gate with multiple portions over a channel, in accordance with some embodiments. In embodiments, a gate may include two gate portions (e.g., a first gate portion 361 and a second gate portion 362 of the transistor 391 shown in Figure 3(a); or a first gate portion 365 and a second gate portion 366 of the transistor 393 shown in Figure 3(b)), or three gate portions (e.g., a first gate portion 381 , a second gate portion 382, and a third gate portion 383 of the transistor 395 shown in Figure 3(c); or a first gate portion 385, a second gate portion 386, and a third gate portion 387 of the transistor 397 shown in Figure 3(d)).

Figure 3fa) illustrates a transistor 391 including a drain 302, a source 303, a channel 330 including a first channel portion 351 and the second channel portion 352, and a gate 320 including the first gate portion 361 and the second gate portion 362. In embodiments, the transistor 391 may be similar to the transistor 100 in Figure 1 . For example, the drain 302 may be similar to the drain 102, the source 303 may be similar to the source 103, the channel 330 may be similar to the channel 150, and the gate 320 may be similar to the gate 160.

in embodiments, the gate 320 may include the first gate portion 361 and the second gate portion 362, where the first gate portion 361 may include a first metal, and the second gate portion 362 may include a second metal different from the first metal. Accordingly, the channel 330 may include the first channel portion 351 overlapping with the first gate portion 361 but not the second gate portion 362, and the second channel portion 352 overlapping with both the first gate portion 361 and the second gate portion 362. Due to the difference in the metal stack overlapping with the two channel portions, the first channel portion 351 and the second channel portion 352 may have different threshold voltages.

in embodiments, the second gate portion 362 may be of a quarter of a circle shape. In some other embodiments, the second gate portion 362 may be of a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides. The first gate portion 361 may be on a side surface and/or on a top surface of the second gate portion 362. in addition, the first gate portion 361 and the second gate portion 362 combined together may form a rectangle. In some other embodiments, the first gate portion 361 and the second gate portion 382 combined together may form a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

Figure 3(b) illustrates a transistor 393 including a drain 306, a source 307, a channel 332 including a first channel portion 355 and a second channel portion 358, a gate 322 including the first gate portion 365 and the second gate portion 368. In embodiments, the transistor 393 may be similar to the transistor 100 in Figure 1 . For example, the drain 308 may be similar to the drain 102, the source 307 may be similar to the source 103, the channel 332 may be similar to the channel 150, and the gate 322 may be similar to the gate 160.

In embodiments, the gate 322 may include the first gate portion 385 and the second gate portion 366, where the first gate portion 365 may include a first metal, and the second gate portion 366 may include a second metal different from the first metal. Accordingly, the channel 332 may include the first channel portion 355 overlapping with the first gate portion 365 but not the second gate portion 366, and the second channel portion 356 overlapping with both the first gate portion 365 and the second gate portion 366. Due to the difference in the metal stack overlapping with the two channel portions, the first channel portion 355 and the second channel portion 356 may have different threshold voltages.

in embodiments, the second gate portion 366 may be of a rectangular cross-sectional shape, different from the quarter of a circle cross-sectional shape of the second gate portion 362 shown in Figure 3(a). The first gate portion 385 may be on a side surface and on a top surface of the second gate portion 366. in addition, the cross-sectional shapes of the first gate portion 365 and the second gate portion 386 combined together may form a rectangle, in some other embodiments, the first gate portion 365 and the second gate portion 366 combined together may have any suitable cross-sectionai shape, such as a cross- sectional shape that forms a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

Figure 3(c) illustrates a transistor 395 including a drain 308, a source 309, a channel 334 including a first channel portion 371 , a second channel portion 372, and a third channel portion 373, and a gate 324 including a first gate portion 381 , a second gate portion 382, and a third gate portion 383. In embodiments, the transistor 395 may be similar to the transistor 100 in Figure 1 . For example, the drain 308 may be similar to the drain 102, the source 309 may be similar to the source 103, the channel 334 may be similar to the channel 150, and the gate 324 may be similar to the gate 160.

In embodiments, the gate 324 may include the first gate portion 381 , the second gate portion 382, and the third gate portion 383. The first gate portion 381 may include a first metal, the second gate portion 382 may include a second metal different from the first metal, and the third gate portion 383 may include a third metal different from the second metal, in embodiments, the first gate portion 381 , the second gate portion 382, and the third gate portion 383 may be of a rectangular cross-sectional shape. In some other embodiments, the first gate portion 381 , the second gate portion 382, and the third gate portion 383 may be of a different cross-sectional shape, such as a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides. Furthermore, the shape of the first gate portion 381 , the shape of the second gate portion 382, and the shape of the third gate portion 383 may be different from each other.

in embodiments, the channel 334 may include the first channel portion 371 overlapping with the first gate portion 381 only (e.g., not overlapping with the second gate portion 382 or the first gate portion 383), the second channel portion 372 overlapping with the first gate portion 381 and the second gate portion 382 but not the third gate portion 383, and the third channel portion 373 overlapping with the first gate portion 381 , the second gate portion 382, and the third gate portion 383. The first channel portion 371 may be between the drain 308 and the second channel portion 372. The second channel portion 372 may be between the first channel portion 371 and the third channel portion 373. The third channel portion 373 may be between the second channel portion 372 and the source 309. Due to the difference in the metal stack overlapping with the three channel portions, the first channel portion 371 , the second channel portion 372, and the third channel portion 373 may have different threshold voltages.

Figure 3(d) illustrates a transistor 397 including a drain 31 1 , a source 312, a channel 338 including a first channel portion 375 and a second channel portion 378, a gate 326 including the first gate portion 385, the second gate portion 388, and the third gate portion 387. In embodiments, the transistor 397 may be similar ΐο the transistor 100 in Figure 1 . For example, the drain 31 1 may be similar to the drain 102, the source 312 may be similar to the source 103, the channel 336 may be similar to the channel 150, and the gate 326 may be similar to the gate 160.

In embodiments, the gate 326 may include the first gate portion 385, the second gate portion 386, and the third gate portion 387. The first gate portion 385 may include a first metal, the second gate portion 386 may include a second metal different from the first metal, and the third gate portion 387 may include a third metal different from the first metal and the second metal. Accordingly, the channel 336 may include the first channel portion 375 overlapping with the first gate portion 385 without overlapping with the second gate portion 386, and the second channel portion 386 overlapping with both the first gate portion 385 and the second gate portion 386. In addition, the first channel portion 375 may overlap with the third gate portion 387 as well as the first gate portion 385. Therefore the threshold voltage of the first channel portion 375 may depend on the metal stack formed by the first gate portion 385 and the third gate portion 387. Similarly, the threshold voltage of the second channel portion 376 may depend on the metal stack formed by the first gate portion 385 and the second gate portion 386. Due to the difference in the metal stack overlapping with the two channel portions, the first channel portion 375 and the second channel portion 376 may have different threshold voltages.

in embodiments, the first gate portion 385, the second gate portion 386, and the third gate portion 387 may be of a rectangular shape. The first gate portion 385 may be on a top surface of the second gate portion 386 and the third gate portion 387, while the second gate portion 386 and the third gate portion 387 may be placed in parallel with contact on a side, in addition, the cross-sectional shapes of the first gate portion 385, the second gate portion 386, and the third gate portion 387 combined together may form a rectangle, in some other embodiments, the first gate portion 385, the second gate portion 386, and the third gate portion 387 combined together may form a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

Figure 4 schematically illustrates a process 400 for forming a gate with multiple portions over a channel of a transistor, in accordance with some embodiments, in embodiments, the process 400 may be applied to form the gate 160 over the channel 150 of the transistor 100, as shown in Figure 1 , where the gate 160 includes the first gate portion 161 and the second gate portion 162.

At block 401 , the process 400 may include forming a drain and a source in a substrate. For example, in embodiment, the process 410 may include forming the drain 102 and the source 103 in the substrate 101 as illustrated in Figure 1 .

At block 403, the process 400 may include forming a gate dielectric layer over a channel between the drain and the source. At block 405, the process 400 may include forming a first metal layer for a gate over the gate dielectric layer.

At block 407, the process 400 may include removing a portion of the first metal layer with non-uniform metal recess, while leaving a first gate portion of the first metal layer on a side close to the source, wherein the first gate portion overlaps a first channel portion of the channel. In embodiments, the process 400 may form the non-uniform metal recess by etching the first metal layer. The first gate portion may be a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

At block 409, the process 400 may include depositing a second metal layer next to the first gate portion to form a second gate portion of the gate, wherein the second gate portion overlaps the first channel portion, and overlaps a second channel portion adjacent to the first channel portion. In embodiments, the first gate portion and the second gate portion together may form a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides, in embodiments, the first gate portion and the second gate portion may be oriented in a planar direction, a vertical direction, and/or over a fin.

Figures 5fa)~5fh) schematically illustrate another process 500 for forming a gate with multiple portions over a channel of a transistor, in accordance with some embodiments, in embodiments, the process 500 may be applied to form the gate 160 over the channel 150 of the transistor 100, as shown in Figure 1 , where the gate 160 includes the first gate portion 161 and the second gate portion 162. in embodiments, the process 500 may be an example of the process 400 shown in Figure 4.

As shown in Figure 5(a), a drain 502 and a source 503 may be formed in a substrate 501 . A gate dielectric layer 504 may be formed on the substrate 501 . A spacer 508 may be formed around a contact 507 for the drain 502, and a spacer 505 may be formed around a contact 508 for the source 503. A dummy gate material may be removed to have a gate space 509.

As shown in Figure 5(b), a conformal amorphous Si film 510 may be deposited on the surface of the gate dielectric layer 504, the spacer 508, the spacer 505, the contact 507, and the contact 506.

As shown in Figure 5(c), the Si film 510 may be hardened to form a hardened part 51 1 at the side over the drain 502. in addition, the Si film 510 may also be hardened to form a hardened part 512, which is outside the gate area.

As shown in Figure 5(d), the part of the Si film 510 that is not hardened may be removed. The Si film 510 may be removed by a wet clean removal. As a result of the removal, only the hardened part 51 1 and the hardened part 512 may remain, and the dielectric layer 504 previously covered by the Si film 510 may be exposed.

As shown in Figure 5(e), a metal 513 may be deposited above the exposed dielectric layer 504, next to the harden part 51 1 and the spacer 505.

As shown in Figure 5(f), the hardened part 51 1 and the hardened part 512 of the Si film may be removed. In embodiments, the hardened part 51 1 and the hardened part 512 may be removed by wet clean.

As shown in Figure 5(g), the metal 513 may be partially removed with nonuniform metal recess, while leaving a remaining portion on a side close to the source 503. The remaining portion of the metal 513 may be a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides. The remaining portion of the metal 513 may form a first gate portion of a gate.

As shown in Figure 5(h), a second metal 514 may be deposited. The second metal 514 may be a different material from the metal 513. The second metal 514 may be deposited next to the remaining portion of metal 513 to form a second gate portion of a gate. In embodiments, the remaining portion of metal 513 and the second metal 514 together may form a gate in a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

Figures 6fa)~6fh) schematically illustrate another process 800 for forming a gate with multiple portions over a channel of a transistor, in accordance with some embodiments, in embodiments, the process 600 may be applied to form the gate having three gate portions. Compared to the process 500 shown in Figures 5(a)-5(h), the process 800 may include one additional metal layer formed for the gate.

As shown in Figure 6(a), a drain 602 and a source 603 may be formed in a substrate 601 . A gate dielectric layer 604 may be formed on the substrate 601 . A spacer 608 may be formed around a contact 607 for the drain 602, and a spacer 805 may be formed around a contact 608 for the source 603. A dummy gate material may be removed to have a gate space 609.

As shown in Figure 6(b), a metal 620 and a conformal amorphous Si film 610 may be deposited on the surface of the gate dielectric layer 604, the spacer 808, the spacer 605, the contact 607, and the contact 606. in embodiments, the metal 620 may be deposited first before the Si film 610 is deposited. Compared to the operations shown in Figure 5(b), the metal 820 is the additional metal layer formed for the process 600.

As shown in Figure 8(c), the Si film 810 may be hardened to form a hardened part 81 1 at the side over the drain 802. in addition, the Si film 610 may also be hardened to form a hardened part 612, which is outside the gate area.

As shown in Figure 6(d), the part of the Si film 610 that is not hardened may be removed. The Si film 810 may be removed by a wet clean removal. As a result of the removal, only the hardened part 81 1 and the hardened part 812 may remain, and the metal 620 previously covered by the Si film 610 may be exposed.

As shown in Figure 8(e), a metal 613 may be deposited above the exposed dielectric metal 620, next to the harden part 61 1 and the metal 620. The metal 613 may include a material different from the metal 620.

As shown in Figure 6(f), the hardened part 61 1 and the hardened part 812 of the Si film may be removed. In embodiments, the hardened part 81 1 and the hardened part 612 may be removed by wet clean.

As shown in Figure 6(g), the metal 613 and the metal 620 may be partially removed with non-uniform metal recess, while leaving a remaining portion on a side close to the source 603. The remaining portion of the metal 813 may be a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides. The remaining portion of the metal 820 and the remaining portion of the metal 613 may form a first gate portion of a gate and a second gate portion of the gate. As shown in Figure 6(h), a third metal 814 may be deposited. The third metal 614 may be a different material from the metal 613. The third metal 614 may be deposited next to the remaining portion of metal 613 and the remaining portion of metal 620 to form a third gate portion of the gate. In embodiments, the remaining portion of metal 820, the remaining portion of metal 613 and the second metal 614 together may form a gate in a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

Figure 7 illustrates an interposer 700 that includes one or more embodiments of the disclosure. The interposer 700 is an intervening substrate used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 may be, for instance, an integrated circuit die. The second substrate 704 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 700 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 700 may couple an integrated circuit die to a ball grid array (BGA) 706 that can subsequently be coupled to the second substrate 704. in some embodiments, the first and second substrates 702/704 are attached to opposing sides of the interposer 700. in other embodiments, the first and second substrates 702/704 are attached to the same side of the interposer 700. And in further embodiments, three or more substrates are interconnected by way of the interposer 700.

The interposer 700 may be formed of an epoxy resin, a fiberglass- reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. in further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III- V and group IV materials.

The interposer may include metal interconnects 708 and vias 710, including but not limited to through-silicon vias (TSVs) 712. The interposer 700 may further include embedded devices 714, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (BSD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and EMS devices may also be formed on the interposer 700.

In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer 700.

Figure 8 illustrates a computing device 800 in accordance with one embodiment of the disclosure. The computing device 800 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as a SoC used for mobile devices. The components in the computing device 800 include, but are not limited to, an integrated circuit die 802 and at least one communications logic unit 808. In some implementations the communications logic unit 808 is fabricated within the integrated circuit die 802 while in other implementations the communications logic unit 808 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 802. The integrated circuit die 802 may include a CPU 804 as well as on-die memory 806, often used as cache memory, which can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT- MRAM).

Computing device 800 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within a SoC die. These other components include, but are not limited to, volatile memory 810 (e.g., DRAM), non-volatile memory 812 (e.g., ROM or flash memory), a graphics processing unit 814 (GPU), a digital signal processor 818, a crypto processor 842 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 820, at least one antenna 822 (in some implementations two or more antenna may be used), a display or a touchscreen display 824, a touchscreen controller 826, a battery 828 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 828, a compass 830, a motion coprocessor or sensors 832 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 834, a camera 836, user input devices 838 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 840 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 800 may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device 800 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 800 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.

The communications logic unit 808 enables wireless communications for the transfer of data to and from the computing device 800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communications logic unit 808 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.1 1 family), Wi AX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 800 may include a plurality of communications logic units 808. For instance, a first communications logic unit 808 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 808 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 804 of the computing device 800 includes one or more devices, such as transistors, that are formed in accordance with embodiments of the current disclosure, e.g. , transistors 100, 291 , 293, 298, 391 , 393, 395, 397, and/or a transistor fabricated using the process 400, the process 500, or the process 600. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communications logic unit 808 may also include one or more devices, such as transistors, that are formed in accordance with embodiments of the current disclosure, e.g. , transistors 100, 291 , 293, 296, 391 , 393, 395, 397, and/or a transistor fabricated using the process 400, the process 500, or the process 800.

in further embodiments, another component housed within the computing device 800 may contain one or more devices, such as transistors, that are formed in accordance with implementations of the current disclosure, e.g., transistors 100, 291 , 293, 296, 391 , 393, 395, 397, and/or a transistor fabricated using the process 400, the process 500, or the process 600.

In various embodiments, the computing device 800 may be a laptop computer, a netbook computer, a notebook computer, an uitrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 800 may be any other electronic device that processes data.

The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

Some non-limiting Examples are provided be!ow.

Example 1 may include a semiconductor device, comprising: a drain; a source; a channel between the drain and the source, wherein the channel includes a first channel portion and a second channel portion adjacent to the first channel portion; and a gate, wherein the gate includes a first gate portion and a second gate portion, the first gate portion includes a first metal, the second gate portion includes a second metal different from the first metal, the first gate portion overlaps the first channei portion, and the first gate portion and the second gate portion overlap the second channei portion.

Example 2 may include the semiconductor device of example 1 and/or some other examples herein, wherein the gate further includes a third gate portion, the channei further includes a third channei portion adjacent to the second channel portion, the third gate portion includes a third metal different from the second metal, and wherein the third gate portion, the second gate portion, and the first gate portion overlap the third channei portion.

Example 3 may include the semiconductor device of example 1 and/or some other examples herein, wherein the first gate portion is on a side surface and on a top surface of the second gate portion.

Example 4 may include the semiconductor device of example 1 and/or some other examples herein, wherein the first gate portion and the second gate portion combined together form a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

Example 5 may include the semiconductor device of example 1 and/or some other examples herein, wherein the second gate portion is a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

Example 6 may include the semiconductor device of any of examples 1 -5 and/or some other examples herein, wherein the device is a tunnel field-effect transistor, a strained silicon transistor, an 11 l-V transistor, or a dichalcogenide transistor.

Example 7 may include the semiconductor device of any of examples 1 -5 and/or some other examples herein, wherein the gate is oriented in a planar direction, a vertical direction, or over a fin. Example 8 may include the semiconductor device of any of examples 1 -5 and/or some other examples herein, wherein the channel includes Si, GaAs, GaSb, InAs, a nanowire, or a MX2 material, where M is a transition metal Mo, W, or Ti, and X is a chaicogenide S or Se.

Example 9 may include the semiconductor device of any of examples 1 -5 and/or some other examples herein, wherein the first channel portion is next to the drain, and the second channel portion is next to the source.

Example 10 may include the semiconductor device of any of examples 1 -5 and/or some other examples herein, wherein the first channel portion is next to the drain, the second channel portion is next to the source, and a threshold voltage of the first channel portion is lower than a threshold voltage of the second channel portion.

Example 1 1 may include an electrical system comprising: a memory device, a display, and a processor coupled to the memory device and the display, the processor including a transistor, and the transistor including: a drain; a source; a channel between the drain and the source, wherein the channel includes a first channel portion and a second channel portion adjacent to the first channel portion; and a gate, wherein the gate includes a first gate portion and a second gate portion, the first gate portion includes a first metal, the second gate portion includes a second metal different from the first metal, the first gate portion overlaps the first channel portion, and the first gate portion and the second gate portion overlap the second channel portion.

Example 12 may include the electrical system of example 1 1 and/or some other examples herein, wherein the gate further includes a third gate portion, the channel further includes a third channel portion adjacent to the second channel portion, the third gate portion includes a third metal different from the second metal, and wherein the third gate portion, the second gate portion, and the first gate portion overlap the third channel portion.

Example 13 may include the electrical system of example 1 1 and/or some other examples herein, wherein the first gate portion is on a side surface and on a top surface of the second gate portion.

Example 14 may include the electrical system of example 1 1 and/or some other examples herein, wherein the first gate portion and the second gate portion combined together form a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

Example 15 may include the electrical system of example 1 1 and/or some other examples herein, wherein the second gate portion is a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

Example 16 may include the electrical system of any of examples 1 1 -15 and/or some other examples herein, wherein the transistor is a tunnel field-effect transistor, a strained silicon transistor, an l il-V transistor, or a dichaicogenide transistor,

Example 17 may include the electrical system of any of examples 1 1 -15 and/or some other examples herein, wherein the gate is oriented in a planar direction, a vertical direction, or over a fin.

Example 18 may include the electrical system of any of examples 1 1 -15 and/or some other examples herein, wherein the channel includes Si, GaAs, GaSb, InAs, a nanowire, or a X2 material, where M is a transition metal Mo, W, or Ti, and X is a chaicogenide S or Se.

Example 19 may include the electrical system of any of examples 1 1 -15 and/or some other examples herein, wherein the first channel portion is next to the drain, and the second channel portion is next to the source.

Example 20 may include the electrical system of any of examples 1 1 -15 and/or some other examples herein, wherein the first channel portion is next to the drain, the second channel portion is next to the source, and a threshold voltage of the first channel portion is lower than a threshold voltage of the second channel portion.

Example 21 may include a method for forming a semiconductor device, the method comprising: forming a drain and a source in a substrate; forming a gate dielectric layer over a channel between the drain and the source; forming a first metal layer for a gate over the gate dielectric layer; removing a portion of the first metal layer with non-uniform metal recess, while leaving a first gate portion of the first metal layer on a side close to the source, wherein the first gate portion overlaps a first channel portion of the channel; and depositing a second metal layer next to the first gate portion to form a second gate portion of the gate, wherein the second gate portion overlaps the first channel portion, and overlaps a second channel portion adjacent to the first channel portion.

Example 22 may include the method of example 21 and/or some other examples herein, wherein the first gate portion is a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

Example 23 may include the method of example 21 and/or some other examples herein, wherein the first gate portion and the second gate portion together form a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

Example 24 may include the method of any of examples 21 -23 and/or some other examples herein, wherein the first channel portion is next to the source, and the second channel portion is next to the drain.

Example 25 may include the method of any of examples 21 -23 and/or some other examples herein, wherein the first gate portion and the second gate portion are oriented in a planar direction, a vertical direction, or over a fin.

Various embodiments may include any suitable combination of the above- described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the "and" may be "and/or"). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.

The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various embodiments of the present disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

Claims What is claimed is:

1 . A semiconductor device, comprising:

a drain;

a source;

a channel between the drain and the source, wherein the channel includes a first channe! portion and a second channel portion adjacent to the first channel portion; and

a gate, wherein the gate includes a first gate portion and a second gate portion, the first gate portion includes a first metal, the second gate portion includes a second metal different from the first metal, the first gate portion overlaps the first channel portion, and the first gate portion and the second gate portion overlap the second channel portion.

2. The device of claim 1 , wherein the gate further includes a third gate portion, the channel further includes a third channel portion adjacent to the second channel portion, the third gate portion includes a third metal different from the second metal, and wherein the third gate portion, the second gate portion, and the first gate portion overlap the third channel portion.

3. The device of claim 1 , wherein the first gate portion is on a side surface and on a top surface of the second gate portion.

4. The device of claim 1 , wherein the first gate portion and the second gate portion combined together form a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

5. The device of claim 1 , wherein the second gate portion is a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

6. The device of any of claims 1 -5, wherein the device is a tunnel field- effect transistor, a strained silicon transistor, an lii-V transistor, or a

dichalcogenide transistor.

7. The device of any of claims 1 -5, wherein the gate is oriented in a planar direction, a vertical direction, or over a fin.

8. The device of any of claims 1 -5, wherein the channel includes Si, GaAs, GaSb, InAs, a nanowire, or a MX2 material, where M is a transition metal Mo, W, or Ti, and X is a chalcogenide S or Se.

9. The device of any of claims 1 -5, wherein the first channel portion is next to the drain, and the second channel portion is next to the source.

10. The device of any of claims 1 -5, wherein the first channel portion is next to the drain, the second channel portion is next to the source, and a threshold voltage of the first channel portion is lower than a threshold voltage of the second channel portion.

1 1 . An electrical system comprising:

a memory device,

a display, and

a processor coupled to the memory device and the display, the processor including a transistor, and the transistor including:

a drain;

a source;

a channel between the drain and the source, wherein the channel includes a first channel portion and a second channel portion adjacent to the first channel portion; and

12. The system of claim 1 1 , wherein the gate further includes a third gate portion, the channel further includes a third channel portion adjacent to the second channel portion, the third gate portion includes a third metal different from the second metal, and wherein the third gate portion, the second gate portion, and the first gate portion overlap the third channel portion.

13. The system of claim 1 1 , wherein the first gate portion is on a side surface and on a top surface of the second gate portion.

14, The system of claim 1 1 , wherein the first gate portion and the second gate portion combined together form a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

15. The system of claim 1 1 , wherein the second gate portion is a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

16. The system of any of claims 1 1 -15, wherein the transistor is a tunnel field-effect transistor, a strained silicon transistor, an lll-V transistor, or a dichalcogenide transistor.

17. The system of any of claims 1 1 -15, wherein the gate is oriented in a planar direction, a vertical direction, or over a fin.

18. The system of any of claims 1 1 -15, wherein the channel includes Si, GaAs, GaSb, InAs, a nanowire, or a MX2 material, where M is a transition metal Mo, W, or Ti, and X is a chalcogenide S or Se.

19, The system of any of claims 1 1 -15, wherein the first channel portion is next to the drain, and the second channel portion is next to the source.

20. The system of any of claims 1 1 -15, wherein the first channel portion is next to the drain, the second channel portion is next to the source, and a threshold voltage of the first channel portion is lower than a threshold voltage of the second channel portion.

21 . A method for forming a semiconductor device, the method

comprising:

forming a drain and a source in a substrate;

forming a gate dielectric layer over a channel between the drain and the source;

forming a first metal layer for a gate over the gate dielectric layer; removing a portion of the first metal layer with non-uniform metal recess, while leaving a first gate portion of the first metal layer on a side close to the source, wherein the first gate portion overlaps a first channel portion of the channel; and

depositing a second metal layer next to the first gate portion to form a second gate portion of the gate, wherein the second gate portion overlaps the first channel portion, and overlaps a second channel portion adjacent to the first channel portion.

22. The method of claim 21 , wherein the first gate portion is a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

23. The method of claim 21 , wherein the first gate portion and the second gate portion together form a triangular shape, a square, a rectangular shape, a circular shape, an elliptical shape, or a polygon comprising three or more sides.

24. The method of any of claims 21 -23, wherein the first channel portion is next to the source, and the second channel portion is next to the drain.

25. The method of any of claims 21 -23, wherein the first gate portion and the second gate portion are oriented in a planar direction, a vertical direction, or over a fin.