WO2018125212A1

WO2018125212A1 - Fin patterning for semiconductor devices

Info

Publication number: WO2018125212A1
Application number: PCT/US2016/069501
Authority: WO
Inventors: Mehmet O. BAYKAN; Leonard P. GULER; Anurag Jain; Gordon S. FREEMAN; Robert M. Bigwood
Original assignee: Intel Corporation
Priority date: 2016-12-30
Filing date: 2016-12-30
Publication date: 2018-07-05

Abstract

Embodiments herein describe techniques for forming multiple cut regions with orthogonal corners on multiple fins of a semiconductor device based on multiple masks formed by using sacrificial layers with embedded grating lines. A cut region with orthogonal corners on a fin may be formed based on a mask with the aid of the grating lines embedded within a sacrificial layer, where the irregular shape of the mask may land on the grating lines without affecting the cut region formed on the fin. Multiple cut regions formed by multiple masks may be accumulated on a sacrificial layer, which may act as an intermediate patterning layer. Multiple cut regions with orthogonal corners on multiple fins may be formed in a single pass based on the multiple cut regions accumulated on the intermediate patterning layer. Other embodiments may also be described and claimed.

Description

FIN PATTERNING FOR SEMICONDUCTOR DEVICES

Field

Embodiments of the present disclosure generally relate to the field of integrated circuits, and more particularly, to semiconductor devices including transistors.

Background

A fin field effect (FinFET) transistor may be a transistor built on a substrate with a gate normally wrapped around a fin-shaped channel between a source and a drain. In general, a FinFET transistor may have any fin-based, multi-gate transistor architecture. For a semiconductor device including FinFET transistors, fins are often first patterned in a grid as continuous lines. Unwanted sections of fins may then be removed by forming cut regions on the fins based on lithography masks, or simply masks. Often multiple masks may be used to form the desired cut regions on the fins. However, current lithography techniques have many limits. For example, it may be difficult to pattern an orthogonal corner of a cut region for a rectangular shaped fin using a mask. Instead, corner rounding effects with irregular shapes may be created for cut regions on the fins. In addition, multiple masks used in the formation of multiple cut regions on the fins in a semiconductor device may introduce compounded errors on the fins.

Brief Description of the Drawings

Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings.

Figure 1 schematically illustrates a three-dimensional view of an example semiconductor device having a gate and multiple fins, in accordance with some embodiments.

Figures 2(a)-2(c) schematically illustrate three-dimensional views and a cross- section view of an example semiconductor device including multiple fins covered by a first sacrificial layer and a second sacrificial layer with embedded grating lines to facilitate the formation of multiple cut regions with orthogonal comers on the multiple fins, in accordance with some embodiments.

Figures 3(a)-3(f) schematically illustrate top-down views of an example semiconductor device including multiple fins having multiple cut regions with orthogonal comers on the multiple fins based on multiple masks formed with the aid of grating lines embedded within a sacrificial layer, in accordance with some embodiments.

Figures 4(a)-4(h) schematically illustrate a process for forming an example semiconductor device including multiple fins having multiple cut regions with orthogonal corners on the multiple fins based on multiple masks formed by using a first sacrificial layer and a second sacrificial layer with embedded grating lines, in accordance with some embodiments.

Figure 5 schematically illustrates another process for forming an example semiconductor device including multiple fins having multiple cut regions with orthogonal comers on multiple fins based on multiple masks formed by using a first sacrificial layer and a second sacrificial layer with embedded grating lines, in accordance with some embodiments.

Figure 6 schematically illustrates an interposer implementing one or more embodiments of the disclosure, in accordance with some embodiments.

Figure 7 schematically illustrates a computing device built in accordance with an embodiment of the disclosure, in accordance with some embodiments.

Detailed Description

Described herein are systems and methods of design and fabrication of semiconductor devices including multiple fins having multiple cut regions with orthogonal corners on the multiple fins based on multiple masks formed by using sacrificial layers with embedded grating lines. A cut region with orthogonal comers on a fin may be formed based on a mask with the aid of the grating lines embedded within a sacrificial layer, where the irregular shape of the mask may land on the grating lines without affecting the cut region formed on the fin. Multiple cut regions formed by multiple masks may be accumulated on a sacrificial layer, which may act as an intermediate patterning layer. Multiple cut regions with orthogonal corners on multiple fins may be formed in a single pass based on the multiple cut regions accumulated on the intermediate patterning layer. In embodiments, two sacrificial layers may be presented to illustrate the techniques. However, there may be more than two sacrificial layers or less than two sacrificial layers in some embodiments. Techniques presented herein may reduce or eliminate corner rounding effects in the formation of multiple cut regions on multiple fins, hence providing higher process margin, with increased technology yield. In embodiments, a method for forming a semiconductor device may include: forming a first fin and a second fin over a substrate, wherein the first fin and the second fin may be in parallel along a first direction. The method may further include forming a first sacrificial layer of a first material over the first fin and the second fin, and forming a second sacrificial layer of a second material over the first sacrificial layer, where the second material may be different from the first material. In addition, within the second sacrificial layer, a plurality of grating lines, e.g., a first grating line and a second grating line, may be formed in parallel along a second direction orthogonal to the first direction. The plurality of grating lines may include a third material different from the second material. A first cut region may be formed in the second sacrificial layer based on a mask, between the first grating line and the second grating line. An irregular part of the mask may land on the first grating line or the second grating line, which is not removed. The first cut region in the second sacrificial layer may be over a portion of the first fin with orthogonal comers. Afterwards, the portion of the first fin may be removed to form a cut region with orthogonal corners on the first fin.

In embodiments, a method for forming a semiconductor device may include: forming a first fin and a second fin over a substrate, wherein the first fin and the second fin may be in parallel. The method may further include forming a first sacrificial layer of a first material over the first fin and the second fin, and forming a second sacrificial layer of a second material over the first sacrificial layer, where the second material may be different from the first material. A first cut region in the second sacrificial layer may be formed based on a first mask, and a second cut region in the second sacrificial layer may be formed based on a second mask. After both cut regions are formed on the second sacrificial layer, a first cut region in the first sacrificial layer and a second cut region in the first sacrificial layer may be formed simultaneously, following the first cut region and the second cut region in the second sacrificial layer. Therefore, multiple cut regions may be formed in a single pass based on the multiple cut regions accumulated on the second sacrificial layer, which may be viewed as an intermediate patterning layer.

In embodiments, a method for forming a semiconductor device may include: forming a first fin and a second fin over a substrate, wherein the first fin and the second fin may be in parallel along a first direction. The method may further include forming a first sacrificial layer of a first material over the first fin and the second fin, and forming a second sacrificial layer of a second material over the first sacrificial layer, where the second material may be different from the first material. In addition, within the second sacrificial layer, a plurality of grating lines, e.g., a first grating line, a second grating line, a third grating line, and a fourth grating line, may be formed in parallel along a second direction orthogonal to the first direction. The plurality of grating lines may include a third material different from the second material. A first cut region in the second sacrificial layer may be formed based on a first mask, between the first grating line and the second grating line. An irregular part of the first mask may land on the first grating line or the second grating line, which is not removed. The first cut region in the second sacrificial layer may be over a portion of the first fin with orthogonal corners. Afterwards, the portion of the first fin may be removed to form a cut region on the first fin with orthogonal comers. Similarly, a second cut region in the second sacrificial layer may be formed based on a second mask, between the third grating line and the fourth grating line. An irregular part of the second mask may land on the third grating line or the fourth grating line, which is not removed. The second cut region in the second sacrificial layer may be over a portion of the second fin with orthogonal corners. Afterwards, the portion of the second fin may be removed to form a cut region with orthogonal corners on the second fin.

In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure. However, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation.

For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms "over," "under," "between," "above," and "on" as used herein may refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening features.

The description may use the phrases "in an embodiment," or "in embodiments," which may each refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous.

The term "coupled with," along with its derivatives, may be used herein. "Coupled" may mean one or more of the following. "Coupled" may mean that two or more elements are in direct physical or electrical contact. However, "coupled" may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term "directly coupled" may mean that two or more elements are in direct contact.

In various embodiments, the phrase "a first feature formed, deposited, or otherwise disposed on a second feature" may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

Where the disclosure recites "a" or "a first" element or the equivalent thereof, such disclosure includes one or more such elements, neither requiring nor excluding two or more such elements. Further, ordinal indicators (e.g., first, second, or third) for identified elements are used to distinguish between the elements, and do not indicate or imply a required or limited number of such elements, nor do they indicate a particular position or order of such elements unless otherwise specifically stated.

As used herein, the term "circuitry" may refer to, be part of, or include an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group), and/or memory (shared, dedicated, or group) that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable hardware components that provide the described functionality. As used herein, "computer-implemented method" may refer to any method executed by one or more processors, a computer system having one or more processors, a mobile device such as a smartphone (which may include one or more processors), a tablet, a laptop computer, a set-top box, a gaming console, and so forth.

Implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.

A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the disclosure, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all- around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the disclosure may also be carried out using nonplanar transistors.

Each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si02) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and oxygen-containing metal alloys such as conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a work function that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbon-containing metal alloys such as metal carbides of these metals, for example hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a work function that is between about 3.9 eV and about 4.2 eV.

In some implementations, when viewed as a cross-section of the transistor along the source-channel-drain direction, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some implementations of the disclosure, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from materials such as silicon, nitrogen, carbon, and oxygen, for example silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistors.

The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. The dielectric materials may contain elements such as silicon, oxygen, carbon, nitrogen, fluorine, and hydrogen. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si02), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant. Figure 1 schematically illustrates a three-dimensional view of an example semiconductor device 100 including a gate 161 and a plurality of fins, e.g., a fin 151, a fin 153, a fin 155, and a fin 157, in accordance with some embodiments.

In embodiments, the semiconductor device 100 may include a substrate 101. The fin 151, the fin 153, the fin 155, and the fin 157 may be formed above the substrate 101. A gate electrode 161 may traverse the fin 151, the fin 153, the fin 155, and the fin 157. A spacer 163 may be disposed between the gate electrode 161, the fin 151, the fin 153, the fin 155, and the fin 157, around both side walls of the gate electrode 161. In embodiments, the fin 151, the fin 153, the fin 155, and the fin 157 may be in parallel along a first direction (e.g., y direction), while the gate electrode 161 may be along a second direction (e.g., x direction) orthogonal to the first direction. In embodiments, the first direction may be any of the three directions, e.g., x direction, y direction, or z direction with respect to the substrate 101, and the second direction may be orthogonal to the first direction.

The semiconductor device 100 may have one or more other layers, such as a gate insulating layer, an isolation layer, and/or another suitable layer, not shown for clarity. Although not shown, according to example embodiments, the semiconductor device 100 may further include a source region and a drain region doped with an impurity within the fin 151, the fin 153, the fin 155, or the fin 157 on both sides of the gate electrode 161. Furthermore, the semiconductor device 100 may include a channel region disposed below the gate electrode 161 within the fin 151, the fin 153, the fin 155, or the fin 157. There may be multiple FinFET transistors formed in the semiconductor device 100. For example, the source region, the drain region, the channel region within the fin 151, and the gate electrode 161 may form a FinFET transistor. More FinFET transistors may be similarly formed with other fins.

In some embodiments, the substrate 101 may be a silicon substrate, or a silicon- on-insulator (SOI) substrate. In detail, the substrate 101 may be formed of one or more semiconductor materials, e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, InP, and/or another suitable material.

The fin 151, the fin 153, the fin 155, or the fin 157 may be a portion of the substrate 101 or may include an epitaxial layer grown from the substrate 101. For example, the fin 151, the fin 153, the fin 155, or the fin 157 may be a portion of the substrate formed of a single crystal silicon (Si), and the epitaxial layer may be one of Ge, SiGe, SiC, or others. The gate electrode 161 may cover the fin 151, the fin 153, the fin 155, and the fin

157, extending in the second direction (e.g., x direction). In example embodiments, the gate electrode 161 may include doped poly crystalline silicon. In some other embodiments, the gate electrode 161 may include a metal or other conductive material. For example, the gate electrode 161 may include one or more of aluminum (Al), tungsten (W), molybdenum (Mo), nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), tantalum (Ta), ruthenium, platinum, cobalt, hafnium, zirconium, titanium, aluminum, conductive metal oxides, alloys of these metals, and/or combinations thereof. The spacer 163 disposed on both side walls of the gate electrode 161 may include one of a nitride layer and an oxynitride layer.

Figures 2(a)-2(c) schematically illustrate three-dimensional views and a cross- section view of an example semiconductor device 200 having multiple fins, e.g., a fin 251, a fin 253, a fine 255, and a fin 257, covered by a first sacrificial layer 270, and a second sacrificial layer 290 with embedded grating lines to facilitate the formation of multiple cut regions with orthogonal corners on the multiple fins, in accordance with some embodiments. In embodiments, the layers may be in contact or there may be one or more layers between them, e.g., spacers, dielectrics, as appropriate. The semiconductor device 200 may illustrate one stage of formation for the semiconductor device 100 shown in Figure 1.

Figure 2(a) illustrates a cross-section view of the semiconductor device 200 having a substrate 201. Multiple fins, such as the fin 251, the fin 253, the fine 255, and the fin 257, may be formed over the substrate 201, and included within a dielectric layer 250. In addition, the first sacrificial layer 270 and the second sacrificial layer 290 may be formed above the multiple fins. The arrangement of the semiconductor device 200 is described herein with reference to a first direction, a second direction, and a third direction, which are labeled in Figures 2(a)-(c). The first, second, and third directions may be orthogonal to one another. The first and second directions may be parallel to a plane of the substrate 201, and the third direction may be orthogonal to the plane of the substrate 201. In embodiments, the cross-section view of the semiconductor device 200 may be taken along the third direction.

In embodiments, the substrate 201 may be an example of the substrate 101, while the fin 251, the fin 253, the fine 255, and the fin 257, may be examples of the fin 151, the fin 153, the fin 155, and the fin 157, respectively, as shown in Figure 1. The first sacrificial layer 270 and the second sacrificial layer 290 may be used to facilitate the formation of multiple cut regions with orthogonal comers on the multiple fins, such as the fin 251, the fin 253, the fine 255, and the fin 257. The orthogonal corners on the multiple fins, such as the fin 251, the fin 253, the fine 255, and the fin 257, may be formed with the aid of multiple grating lines embedded within the second sacrificial layer 290, as shown in Figure 2(c).

In embodiments, the first sacrificial layer 270 may include a first material, and the second sacrificial layer 290 may include a second material different from the first material. The first sacrificial layer 270 and the second sacrificial layer 290 may have different materials so that selective etching may be used to form various cut regions on the second sacrificial layer 290 without affecting the first sacrificial layer 270. Therefore, multiple cut regions may be formed in the first sacrificial layer 270 or on the fins in a single pass based on the multiple cut regions accumulated on the second sacrificial layer 290, which may be viewed as an intermediate patterning layer.

In embodiments, the second sacrificial layer may include one of SiN, SiON, SiC, SiCN, SiOCN, SiOC, SiBN, SiBCN, or combinations thereof. On the other hand, the first sacrificial layer 270 may include TiN, which may be different from a material for the second sacrificial layer. In embodiments, the first sacrificial layer 270 may have a thickness ranging from about 1 nm to about 5 nm. The second sacrificial layer 290 may have a thickness ranging from about 1 nm to about 10 nm.

Figure 2(b) illustrates a three-dimensional view of the dielectric layer 250 including the multiple fins, e.g., the fin 251, the fin 253, the fine 255, and the fin 257. The multiple fins, e.g., the fin 251, the fin 253, the fine 255, and the fin 257 may be in parallel along the first direction (e.g., y direction), which may be orthogonal to a gate electrode (not shown) along the second direction. In embodiments, the first direction and the second direction are orthogonal to each other, and further orthogonal to the third direction shown in Figure 2(a) and Figure 2(b).

Figure 2(c) illustrates a three-dimensional view of the semiconductor device 200 on the substrate 201 with the dielectric layer 250 including multiple fins, e.g., the fin 251, the fin 253, the fine 255, and the fin 257. In addition, the first sacrificial layer 270 and the second sacrificial layer 290 may be above the multiple fins. The second sacrificial layer 290 may have multiple embedded grating lines, e.g., a grating line 291, a grating line 293, a grating line 295, and a grating line 297. The multiple grating lines, e.g., the grating line 291, the grating line 293, the grating line 295, and the grating line 297 may be oriented along the second direction (e.g., with a long axis of the grating line oriented in the second direction) orthogonal to the first direction and the third direction. In embodiments, the second direction may be along a gate electrode direction.

The multiple grating lines, e.g., the grating line 291, the grating line 293, the grating line 295, and the grating line 297 may include SiN, SiC, Si, SiO, TiN, CHM, or SiON. The material of the multiple grating lines may be different from the material for the second sacrificial layer 290, so that selective etching may be used to remove a part of the second sacrificial layer 290 without removing any part of the grating lines. The multiple grating lines, e.g., the grating line 291, the grating line 293, the grating line 295, may have a width of a critical dimension, which is the minimum feature size allowed by the lithographic technique.

Any two adjacent grating lines, e.g., the grating line 291 and the grating line 293 may be separated by a part of the second sacrificial layer 290, e.g., a part 292. Similarly, the grating line 293 and the grating line 295 may be separated by a part 294 of the second sacrificial layer 290, and the grating line 295 and the grating line 297 may be separated by a part 296 of the second sacrificial layer 290. Cut regions may be formed within the parts of the second sacrificial layer 290, e.g., the part 292, the part 294, or the part 296, without removing any material from the grating lines.

Figures 3(a)-3(f) schematically illustrate top-down views of an example semiconductor device 300 including multiple fins, e.g., a fin 351, a fin 353, a fine 355, and a fin 357, having multiple cut regions with orthogonal corners on the multiple fins, e.g., a cut region 331, a cut region 333, and a cut region 335, based on multiple masks, e.g., a mask 310, a mask 320, and a mask 330, formed with the aid of grating lines embedded within a sacrificial layer, e. g., a grating line 391, a grating line 393, a grating line 395, and a grating line 397 embedded within a sacrificial layer 390, in accordance with some embodiments. The semiconductor device 300 may illustrate one stage of formation for the semiconductor device 100 shown in Figure 1.

Figure 3(a) illustrates a top-down view of the semiconductor device 300 having a substrate 301. Multiple fins, such as the fin 351, the fin 353, the fine 355, and the fin 357, may be formed over the substrate 301. The multiple fins, e.g., the fin 351, the fin 353, the fine 355, and the fin 357 may be in parallel along a first direction (e.g., y direction), and may each have a rectangular shape.

In embodiments, the substrate 301 may be an example of the substrate 101, while the fin 351, the fin 353, the fine 355, and the fin 357, may be examples of the fin 151, the fin 153, the fin 155, and the fin 157, respectively, as shown in Figure 1. In embodiments, the fin 351, the fin 353, the fine 355, and the fin 357, may also be similar to the fin 251, the fin 253, the fin 255, and the fin 257, respectively, as shown in Figure 2.

In embodiments, the fin 351, the fin 355, and the fin 357 may initially be formed as continuous lines. The cut region 331, the cut region 335, and the cut region 337 may break the continuous fins into different sections to form different FinFET transistors on the substrate 301. In embodiments, the fin 351 may have the cut region 331 with orthogonal comers, e.g., an orthogonal comer 332. Similarly, the fin 355 may have a cut region 335, and the fin 357 may have a cut region 337, each with orthogonal corners. The cut region 331, the cut region 335, and the cut region 337 may be located at various portions of the fin 351, the fin 355, and the fin 357, respectively. The cut region 331, the cut region 335, and the cut region 337 may be of different length. The cut region 331 and the cut region 335 may have a same or similar processing variation, because they are formed by similar grating lines. For example, the cut region 331 and the cut region 335 may both have sharply orthogonal comers. Alternatively, the cut region 331 and the cut region 335 may still have slightly degree variations from sharply orthogonal corners, but the differences for the cut region 331 to sharply orthogonal corners may be similar to the differences for the cut region 335 to sharply orthogonal corners. In embodiments, the cut region 331, the cut region 335, and the cut region 337 may be formed based on one or more masks as shown in Figure 3(b) and Figure 3(c).

Figure 3(b) illustrates a partem of a mask 310, which may be used to form the cut region 331. The pattern of the mask 310 may be simply referred to as the mask 310. In order to form a cut region with orthogonal comers, e.g., the comer 332, the desired mask should have orthogonal corners. However, current lithography techniques may limit the ability to form a mask 310 with a rectangular shape. For example, the mask 310 shown in Figure 3(b) used to form the cut region 331 may not be a rectangular shape with orthogonal corners as desired to form the cut region 331. Instead, the mask 310 may have a rectangular portion 315, which represents the desired rectangle with orthogonal corners, surrounded by additional irregular parts, e.g., a part 312, a part 314, a part 316, and a part 318, having irregular shapes. The part 312 may be an irregular part located at the top of the rectangular portion 315. The part 314 may be an irregular part located at the bottom of the rectangular portion 315. The part 316 may be an irregular part located at the left of the rectangular portion 315. The part 318 may be an irregular part located at the right of the rectangular portion 315. The multiple parts, e.g., the part 312, the part 314, the part 316, and the part 318 are for illustration purposes only and are not limiting. For example, in some embodiments, the mask 310 may only have some irregular parts at the top or bottom of the rectangle center 315, e.g., the part 312 or the part 314. It should be noted that the rectangular portion 315 and parts 312, 314, 316, and 318 for a contiguous region of the opening of the mask 310 and are labeled and described separately for ease of understanding.

In embodiments, based on the mask 310, it may be difficult to pattern the orthogonal comer 332 of the cut region 331 on the fin 351 which is of a rectangular shape. Instead, corner rounding effects with irregular shapes may be created for cut regions on the fins. Grating lines embedded within a sacrificial layer may be used to aid the formation of the orthogonal comer 332 of the cut region 331 on the fin 351 based on the mask 310, as shown in Figure 3(c).

Figure 3(c) illustrates the semiconductor device 300 on the substrate 301 before the cut region 331, the cut region 335, and the cut region 337 are formed as shown in Figure 3(a). Multiple grating lines, e.g., a grating line 391, a grating line 393, a grating line 395, and a grating line 397 may be formed within a sacrificial layer, e.g., a sacrificial layer 390, above the multiple fins, e.g., the fin 351, the fin 353, the fin 355, and the fin 357. The multiple fins, e.g., the fin 351, the fin 353, the fin 355, and the fin 357 may be in parallel along a first direction (e.g., y direction). The multiple grating lines, e.g., the grating line 391, the grating line 393, the grating line 395, and the grating line 397 may be in parallel along a second direction (e.g., x direction) orthogonal to the first direction.

In embodiments, the grating line 391, the grating line 393, the grating line 395, and the grating line 397 may be embedded within the sacrificial layer 390, and separated by a part of the sacrificial layer 390. For example, the grating line 391 and the grating line 393 may be separated by a part 392 of the sacrificial layer 390. Similarly, the grating line 393 and the grating line 395 may be separated by a part 394 of the sacrificial layer 390, and the grating line 395 and the grating line 397 may be separated by a part 396 of the sacrificial layer 390. Cut regions may be formed within the parts of the second sacrificial layer 390. For example, the cut region 331 may be formed within the part 392 between the grating line 391 and the grating line 393.

The mask 320 may be placed over the fin 351 to form the intended cut region, e.g., the cut region 331, on the fin 351. The mask 330 may be placed over the fin 355 and the fin 357 to form the intended cut regions, e.g., the cut region 335 on the fin 355, and the cut region 337 on the fin 357. The mask 320 may have a rectangular portion 325, which overlaps with the intended cut region on the fin 351. In addition, the mask 320 may have irregular parts around the rectangular portion 325. Without the aid of the multiple grating lines, e.g., the grating line 391, the grating line 393, the grating line 395, and the grating line 397, the mask 320 and the mask 330 may create irregular cut regions on the fins.

Figure 3(d) illustrates the details of placing the mask 320 above the sacrificial layer 390, overlap with the fin 351 to create a cut region on the fin 351 with orthogonal comers, e.g., the comer 332 as shown in Figure 3(a).

The mask 320 may have the rectangle central 325 surrounded by irregular parts, e.g., an irregular part 322, an irregular part 324, an irregular part 326, and an irregular part 328. The rectangle center 325 of the mask 320 may be over a portion of the fin 351 to form the cut regions on the fin 351. The irregular part 326 and the irregular part 328 may not overlap with the fin 351, and would not have any impact on the cut region formed on the fin 351. On the other hand, the irregular part 322 and the irregular part 324 may form an irregular cut region on the fin 351 without the aid of grating lines. With the aid of the grating line 391 and the grating line 393, the irregular part 322 and the irregular part 324 may land on the grating line 391 and the grating line 393, respectively, so that they would not impact the cut region formed on the fin 351.

Figure 3(e) illustrates a cut region 340 formed in the part 392 of the sacrificial layer 390 between the grating line 391 and the grating line 393, based on the mask 320. The cut region 340 in the part 392 of the sacrificial layer 390 may be formed by selective etching based on a mask 320. The selective etching removes the material in the part 392 of the sacrificial layer 390 between the grating line 391 and the grating line 392 based on the mask 320. At the meantime, the grating line 391 and the grating line 392 are not removed during the selective etching because the grating line 391 and the grating line 392 includes a material different from the material for the sacrificial layer 390.

The cut region 340 may include a rectangular portion 345, an irregular part 346, and an irregular part 348, which are formed following the rectangle center 325, the irregular part 326, and the irregular part 328, of the mask 320 shown in Figure 3(d). The rectangular portion 345 may have orthogonal corners, e.g., a corner 334. The comer 334 may be formed along the grating line 391, and the projected edge of the fin 351. The irregular part 322 and the irregular part 324 of the mask 320 may land on the grating line 391 and the grating line 393, which may not create any impact or remove any part of the grating line 391 and the grating line 393, because the grating line 391 and the grating line 393 are formed by a material different from the material for the part 392. The rectangular portion 345 may have orthogonal comers and may be over a portion of the fin 351, while the irregular part 346 and the irregular part 348 of the cut region 340 in the sacrificial layer 390 may not overlap with the fin 351, hence creating no impact on the fin 351 cut regions.

Figure 3(f) illustrates the cut region 331 formed on the fin 351 with orthogonal comers, e.g., the comer 332, based on the cut region 340 on the sacrificial layer 390. The comer 332 may be formed following the comer 334 of the cut region 340 on the sacrificial layer 390. For the rectangle cut region 331, other orthogonal comers may be formed similarly. In embodiments, the comer 332 may be a sharply orthogonal comer instead of substantially orthogonal comer. Other comers of the cut region 331 may be sharply orthogonal as well. Without the use of the grating lines, e.g., the grating line 391, the grating line 393, the grating line 395, and the grating line 397 within the sacrificial layer 390, a comer of a cut region on a fin may be substantially orthogonal instead of sharply orthogonal as illustrated by the comer 332. Various processing variations and the irregular parts of the masks may make it difficult to make a sharply orthogonal comer, such as the comer 332, without the help of the grating lines.

Figures 4(a)-4(h) schematically illustrate a process 400 for forming an example semiconductor device, e.g., a semiconductor device 410, including multiple fins, e.g., a fin 451, a fin 453, a fin 455, and a fin 457, having multiple cut regions with orthogonal comers on the multiple fins based on multiple masks formed by using a first sacrificial layer and a second sacrificial layer with embedded grating lines, in accordance with some embodiments. The process 400 may illustrate a part of the formation for the semiconductor device 100 shown in Figure 1. Various suitable patterning techniques may be used to form the multiple cut regions, for example photolithographic techniques in combination with a photoresist and material removal by selective etching.

As shown in Figure 4(a), a substrate 401 may be provided. Multiple fins, e.g., the fin 451, the fin 453, the fin 455, and the fin 457 may be formed over the substrate 401, and included within a dielectric layer 450. In addition, a first sacrificial layer 470 and a second sacrificial layer 490 may be formed above the multiple fins. There may be grating lines embedded within the second sacrificial layer 490, as shown in Figure 2(c), Figure 3(c), or Figure 3(d).

In embodiments, the substrate 401 may be an example of the substrate 101, while the fin 451, the fin 453, the fin 455, and the fin 457, may be examples of the fin 151, the fin 153, the fin 155, and the fin 157, respectively, as shown in Figure 1. In embodiments, the fin 451, the fin 453, the fin 455, and the fin 457, may also be similar to the fin 251, the fin 253, the fin 255, and the fin 257, respectively, as shown in Figure 2.

A first patterning layer, e.g., a photoresist layer 413, may be formed over the second sacrificial layer 490. An opening 412 may be formed on the photoresist layer 413, based on a mask. The mask used to form the opening 412 may be similar to the mask 310 shown in Figure 3(b), or the mask 320 shown in Figure 3(c). For example, the mask forming the opening 412 may have irregular parts that are landed on grating lines embedded within the second sacrificial layer 490, as shown in Figure 3(d).

As shown in Figure 4(b), a first cut region, e.g., a cut region 442, may be formed in the second sacrificial layer 490, following the opening 412. The cut region 442 may be similar to the cut region 340 as shown in Figure 3(e). The cut region 442 may be formed by selective etching. In more detail, in the selective etching process, the etchant only removes the desired portions of the second sacrificial layer 490, e.g., the cut region 340 in the part 392 between the grating line 391 and the grating line 393, as shown in Figure 3(e). The embedded grating lines, e.g., the grating line 391 and the grating line 393 may remain intact. The etchant also leaves the first sacrificial layer 470 intact due to the different material included in the first sacrificial layer 470.

As shown in Figure 4(c), a second patterning layer, e.g., a photoresist layer 415, may be formed over the second sacrificial layer 490. An opening 414 may be formed on the photoresist layer 415, based on a mask. The mask used to form the opening 414 may be similar to the mask 330 shown in Figure 3(c). For example, the mask forming the opening 414 may land on grating lines embedded within the second sacrificial layer 490 so that the irregular parts of the mask land on the grating lines, as shown in Figure 3(d).

As shown in Figure 4(d), a second cut region, e.g., a cut region 444, may be formed in the second sacrificial layer 490, following the opening 414. The cut region 444 may be formed by selective etching. In more detail, in the selective etching process, the etchant only removes the desired portions of the second sacrificial layer 490, e.g., the cut region 340 in the part 392 between the grating line 391 and the grating line 393, as shown in Figure 3(e). The embedded grating lines, e.g., the grating line 391 and the grating line 393 may remain intact. The etchant also leaves the first sacrificial layer 470 intact due to the different material included in the first sacrificial layer 470.

As shown in Figure 4(e), the patterning layer, e.g., the photoresist layer 415 may be removed, exposing the second sacrificial layer 490 with two cut regions, the cut region 442 and the cut region 444 formed in the second sacrificial layer 490. In embodiment, there may be more than two cut regions formed in the second sacrificial layer 490. Therefore, the second sacrificial layer 490 may have two or more cut regions accumulated, and may act as an intermediate patterning layer.

As shown in Figure 4(f), a first cut region 482 and a second cut region 484 may be formed in the first sacrificial layer 470 in a single pass without using multiple masks. Therefore, the multiple cut regions formed on the first sacrificial layer 470 can reduce or eliminate the compounded errors introduced by multiple masks. The first cut region 482 and the second cut region 484 may be formed in the first sacrificial layer 470 by selective etching.

As shown in Figure 4(g), a cut region 486 on the fin 451, a cut region 488 on the fin 455, and a cut region 489 on the fin 457 may be formed, following the cut region 482 and the cut region 484 in the first sacrificial layer 470. The cut region 486, the cut region 488, and the cut region 489 have been formed with the aid of grating lines, the first sacrificial layer 470, and the second sacrificial layer 490. The cut region 486, the cut region 488, and the cut region 489 may be formed in one single pass based on the cut regions formed in the second sacrificial layer 490.

As shown in Figure 4(h), the first sacrificial layer 470, the second sacrificial layer 490 with the embedded grating lines may be removed, together with the dielectric layer 450 covering the fin 451, the fin 453, the fin 455, and the fin 457. A semiconductor device 410 may be formed including multiple fins having multiple cut regions, where the multiple cut regions may have sharply orthogonal corners instead of substantially orthogonal comers. Furthermore, there may be residue material of the first sacrificial layer 470 or the second sacrificial layer 490 left on the fins, e.g., above the fin 451, the fin 453, the fin 455, and the fin 457. Afterwards, gate electrode and other layers may be made to form various FinFET transistors.

Figure 5 schematically illustrates another process 500 for forming an example semiconductor device including multiple fins having multiple cut regions with orthogonal comers on multiple fins based on multiple masks formed by using a first sacrificial layer and a second sacrificial layer with embedded grating lines, in accordance with some embodiments. In embodiments, the process 500 may be applied to form the semiconductor device 100 as shown in Figure 1, or the semiconductor device 300 as shown in Figure 3. In embodiments, the process 500 may be an example of the process 400 shown in Figure 4.

At block 501, the process 500 may include forming a first fin and a second fin over a substrate, wherein the first fin and the second fin are in parallel along a first direction. For example, in embodiment, the process 500 may include forming the fin 151 and the fin 152 over the substrate 101 as illustrated in Figure 1 , where the fin 151 and the fin 153 may be in parallel along a first direction. There may be more than two fins formed.

At block 503, the process 500 may include forming a first sacrificial layer of a first material over the first fin and the second fin. For example, in embodiment, the process 500 may include forming the first sacrificial layer 270 over the fin 251 and the fin 253, as shown in Figure 2(a).

At block 505, the process 500 may include forming a second sacrificial layer of a second material over the first sacrificial layer, wherein the second material is different from the first material. For example, in embodiment, the process 500 may include forming the second sacrificial layer 290 over the first sacrificial layer 270, as shown in Figure 2(a).

At block 507, the process 500 may include forming a plurality of grating lines including a first grating line and a second grating line within the second sacrificial layer, wherein the plurality of grating lines include a third material different from the second material, and the plurality of grating lines are in parallel along a second direction that is orthogonal to the first direction. For example, in embodiment, the process 500 may include forming the grating line 291 , the grating line 293, the grating line 295, and the grating line 297 within the second sacrificial layer 290, as shown in Figure 2(c). The grating line 291 , the grating line 293, the grating line 295, and the grating line 297 may include a material different from the material for the second sacrificial layer 290. The grating line 291 , the grating line 293, the grating line 295, and the grating line 297 may be in parallel along a second direction that is orthogonal to the first direction, hence orthogonal to the fin 251 and the fin 253.

At block 509, the process 500 may include forming a first cut region in the second sacrificial layer, wherein the first cut region in the second sacrificial layer is between the first grating line and the second grating line, the first grating line and the second grating line are not removed during the forming the first cut region in the second sacrificial layer, and the first cut region in the second sacrificial layer is over a first portion of the first fin between the first grating line and the second grating line. For example, in embodiment, the process 500 may include forming the cut region 340 in the sacrificial layer 390, as shown in Figure 3(e). The cut region 340 may be included in the part 392 of the sacrificial layer 390, between the grating line 391 and the grating line 393. When the cut region 340 is formed, the grating line 391 and the grating line 393 remain intact and are not removed. The cut region 340 may be over a first portion of the fin 351 between the grating line 391 and the grating line 393.

Figure 6 illustrates an interposer 600 that includes one or more embodiments of the disclosure. The interposer 600 is an intervening substrate used to bridge a first substrate 602 to a second substrate 604. The first substrate 602 may be, for instance, an integrated circuit die, including the semiconductor device 100 shown in Figure 1, the semiconductor device 200 shown in Figure 2(a), or the semiconductor device 300 shown in Figure 3(a). For examples, the first substrate 602 may be an integrated circuit die including multiple fins having multiple cut regions with orthogonal corners on the multiple fins based on multiple masks formed by using sacrificial layers with embedded grating lines. The second substrate 604 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 600 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 600 may couple an integrated circuit die to a ball grid array (BGA) 606 that can subsequently be coupled to the second substrate 604. In some embodiments, the first and second substrates 602/604 are attached to opposing sides of the interposer 600. In other embodiments, the first and second substrates 602/604 are attached to the same side of the interposer 600. And in further embodiments, three or more substrates are interconnected by way of the interposer 600.

The interposer 600 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The interposer may include metal interconnects 608 and vias 610, including but not limited to through-silicon vias (TSVs) 612. The interposer 600 may further include embedded devices 614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 600. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer 600.

Figure 7 illustrates a computing device 700 in accordance with one embodiment of the disclosure. The computing device 700 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die, such as a SoC used for mobile devices. The components in the computing device 700 include, but are not limited to, an integrated circuit die 702 and at least one communications logic unit 708. In some implementations the communications logic unit 708 is fabricated within the integrated circuit die 702 while in other implementations the communications logic unit 708 is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit die 702. The integrated circuit die 702 may include a CPU 704 as well as on-die memory 706, often used as cache memory, which can be provided by technologies such as embedded DRAM (eDRAM), SRAM, or spin-transfer torque memory (STT-MRAM).

Computing device 700 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within a SoC die. These other components include, but are not limited to, volatile memory 710 (e.g., DRAM), non-volatile memory 712 (e.g., ROM or flash memory), a graphics processing unit 714 (GPU), a digital signal processor 716, a crypto processor 742 (e.g., a specialized processor that executes cryptographic algorithms within hardware), a chipset 720, at least one antenna 722 (in some implementations two or more antenna may be used), a display or a touchscreen display 724, a touchscreen controller 726, a battery 728 or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device 728, a compass 730, a motion coprocessor or sensors 732 (that may include an accelerometer, a gyroscope, and a compass), a microphone (not shown), a speaker 734, a camera 736, user input devices 738 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 740 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). The computing device 700 may incorporate further transmission, telecommunication, or radio functionality not already described herein. In some implementations, the computing device 700 includes a radio that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space. In further implementations, the computing device 700 includes a transmitter and a receiver (or a transceiver) that is used to communicate over a distance by modulating and radiating electromagnetic waves in air or space.

The communications logic unit 708 enables wireless communications for the transfer of data to and from the computing device 700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communications logic unit 708 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Infrared (IR), Near Field Communication (NFC), Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 700 may include a plurality of communications logic units 708. For instance, a first communications logic unit 708 may be dedicated to shorter range wireless communications such as Wi-Fi, NFC, and Bluetooth and a second communications logic unit 708 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 704 of the computing device 700 includes one or more devices, such as semiconductor devices, that are formed in accordance with embodiments of the current disclosure, e.g., the semiconductor device 100 shown in Figure 1, the semiconductor device 200 shown in Figure 2(a), or the semiconductor device 300 shown in Figure 3(a), and/or a semiconductor device fabricated using the process 400, or the process 500. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communications logic unit 708 may also include one or more devices, such as semiconductor devices, that are formed in accordance with embodiments of the current disclosure, e.g., the semiconductor device 100 shown in Figure 1, the semiconductor device 200 shown in Figure 2(a), or the semiconductor device 300 shown in Figure 3(a), and/or a semiconductor device fabricated using the process 400, or the process 500.

In further embodiments, another component housed within the computing device 700 may contain one or more devices, such as semiconductor devices, that are formed in accordance with implementations of the current disclosure, e.g., the semiconductor device 100 shown in Figure 1, the semiconductor device 200 shown in Figure 2(a), or the semiconductor device 300 shown in Figure 3(a), and/or a semiconductor device fabricated using the process 400, or the process 500.

In various embodiments, the computing device 700 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a dumbphone, a tablet, a tablet/laptop hybrid, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 700 may be any other electronic device that processes data.

The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

Some non-limiting Examples are provided below.

Example 1 may include a method for forming a semiconductor device, the method comprising: forming a first fin and a second fin over a substrate, wherein the first fin and the second fin are in parallel along a first direction; forming a first sacrificial layer of a first material over the first fin and the second fin; forming a second sacrificial layer of a second material over the first sacrificial layer, wherein the second material is different from the first material; forming a plurality of grating lines including a first grating line and a second grating line within the second sacrificial layer, wherein the plurality of grating lines include a third material different from the second material, and the plurality of grating lines are in parallel along a second direction that is orthogonal to the first direction; and forming a first cut region in the second sacrificial layer, wherein the first cut region in the second sacrificial layer is between the first grating line and the second grating line, the first grating line and the second grating line are not removed during the forming the first cut region in the second sacrificial layer, and the first cut region in the second sacrificial layer overlaps with a first portion of the first fin with orthogonal corners. Example 2 may include the method of example 1 and/or some other examples herein, wherein the forming the first cut region in the second sacrificial layer includes forming the first cut region in the second sacrificial layer based on a first mask, and the method further comprising: forming a second cut region in the second sacrificial layer based on a second mask, wherein the second cut region in the second sacrificial layer is between a third grating line and a fourth grating line included in the plurality of grating lines, the third grating line and the fourth grating line are not removed during the forming the second cut region in the second sacrificial layer, and the second cut region in the second sacrificial layer overlaps with a second portion of the second fin with orthogonal comers; and forming a first cut region in the first sacrificial layer and a second cut region in the first sacrificial layer simultaneously, wherein the first cut region in the first sacrificial layer is formed following the first cut region in the second sacrificial layer, and the second cut region in the first sacrificial layer is formed following the second cut region in the second sacrificial layer.

Example 3 may include the method of example 2 and/or some other examples herein, further comprising: forming a first cut region of the first fin as the first portion of the first fin following the first cut region in the first sacrificial layer; and forming a second cut region of the second fin as the second portion of the second fin following the second cut region in the first sacrificial layer.

Example 4 may include the method of any of examples 1 -3 and/or some other examples herein, wherein the first sacrificial layer includes TiN.

Example 5 may include the method of any of examples 1 -3 and/or some other examples herein, wherein the first sacrificial layer has a thickness ranging from 1 nm to 5 nm.

Example 6 may include the method of any of examples 1 -3 and/or some other examples herein, wherein the first grating line is aligned with a gate electrode over the first fin.

Example 7 may include the method of any of examples 1 -3 and/or some other examples herein, wherein the first grating line includes SiN, SiC, Si, SiO, TiN, CHM, or SiON.

Example 8 may include the method of any of examples 1 -3 and/or some other examples herein, wherein the first grating line has a width of a critical dimension. Example 9 may include the method of any of examples 1-3 and/or some other examples herein, wherein the second sacrificial layer includes one of SiN, SiON, SiC, SiCN, SiOCN, SiOC, SiBN, SiBCN, or combinations thereof.

Example 10 may include the method of any of examples 1-3 and/or some other examples herein, wherein the forming the first cut region in the second sacrificial layer includes forming the first cut region in the second sacrificial layer by selective etching based on a mask.

Example 11 may include the method of example 10 and/or some other examples herein, wherein the mask lands on the first grating line and the second grating line, the selective etching removes the second material in the second sacrificial layer between the first grating line and the second grating line based on the mask, and the first grating line and the second grating line including the third material are not removed during the selective etching.

Example 12 may include a method for forming a semiconductor device, the method comprising: forming a first fin and a second fin over a substrate, wherein the first fin and the second fin are in parallel; forming a first sacrificial layer of a first material over the first fin and the second fin; forming a second sacrificial layer of a second material over the first sacrificial layer, wherein the second material is different from the first material; forming a first cut region in the second sacrificial layer based on a first mask; forming a second cut region in the second sacrificial layer based on a second mask; forming a first cut region in the first sacrificial layer and a second cut region in the first sacrificial layer simultaneously, wherein the first cut region in the first sacrificial layer is formed following the first cut region in the second sacrificial layer, and the second cut region in the first sacrificial layer is formed following the second cut region in the second sacrificial layer.

Example 13 may include the method of example 12 and/or some other examples herein, further comprising: forming a plurality of grating lines including a first grating line, a second grating line, a third grating line, and a fourth grating line within the second sacrificial layer, wherein the plurality of grating lines include a third material different from the second material, the first fin and the second fin are in parallel along a first direction, and the plurality of grating lines are in parallel along a second direction orthogonal to the first direction; and wherein the first cut region in the second sacrificial layer is between the first grating line and the second grating line, the first grating line and the second grating line are not removed by the forming the first cut region in the second sacrificial layer, and the first cut region in the second sacrificial layer overlaps with a first portion of the first fin between the first grating line and the second grating line; and the second cut region in the second sacrificial layer is between the third grating line and the fourth grating line, the third grating line and the fourth grating line are not removed by the forming the second cut region in the second sacrificial layer, and the second cut region in the second sacrificial layer overlaps with a second portion of the second fin between the third grating line and the fourth grating line.

Example 14 may include the method of example 13 and/or some other examples herein, further comprising: forming a first cut region of the first fin as the first portion of the first fin following the first cut region in the first sacrificial layer; and forming a second cut region of the second fin as the second portion of the second fin following the second cut region in the first sacrificial layer.

Example 15 may include the method of any of examples 12-14 and/or some other examples herein, wherein the forming the first cut region in the second sacrificial layer includes forming the first cut region in the second sacrificial layer by selective etching based on the first mask.

Example 16 may include the method of example 15 and/or some other examples herein, wherein the first mask lands on the first grating line and the second grating line, the selective etching removes the second material in the second sacrificial layer between the first grating line and the second grating line, and the first grating line and the second grating line including the third material are not removed during the selective etching.

Example 17 may include the method of any of examples 12-14 and/or some other examples herein, wherein the first sacrificial layer includes TiN.

Example 18 may include the method of any of examples 12-14 and/or some other examples herein, wherein the second sacrificial layer includes one of SiN, SiON, SiC, SiCN, SiOCN, SiOC, SiBN, SiBCN, or combinations thereof.

Example 19 may include the method of any of examples 12-14 and/or some other examples herein, wherein the first grating line is aligned with a gate electrode over the first fin.

Example 20 may include a semiconductor device, comprising: a substrate; a first fin over the substrate, wherein the first fin has a first cut region, the first cut region has sharply orthogonal corners; and a second fin over the substrate, wherein the first fin and the second fin are in parallel along a first direction, the second fin has a second cut region, and the second cut region has sharply orthogonal corners. Example 21 may include the device of example 20 and/or some other examples herein, further comprising: a gate electrode, wherein the gate electrode covers the first fin and the second fin along a second direction orthogonal to the first direction.

Example 22 may include the device of example 21 and/or some other examples herein, 22. wherein the first cut region and the second cut region have a same processing variation.

Example 23 may include the device of any of examples 20-22 and/or some other examples herein, wherein the substrate includes a silicon substrate, or a silicon-on- insulator (SOI) substrate.

Example 24 may include the device of any of examples 20-22 and/or some other examples herein, wherein the first fin includes one or more of silicon (Si), germanium (Ge), SiGe, or silicon carbide (SiC).

Example 25 may include the device of any of examples 20-22 and/or some other examples herein, wherein the gate electrode includes one or more of aluminum (Al), tungsten (W), molybdenum (Mo), nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), or tantalum (Ta).

Various embodiments may include any suitable combination of the above- described embodiments including alternative (or) embodiments of embodiments that are described in conjunctive form (and) above (e.g., the "and" may be "and/or"). Furthermore, some embodiments may include one or more articles of manufacture (e.g., non-transitory computer-readable media) having instructions, stored thereon, that when executed result in actions of any of the above-described embodiments. Moreover, some embodiments may include apparatuses or systems having any suitable means for carrying out the various operations of the above-described embodiments.

The above description of illustrated implementations, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments of the present disclosure to the precise forms disclosed. While specific implementations and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize.

These modifications may be made to embodiments of the present disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit various embodiments of the present disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

Claims What is claimed is:

1. A method for forming a semiconductor device, the method comprising:

forming a first fin and a second fin over a substrate, wherein the first fin and the second fin are in parallel along a first direction;

forming a first sacrificial layer of a first material over the first fin and the second fin;

forming a second sacrificial layer of a second material over the first sacrificial layer, wherein the second material is different from the first material;

forming a plurality of grating lines including a first grating line and a second grating line within the second sacrificial layer, wherein the plurality of grating lines include a third material different from the second material, and the plurality of grating lines are in parallel along a second direction that is orthogonal to the first direction; and forming a first cut region in the second sacrificial layer, wherein the first cut region in the second sacrificial layer is between the first grating line and the second grating line, the first grating line and the second grating line are not removed during the forming the first cut region in the second sacrificial layer, and the first cut region in the second sacrificial layer overlaps with a first portion of the first fin with orthogonal corners.

2. The method of claim 1, wherein the forming the first cut region in the second sacrificial layer includes forming the first cut region in the second sacrificial layer based on a first mask, and the method further comprising:

forming a second cut region in the second sacrificial layer based on a second mask, wherein the second cut region in the second sacrificial layer is between a third grating line and a fourth grating line included in the plurality of grating lines, the third grating line and the fourth grating line are not removed during the forming the second cut region in the second sacrificial layer, and the second cut region in the second sacrificial layer overlaps with a second portion of the second fin with orthogonal corners; and

forming a first cut region in the first sacrificial layer and a second cut region in the first sacrificial layer simultaneously, wherein the first cut region in the first sacrificial layer is formed following the first cut region in the second sacrificial layer, and the second cut region in the first sacrificial layer is formed following the second cut region in the second sacrificial layer.

3. The method of claim 2, further comprising:

forming a first cut region of the first fin as the first portion of the first fin following the first cut region in the first sacrificial layer; and

forming a second cut region of the second fin as the second portion of the second fin following the second cut region in the first sacrificial layer.

4. The method of any of claims 1-3, wherein the first sacrificial layer includes

TiN.

5. The method of any of claims 1-3, wherein the first sacrificial layer has a thickness ranging from 1 nm to 5 nm.

6. The method of any of claims 1-3, wherein the first grating line is aligned with a gate electrode over the first fin.

7. The method of any of claims 1-3, wherein the first grating line includes one of SiN, SiC, Si, SiO, TiN, CHM, or SiON.

8. The method of any of claims 1-3, wherein the first grating line has a width of a critical dimension.

9. The method of any of claims 1-3, wherein the second sacrificial layer includes one of SiN, SiON, SiC, SiCN, SiOCN, SiOC, SiBN, SiBCN, or combinations thereof.

10. The method of any of claims 1-3, wherein the forming the first cut region in the second sacrificial layer includes forming the first cut region in the second sacrificial layer by selective etching based on a mask.

11. The method of claim 10, wherein the mask lands on the first grating line and the second grating line, the selective etching removes the second material in the second sacrificial layer between the first grating line and the second grating line based on the mask, and the first grating line and the second grating line including the third material are not removed during the selective etching.

12. A method for forming a semiconductor device, the method comprising: forming a first fin and a second fin over a substrate, wherein the first fin and the second fin are in parallel;

forming a first cut region in the second sacrificial layer based on a first mask; forming a second cut region in the second sacrificial layer based on a second mask;

13. The method of claim 12, further comprising:

forming a plurality of grating lines including a first grating line, a second grating line, a third grating line, and a fourth grating line within the second sacrificial layer, wherein the plurality of grating lines include a third material different from the second material, the first fin and the second fin are in parallel along a first direction, and the plurality of grating lines are in parallel along a second direction orthogonal to the first direction; and

wherein the first cut region in the second sacrificial layer is between the first grating line and the second grating line, the first grating line and the second grating line are not removed by the forming the first cut region in the second sacrificial layer, and the first cut region in the second sacrificial layer overlaps with a first portion of the first fin between the first grating line and the second grating line; and

the second cut region in the second sacrificial layer is between the third grating line and the fourth grating line, the third grating line and the fourth grating line are not removed by the forming the second cut region in the second sacrificial layer, and the second cut region in the second sacrificial layer overlaps with a second portion of the second fin between the third grating line and the fourth grating line.

14. The method of claim 13, further comprising:

15. The method of any of claims 12-14, wherein the forming the first cut region in the second sacrificial layer includes forming the first cut region in the second sacrificial layer by selective etching based on the first mask.

16. The method of claim 15, wherein the first mask lands on the first grating line and the second grating line, the selective etching removes the second material in the second sacrificial layer between the first grating line and the second grating line, and the first grating line and the second grating line including the third material are not removed during the selective etching.

17. The method of any of claims 12-14, wherein the first sacrificial layer includes

TiN.

18. The method of any of claims 12-14, wherein the second sacrificial layer includes one of SiN, SiON, SiC, SiCN, SiOCN, SiOC, SiBN, SiBCN, or combinations thereof.

19. The method of any of claims 12-14, wherein the first grating line is aligned with a gate electrode over the first fin.

20. A semiconductor device, comprising:

a substrate;

a first fin over the substrate, wherein the first fin has a first cut region, the first cut region has sharply orthogonal comers; and

a second fin over the substrate, wherein the first fin and the second fin are in parallel along a first direction, the second fin has a second cut region, and the second cut region has sharply orthogonal comers.

21. The device of claim 20, further comprising:

a gate electrode, wherein the gate electrode covers the first fin and the second fin along a second direction orthogonal to the first direction.

22. The device of claim 21, wherein the first cut region and the second cut region have a same processing variation.

23. The device of any of claims 20-22, wherein the substrate includes a silicon substrate, or a silicon-on-insulator (SOI) substrate.

24. The device of any of claims 20-22, wherein the first fin includes one or more of silicon (Si), germanium (Ge), SiGe, or silicon carbide (SiC).

25. The device of any of claims 20-22, wherein the gate electrode includes one or more of aluminum (Al), tungsten (W), molybdenum (Mo), nickel (Ni), palladium (Pd), gold (Au), silver (Ag), copper (Cu), or tantalum (Ta).