CN101454874B - 半导体薄膜的选择性外延形成 - Google Patents

半导体薄膜的选择性外延形成 Download PDF

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CN101454874B
CN101454874B CN2007800198311A CN200780019831A CN101454874B CN 101454874 B CN101454874 B CN 101454874B CN 2007800198311 A CN2007800198311 A CN 2007800198311A CN 200780019831 A CN200780019831 A CN 200780019831A CN 101454874 B CN101454874 B CN 101454874B
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M·鲍尔
K·D·韦克斯
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Abstract

通过重复均厚淀积和选择性刻蚀的循环工艺在半导体窗口(114)中选择性形成外延层(125)。均厚淀积阶段在绝缘区(112)如场氧化物上留下非外延材料(120)，而选择性刻蚀阶段优先去除非外延材料(120)，同时周而复始地增进淀积的外延材料(125)。相对于在绝缘体(112)上不发生淀积的选择性工艺，该外延材料(125)的质量得到改善。在该工艺的刻蚀阶段中使用锗催化剂可以帮助增大刻蚀速率并且便于在整个循环中经济地维持等温和/或等压条件。通过使用丙硅烷、在绝缘区(112)之上形成无定形材料(120)以及最小化每个淀积阶段中无定形材料与外延材料的厚度比，可以提高产量和质量。

Description

半导体薄膜的选择性外延形成 
相关申请的交叉引用 
本申请要求于2006年6月7日提交的美国临时专利申请第60/811,703号的优先权。 
本申请还涉及美国专利申请11/343,275(提交于2006年1月30日；代理人案号ASMEX.511A)、美国专利申请11/343,264(提交于2006年1月30日；代理人案号ASMEX.517A)、美国专利申请公开文本2003/0036268(提交于2002年5月29日；代理人案号ASMEX.317A)以及美国专利6,998,305(提交于2004年1月23日；代理人案号ASMEX.425A)。因此所有这些相关申请的全部公开通过参考合并于此。 
技术领域
本发明一般地涉及在半导体工艺中淀积含硅材料，并且更具体地涉及在半导体窗口上选择性形成含硅材料。 
背景技术
在形成集成电路时，在选择的位置诸如场氧隔离区之间的有源区平台中，或甚至更特别地在定义的源区和漏区上经常需要外延层。尽管在淀积后可以从场氧隔离区上选择性去除非外延(无定形的或多晶的)材料，但典型地认为更有效的是同时提供化学气相淀积(CVD)和刻蚀化学药品，并调整条件以导致绝缘区上的净淀积和暴露的半导体窗口上的净外延淀积为零。被称为选择性外延CVD的这一工艺利用在绝缘体如二氧化硅或氮化硅上的典型半导体淀积工艺的缓慢晶核形成。这一选择性外延CVD还利用了与外延层的易受影响性相比，无定形和多晶材料对刻蚀剂的自然更大的易受影响性。 
需要选择性外延形成半导体层的很多情形的示例包括用于产生应变或张力(strain)的许多方案。半导体材料诸如硅、锗和硅锗合金的电学特性受到材料应变程度的影响。例如，硅在拉伸应变的情况下展现出增强的电子迁移率，而硅锗在压应变的情况下展现出增强的空穴迁移率。增强半导体材料性能的方法具有相当大的重要性并有可能应用于各种半导体工艺应用中。半导体工艺典型地用于要求特别严厉的质量需求的集成电路加工，以及各种其它领域。例如，半导体工艺技术还用于加工利用大量科技的平板显示器，以及用于加工微机电系统(“MEMS”)。 
 用于在含硅和含锗的材料中诱导应变的许多方法关注于开发不同晶体材料之间的晶格常数的差异。例如，晶体锗的晶格常数是5.65
Figure G2007800198311D0002075450QIETU
，晶体硅是5.431，而金刚石是3.567。各向异性外延涉及以某种方式在不同晶体材料上淀积特定晶体材料的薄层，以使淀积层采用下面单晶材料的晶格常数。例如，利用这一方法应变的硅锗层可以通过在单晶硅衬底上的各向异性外延淀积来形成。因为锗原子稍微大于硅原子，但是淀积的各向异性外延硅锗受到它下面更小的硅的晶格常数的限制，硅锗被压应变到一程度，该程度随锗含量而发生变化。典型地，随着硅锗中的锗含量增大，硅锗层的带隙从纯硅的1.12eV单调减小到纯锗的0.67eV。在另一个方法中，通过在稀疏的硅锗层上各向异性外延淀积硅层来提供薄的单晶硅层中的拉伸应变。在这一示例中，各向异性外延淀积的硅发生应变是因为其晶格常数受到它下面的稀疏硅锗的更大晶格常数的限制。拉伸应变的各向异性外延硅典型地表现出增大的电子迁移率。在这两种方法中，应变是在加工成器件(例如晶体管)之前的衬底级发展出来的。 
在这些示例中，通过用硅原子替代晶格结构中的其它原子来将应变引入到含单晶硅的材料中。这一技术通常被称为“替代掺杂”。例如，用锗原子取代单晶硅晶格结构中的一些硅原子可在最终的取代性掺杂单晶硅材料中产生压应变，因为锗原子大于它们所替代的硅原子。有可能通过用碳取代掺杂来将拉伸应变引入到单晶硅中，因为碳原子小于它们所替代的硅原子。额外的细节在＂Silicon-Germanium Carbon Alloy＂，Taylor and Francis，pp.59-89(New York2002)的第3章、Judy L.Hoyt的＂Substitutional Carbon Incorporation and Electronic Characterization ofSh_yCy/Si and Heterojunctions＂中提供，其公开内容通过参考合并于此， 并在本文中被称为“Hoyt文献”。然而非取代性杂质不会引入应变。 
类似地，电掺杂剂也应该取代合并到外延层中以便具有电活性。掺杂剂在淀积时被合并或者它们需要进行退火以达到所需的取代水平和掺杂剂活化程度。因为退火要消耗加热预算，所以原位掺杂用于调整晶格常数的杂质或电掺杂剂常常优选于接着退火的非原位掺杂以将掺杂剂合并到晶格结构中。然而，在实践中，原位取代性掺杂被淀积过程中非取代性合并杂质的趋势变得复杂，该趋势例如通过以域或群有空隙地合并到硅中，而不是取代栅格结构中的硅原子。非取代性掺杂使得例如硅的碳掺杂、硅锗的碳掺杂、硅和硅锗的电活性掺杂剂掺杂变得复杂。如Hoyt文献的第73页的图3.10所示，现有淀积方法已经用于使晶体硅具有原子数百分比高达2.3％的原位掺杂取代性碳含量，这对应于超过5.4的栅格间距和小于1.0GPa的张应力。 
发明内容
 根据本发明的另一方面，提供用于在半导体窗口中选择性形成半导体材料的方法。该方法包括在化学气相淀积室中提供衬底，其中该衬底包括绝缘表面和单晶半导体表面。在该衬底的绝缘表面和单晶半导体表面上均厚淀积半导体材料，从而使绝缘表面上的非外延半导体材料与单晶半导体表面上的外延半导体材料的厚度比率小于大约1.6:1。从绝缘表面上选择性去除非外延半导体材料，其中在化学气相淀积室中进行均厚淀积和选择性去除。 
根据本发明的另一方面，提供用于选择性形成外延半导体材料的方法。均厚淀积半导体材料，以在衬底的单晶半导体区上形成外延材料，并在该衬底的绝缘区上形成非外延材料。通过将均厚淀积的半导体材料暴露于刻蚀化学物质以从绝缘区上选择性去除非外延材料，该刻蚀化学物质包括卤化物源和锗源。重复至少一次均厚淀积和选择性去除。 
根据本发明的另一方面，提供用于在衬底上的选择位置中形成含硅材料的方法。该方法包括提供衬底，该衬底具有暴露在场氧隔离区之间的单晶半导体窗口。通过使丙硅烷流动经过该衬底，在单晶材料的窗口和场氧隔离区之上均厚淀积含硅材料。从场氧隔离区上选择性去除 含硅材料。在多个循环中重复均厚淀积和选择性去除。 
 根据本发明的另一方面，提供用于选择性形成外延半导体材料的方法。所述方法包括提供带有绝缘区和其中形成有半导体窗口的衬底。在绝缘区上淀积无定形半导体材料，并在半导体窗口上淀积外延半导体材料。从绝缘区上选择性刻蚀无定形半导体材料，而在半导体窗口中留下至少一些外延半导体材料。在多个循环中重复均厚淀积和选择性去除。 
附图说明
结合附图举例说明本文所公开的方法和系统的示例性实施例，这仅是为了举例说明。附图包括以下图形，其中相同的标号指示相同的部件。 
图1是图示说明用于选择性形成外延半导体层的工艺的流程图，该工艺利用在混合衬底的凹陷源/漏区中淀积掺杂碳的硅薄膜的特定示例。 
图2是局部成形的半导体结构的示意图，其包括形成于半导体衬底中的图案化绝缘体区。 
图3是实施在混合衬底表面上均厚淀积掺杂碳的硅薄膜之后图2的局部成形半导体结构的示意图。 
图4是实施选择性化学气相刻蚀工艺以从混合衬底的氧化物区去除掺杂碳的硅之后图3的局部成形半导体结构的示意图。 
 图5A-5D是实施更多次均厚淀积和选择性刻蚀循环后图4的局部成形半导体结构的示意图。 
图6示出掺杂碳的硅薄膜的无定形区的刻蚀速率随刻蚀化学药品过程中HCl局部压强变化的图表。 
图7示出针对不同刻蚀化学药品，刻蚀速率和无定形(“a”)与单晶(“c”)刻蚀速率比随刻蚀化学药品中GeH4流量变化的图表。 
图8示出掺杂碳的硅薄膜的无定形区的刻蚀速率随腔室压强变化的图表。 
图9示出掺杂碳的硅薄膜的无定形区的刻蚀速率随温度的倒数变化的图表。
图10示出掺杂碳的硅薄膜的无定形区的厚度随积累的刻蚀时间变化的图表。 
图11示出晶片上淀积的掺杂碳的硅薄膜的无定形区的刻蚀速率随晶片上的径向位置变化的图表。 
图12示出针对不同刻蚀循环持续时间，晶片上淀积的掺杂碳的硅薄膜的无定形区的厚度随晶片上的径向位置变化的图表。 
图13示出针对不同GeH4刻蚀剂的刻蚀化学药品和不同刻蚀循环持续时间，晶片上淀积的掺杂碳的硅薄膜的无定形区的厚度随晶片上的径向位置变化的图表。 
图14是图示说明示例性局部成形的掺杂碳的硅结构的显微照片，该掺杂碳的硅结构是通过在图案化衬底上实施均厚淀积和局部刻蚀循环所产生的。 
 图15示出元素浓度随示例性局部成形的掺杂碳的硅薄膜的厚度变化的图表，该掺杂碳的硅薄膜是利用本文公开的一些技术形成的。 
 图16是图示说明示例性形成的掺杂碳的硅结构的显微照片，该掺杂碳的硅结构是通过在图案化衬底上实施多次淀积和刻蚀循环所产生的。 
图17图示说明已经利用本文公开的一些循环技术选择性形成的外延掺杂碳的硅薄膜的原子力显微分析(atomic force microscopyanalysis)。 
图18示出利用本文公开的一些循环技术淀积的掺杂碳的硅薄膜的X射线衍射摇摆曲线。 
具体实施方式
淀积技术常常试图调整衬底的不同区域中的淀积量或淀积种类。例如，美国专利第6,998,305号认为同步的刻蚀和淀积反应对于选择性淀积在硅上而不淀积在二氧化硅上来说是公知的。为了控制第三类型表面即暴露的晶体管栅极上的淀积，第6,998,305号专利教导循环交替选择性淀积阶段和刻蚀阶段。然而，本发明者已经认识到选择性淀积化学性质有时会对淀积层产生不希望的影响。尽管所述实施例涉及NMOS应用中 掺杂碳的硅的具体示例，技术人员应该理解本文所述的方法可以应用于多种半导体应用，其中层的选择性形成是需要的，但刻蚀剂会妨碍淀积层的所需特性。 
对于制作多种取代性掺杂的含单晶硅的材料来说，存在一些有用的淀积方法。例如，有可能通过利用作为硅源的丙硅烷(Si3H8)和作为碳源的含碳气体或蒸汽以相对高的速率实施淀积，以实施晶体硅的原位取代性碳掺杂。掺杂碳的含硅合金具有对硅锗系统的互补特性。取代性掺杂的程度为70％或更高，其表示为取代性碳掺杂剂占硅中(取代性和非取代性)碳掺杂剂的总量的质量百分比。用于形成掺杂碳的含硅材料的技术已经克服了若干挑战，包括碳和硅之间的大晶格失配、碳在硅中的低溶解性以及掺杂碳的硅的沉淀趋势。美国专利申请11/343,275(提交于2006年1月30日；代理人案号ASMEX.511A)中提供了关于晶体硅的原位取代性碳掺杂的额外细节。 
在本文中使用的术语“含硅材料”及类似术语指的是很大范围的含硅材料，其包括但不局限于硅(包括晶体硅)、掺杂碳的硅(Si:C)、硅锗和掺杂碳的硅锗(SiGe:C)。如本文所用，“掺杂碳的硅”、“Si:C”、“硅锗”、“掺杂碳的硅锗”、“SiGe:C”及类似术语指的是含有不同比例的所需化学元素和任选的少量其它元素的材料。例如，“硅锗”是一种包含硅、锗和任选的其它元素的材料，该其它元素例如碳和电活性掺杂剂等掺杂剂。“Si:C”和“SiGe:C”等术语本质上并不是化学配比的化学式，因此并不限于包含特定比率的所需元素的材料。此外，Si:C和SiGe:C等术语并不排除其它掺杂剂如磷的存在，且掺杂碳的硅材料被包括在术语Si:C和术语Si:C:P中。除非特别指明，本文所表示的含硅薄膜中掺杂剂(诸如碳、锗或电活性掺杂剂)的百分比指的是相对于整个薄膜的原子数百分比。 
有可能通过以下步骤来确定取代性掺杂到含硅材料中的碳的量：利用X射线衍射测量掺杂含硅材料的垂直晶格间距，然后实施单晶硅和单晶碳(金刚石)之间的线性内插以应用Vegard定律。例如，有可能通过利用X射线衍射测量掺杂硅的垂直晶格间距且然后应用Vegard定律来确定取代性掺杂到硅中的碳的量。关于这一技术的额外细节在Hoyt文献 中提供。有可能通过次级离子质谱法(“SIMS”)来确定掺杂硅中的总体碳含量。有可能通过从总体碳含量中减去取代性碳含量以确定非取代性碳含。有可能以类似的方式确定取代性掺杂到其它含硅材料中的其它元素的量。 
本文所用的术语“衬底”指的是其上希望淀积的工件，或者暴露于一种或多于一种淀积气体的表面。例如，在某些实施例中，衬底是单晶硅晶片、绝缘体上的半导体(“SOI”)衬底、或外延硅表面、硅锗表面、或淀积在晶片上的III族—V族材料。工件并不局限于晶片，而是还包括玻璃、塑料或用于半导体工艺的其它衬底。如全部公开内容通过参考合并于此的美国专利6,900,115所述，“混合衬底”是具有两个或更多不同类型表面的衬底。例如，在某些应用中，混合衬底包括具有第一表面形态的第一表面和具有第二表面形态的第二表面。在某些实施例中，在单晶半导体材料上选择性形成掺杂碳的含硅层，同时最小化或者更优选地避免邻近的电介质或绝缘体上的淀积。电介质材料的示例包括二氧化硅(包括低介电常数的形式诸如掺杂碳和掺杂氟的硅氧化物)、氮化硅、金属氧化物和金属硅化物。本文使用的术语“外延的”、“外延地”、“各向异性外延的”、“各项异性外延地”及类似术语指的是以某种方式将含晶体硅的材料淀积到晶体衬底上以使淀积层采用或遵循衬底的晶格常数。当淀积层的成分不同于衬底的成分时，通常认为外延淀积是各项异性外延的。 
 即使表面由同一种元素组成，如果这些表面的形态(结晶度)不同，则认为这些表面是不同的。本文所述的工艺对于将含硅薄膜淀积到多种衬底上是有用的，但对具有混合表面形态的混合衬底特别有用。这种混合衬底包括具有第一表面形态的第一表面和具有第二表面形态的第二表面。在这一背景中，“表面形态”指的是衬底表面的晶体结构。无定形和晶体是不同形态的示例。多晶形态是由有序晶体的无序排列组成的晶体结构，并因此具有中间有序程度。多晶材料中的原子在每个晶体中是有序的，但是晶体本身相对于彼此缺乏长程有序。单晶形态是具有高度长程有序的晶体结构。外延薄膜的特征在于与它们所生长的衬底(通常为单晶)相同的晶体结构和取向。这些材料中的原子排列成类晶 格结构，该类晶格结构持续相对长的距离(在原子尺度上)。无定形形态是具有低有序程度的非晶体结构，因为原子缺乏明确的周期性排列。其它形态包括微晶和无定形材料与晶体材料的混合物。因此“非外延”包含无定形、多晶、微晶及其混合物。如本文所用，“单晶”或“外延”被用于描述其中具有可容忍的缺陷数量的非常大的晶体结构，其通常用于晶体管制造。层的结晶度通常处于从无定形至多晶到单晶的连续集中；尽管存在低密度缺陷，但常常认为晶体结构是单晶的或外延的。混合衬底的具体示例包括但不限于单晶/多晶、单晶/无定形、外延/多晶、外延/无定形、多晶/电介质、外延/电介质、导体/电介质以及半导体/电介质。术语“混合衬底”包括具有多于两种不同类型表面的衬底。本文所述用于在具有两种类型表面的混合衬底上淀积含硅薄膜的方法也适用于具有三种或更多不同类型表面的混合衬底。 
 当在凹陷源/漏区中生长时，拉伸应变的掺杂碳的硅薄膜(Si:C薄膜)提供具有增强的电子迁移率的拉伸应变硅沟道，这特别有利于NMOS器件。这有利地消除了对提供松散硅锗缓冲层以支撑应变硅层的需求。在这些应用中，通过利用掺杂剂源或掺杂剂前体的原位掺杂来有利地合并电活性掺杂剂。利用磷的高水平电活性取代掺杂也有助于张应力。电掺杂剂的优选前体是掺杂剂的氢化物，包括n型掺杂剂前体诸如磷化氢、砷蒸汽和砷化三氢。甲硅烷基磷化氢(例如(H3Si)3-xPRx)和甲硅烷基砷化三氢(例如(H3Si)3-xAsRx)(其中x＝0、1或2且Rx＝H和/或氘(D))是磷掺杂剂和砷掺杂剂的替代性前体。磷和砷对于掺杂NMOS器件的源区和漏区来说特别有用。SbH3和三甲基铟(trimethylindium)分别是锑和铟的可替代源。这些掺杂剂前体有益于制备前述优选薄膜，特别是掺杂硼、磷、锑、铟和砷的硅、Si:C、硅锗和SiGe:C薄膜及合金。拉伸应变的Si:C薄膜的选择性外延形成 
现在已经发展出用于在暴露的半导体窗口诸如混合衬底的凹陷源/漏区中选择性形成拉伸应变Si:C薄膜的技术。例如，有可能通过以下步骤实现这一选择性形成：(a)利用丙硅烷作为硅前体在混合衬底上均厚淀积Si:C薄膜，以及(b)选择性刻蚀形成在混合衬底的绝缘体部分上的所得非外延层。任意循环地重复步骤(a)和(b)，直到在凹陷源/漏 区上达到目标外延薄膜厚度。 
 有可能通过干法刻蚀以及随后的HF清洗和原位退火来形成凹陷源/漏区。在使用干法刻蚀的实施例中，选择性生长的薄(在大约1nm至大约3nm之间)硅种子层的淀积有助于降低刻蚀损伤。种子层还有助于覆盖由在先掺杂剂注入工艺所造成的损伤。在示例性实施例中，可以通过在大约700℃至大约800℃之间的淀积温度下同时提供HCl和氯代硅烷来选择性淀积种子层。 
 根据优选实施例，图1提供的流程图和图2-图5D中示出的局部成形半导体结构的示意性描述举例说明了循环的均厚淀积和刻蚀工艺。虽然用凹陷源/漏区中的Si:C淀积进行举例说明，应该了解本文所述的技术有利于其它情况下外延薄膜的选择性形成，诸如在任何栅极定义和没有凹陷之前由场氧隔离的所围绕的有源岛区上选择性形成外延薄膜。 
 特别地，图1图示说明在操作块10中，具有绝缘体区和凹陷源/漏区的混合衬底被置于工艺室内。图2提供对示例性混合衬底的示意性说明，该混合衬底包括形成在半导体衬底100诸如硅晶片中的图案化绝缘体110。以填充氧化物的浅槽隔离(STI)形式示出的绝缘体110定义出场氧隔离区112并且邻近显示在栅电极115结构两侧的凹陷源/漏区114。注意到栅电极115位于衬底的沟道区117之上。沟道117和源漏区114共同定义晶体管有源区，该有源区通常由场氧隔离112所环绕以防止与相邻器件的串扰(cross-talk)。在其它布局中，多个晶体管可以被场氧隔离环绕。在一种情况下，如图所示，栅结构115的顶部可以覆盖有电介质。则这一表面表现为类似于其上进行淀积的场区110，且保持场区中的选择性的条件也可以应用于栅极的顶部。在栅极115没有被电介质覆盖的情况下，栅极表面有可能生长多晶材料，然后可以通过原位刻蚀多晶材料来将其去除，但是与用于确保场区110上没有残余多晶材料的条件相比，将应用一套不同的选择性条件(压强、气流等)。 
如图1中的操作块20所示，以及如图3的示意说明，然后利用丙硅烷作为硅前体在混合衬底上淀积均厚的Si:C层。这导致氧化物区112上的无定形的或多晶的(非外延)淀积120，以及凹陷源/漏区114上的较低外延淀积125和侧壁外延淀积130。应注意“均厚淀积”意味着在每个淀 积阶段中无定形绝缘体110和单晶区114上的最终净淀积。尽管在均厚淀积中优选缺少刻蚀剂(例如缺少卤化物)，在这种情况下也可以认为该淀积是“非选择性的”，可能需要一些刻蚀剂来调整不同区域上的淀积厚度比率，这在下面更详细地讨论。在需要该少量刻蚀剂的情况下，淀积工艺可能是局部选择性的，但仍然是均厚的，因为每个淀积阶段将在绝缘体110和单晶区114上产生净淀积。 
 然后在操作块30中选择性刻蚀无定形或多晶淀积120区域和侧壁外延淀积130区域(图1)，因此导致在图4中示意性说明的结构。优选地，在选择性刻蚀过程中很少或没有外延淀积的Si:C被从凹陷源/漏区114的较低外延层125上去除。如下面更详细地讨论，蒸汽刻蚀化学药品优选包括卤化物(例如含氟、含溴或含氯蒸汽化合物)，特别是氯源诸如HCl或Cl2。更优选地，该刻蚀化学药品还含有锗源(例如，锗烷如四氢化锗(GeH4)、GeCl4、金属有机Ge前体、固体源Ge)以改善刻蚀速率。在选择性去除非外延材料120的同时，一些外延材料被留下，而一些外延材料被去除。侧壁外延层130位于不同的平面并且还比较低外延层125更欠缺(由于两个表面上的生长速率不同)。相应地，侧壁外延层130连同非外延材料120更易于被去除。因此，可以调整每个工艺循环以实现凹陷处114的很大程度的颠倒(bottom-up)填充。在一些布局中，如果具有优良的质量且不妨碍选择性填充的目标，甚至可以通过该工艺留下侧壁上的外延材料。 
如决定块40所示(图1)，且如图5A(淀积第二次循环的均厚Si:C层120)和图5B(刻蚀第二次循环的Si:C层以留下外延Si:C层，该外延Si:C层具有凹陷源/漏区114中外延层125的增大厚度)示意说明，重复这一工艺直到在凹陷源/漏区114上实现外延Si:C薄膜厚度的目标厚度。图5C图解说明实施进一步(多个)循环以留下外延充填源/漏区114的结果，其中选择性外延层125大致与场氧化物110共面。图5D图解说明实施进一步(多个)循环以选择性留下外延层125作为升高源/漏区114的结果。 
选择性形成工艺可以进一步包括返回电介质区进行均厚淀积和选择性刻蚀的额外循环且不掺杂碳以形成覆盖层。该覆盖层可以含有或 没有电掺杂物。例如，图5D中原始衬底表面之上(即沟道117之上)的升高源/漏区125的部分可以是不含碳的，因为它对沟道117的应变不起作用。 
 在示例性实施例中，淀积的Si:C薄膜任选地包括电活性掺杂物，特别是适用于NMOS器件的掺杂物，诸如磷或砷，由此允许淀积掺杂磷的Si:C薄膜或掺杂砷的Si:C薄膜(分别为Si:C:P薄膜或Si:C:As薄膜)。优选以一定的无定形-外延生长速率比率淀积Si:C薄膜，该无定形-外延生长速率比率优选在大约1.0:1至大约1.6:1之间，更优选地在大约1.0:1至大约1.3:1之间，且最优选地在大约1.0:1至大约1.1:1，从而使绝缘体上的薄膜厚与凹陷源/漏区114上的薄膜厚大约相等。控制无定形(或更一般地非外延)-外延生长速率比率可以有利地使能对后续刻蚀工艺之后无定形Si:C和晶体Si:C之间界面处的小平面角的控制，并且还可以相对于绝缘体上的更大厚度，最小化用于去除的刻蚀持续时间。优选Si:C淀积的无定形区具有很小或没有结晶度(即主要是无定形的)，由此便于这些区域中的后续刻蚀。此外，通过使厚度比率接近于1:1而最小化过度的非外延淀积，由此降低从场区(且任选地从栅极)清除非外延淀积所需的刻蚀阶段长度。 
 在优选实施例中，利用原位化学蒸汽刻蚀技术来从混合衬底上选择性刻蚀Si:C薄膜。任选地实施同时具有短暂的温度尖峰的该化学蒸汽刻蚀技术。在一个实施例中，利用美国专利申请公开文本2003/0036268(提交于2002年5月29日；代理人案号：ASMEX.317A)中描述的工艺来管理该温度尖峰。如本文所述，通过穿透冷石英或其它透明壁的辐射加热来使用单一晶片外延淀积工具，温度尖峰能够在一段时间(例如大约12秒至大约15秒)内将全部功率应用到上部灯，同时解耦下部灯的功率比。以这种方式，晶片温度能够快速攀升而基座温度显著滞后。晶片温度优选从加载温度升高大约100℃至大约400℃，且更优选地升高大约200℃至大约350℃。因为温度尖峰和刻蚀阶段的短持续时间，在基座有可能达到尖峰温度之前允许晶片冷却。以这种方式，与同时循环晶片/基座在一起的更大块组合的温度相比，晶片花费少得多的时间来进行温度循环。用于这一温度尖峰技术的示例性反应器是
Figure G2007800198311D0011080226QIETU
系列单晶 片外延化学气相淀积室，其可以从美国ASM公司(Phoenix，AZ)购得。 
然而，在另一个实施例中，为了帮助维持取代性的碳和电活性掺杂物的高浓度，而同时使温度斜坡/稳定时间最小化，优选保持低的刻蚀温度。在刻蚀时使用低温也也降低刻蚀过程中电活性掺杂物被去激活的可能性。例如，用Cl2气体刻蚀有利地允许刻蚀温度被降低，由此帮助维持取代性的碳和电活性掺杂物。 
刻蚀阶段的低温使得能够粗略匹配淀积阶段的温度，同时利用低温下实现的高掺杂物合并量。可以通过在刻蚀阶段内引进锗源(例如GeH4、GeCl4、金属有机Ge前体、固体Ge源)来提高刻蚀速率以允许这些更低的温度且不牺牲产量，而不是通过使温度快速攀升来提高产量。如本文所用，“等温”循环均厚淀积和刻蚀意味着淀积温度和刻蚀温度相互之间的差值在±50℃内，优选在±10℃内，且最优选地两个步骤的定位点温度在±5℃内。有利地，等温工艺提高了产量并使温度攀升和和温度稳定的时间最小化。类似地，均厚淀积和刻蚀工艺优选是“等压的”，即相互之间的压强差在±50Torr内，优选在±20Torr内。等温和/或等压条件有利于更好的产出以避免攀升时间和稳定时间。 
如图1所示，实施均厚淀积并紧跟着选择性刻蚀的两阶段工艺被任意地循环重复，直到在凹陷源/漏区上实现目标外延薄膜厚度。下面的表A总结了示例性工艺参数，该表列出了优选的操作点以及圆括号中的优选操作范围。从表A可以明显看出，淀积阶段和刻蚀阶段的工艺条件—诸如腔室温度、腔室压强和载体气体流速—优选基本上相似，由此允许增加产量。因此，以下的示例在循环的两个阶段中均使用等温和等压条件。其它参数用于改进的实施例中。 
                          表A 
Figure G2007800198311D00121
利用表A所提供的参数，有可能实现选择性淀积在凹陷源/漏区中的外延Si:C:P薄膜的净生长速率，该净生长速率优选在大约4nm min-1至大约11nm min-1之间，且更优选地在大约8nm min-1至大约11nm min-1之间。还有可能实现薄的Si:C:P薄膜，该Si:C:P薄膜具有通过Vegard定律确定的高达3.6％的替代碳含量，并具有在大约0.4mΩ cm至大约2.0mΩcm之间的电阻率。通过控制淀积条件，有可能获得其它薄膜特性。 
在本文公开的刻蚀工艺过程中，在每个刻蚀阶段，外延Si:C明显比无定形或多晶Si:C刻蚀得慢(刻蚀选择性在10:1—30:1范围内)。在刻蚀阶段还优先去除有缺陷的外延材料。在优选实施例中，对循环淀积和刻蚀工艺条件进行调谐以降低或消除氧化物上的净生长，同时在每个循环中实现外延凹陷源/漏区中的净生长。这一循环工艺与常规选择性淀积工艺的区别在于同时进行淀积和刻蚀反应。 
下面的表B和表C给出使用类似于表A的配方所得到的淀积和刻蚀持续时间以及厚度的两种示例。不同地调谐这些配方以通过增大Si3H8的局部压强并优化刻蚀剂的局部压强来调整淀积速率和刻蚀速率。 
                         表B 
Figure G2007800198311D00141
每个循环的最终时间[s]         122.8 
每个循环的最终厚度[nm]        8.96 
平均生长速率[nm/min]          4.38 
                            表C 
Figure G2007800198311D00142
每个循环的最终时间[s]      61.3 
每个循环的最终厚度[nm]     9.977 
平均生长速率[nm/min]       9.76 
表A中提供的工艺参数显示出Cl2/HCl刻蚀化学药品。在改进的实施例中，在大约20sccm至大约200sccm之间的10％GeH4被包含在刻蚀化学药品中作为刻蚀催化剂。在某些实施例中，在刻蚀化学药品中包含锗源(例如，锗烷如GeH4、GeCl4、金属有机Ge前体、固态Ge源) 可以有利地提高刻蚀速率和刻蚀选择性。另外，使用锗作为催化剂还有利地允许使用更低的刻蚀温度，并允许忽略开始过程中的温度尖峰，如上面关于等温工艺的讨论。关于在无定形硅、多晶硅和单晶硅中扩散锗及随后刻蚀富含Ge的硅材料的额外信息在以下文献中提供，参见例如Mitchell et al.，＂Germanium diffusion in polysilicon emitters of SiGeheterojunction bipolar transistors fabricated by germanium implantation＂，J.of Appl.Phys，92(11)，pp.6924-6926(1December 2002)，Wu et al.， ＂Stability and mechanism of selective etching of ultrathin Ge films on theSi(100)surface，＂Phys.Rev.B，69(2004)和Bogumilowicz et al.，＂Chemicalvapour etching of Si，SiGe and Ge with HCl；applications to the formation ofthin relaxed SiGe buffers and to the revelation of threading dislocations uponchlorine adsorption，＂Semicond.Sci.& Tech.，no.20，pp.127-134，(2005)。 
图6示出掺杂碳的硅薄膜的无定形区的刻蚀速率随刻蚀化学药品中HCl局部压强变化的图表，该过程处于600℃的恒定温度。在某些实施例中，通过降低H2载体流量，HCl和GeH4的局部压强增大，由此显著增大无定形刻蚀速率。例如，图6显示在刻蚀化学药品(符号
Figure G2007800198311D0015080837QIETU
和▲)中包含20sccm的10％ GeH4导致基本上更高的无定形刻蚀速率。 
图7示出针对不同刻蚀化学药品，刻蚀速率和无定形/外延刻蚀速率比随刻蚀化学药品中GeH4流量变化的图表，该过程处于以下条件：600℃的恒定温度、2slm的恒定H2载体流速以及64Torr的恒定腔室压强。无定形刻蚀速率在图例中用前缀“a-”指代，外延刻蚀速率在图例中用前缀“c-”指代，而刻蚀速率比在图例中用“ER”指代。增大GeH4的流量导致无定形/外延刻蚀速率比增大到某一点，超过此点，额外的GeH4降低刻蚀选择性。例如，图7显示包含200sccm的HCl和大约30-40sccm的10％GeH4的刻蚀化学药品产生一个不可能用更低或更高GeH4流量获得的无定形/外延刻蚀速率比。 
图8示出针对刻蚀化学药品中不同的GeH4流速，Si:C薄膜的无定形区的刻蚀速率随腔室压强变化的图表，该过程处于以下条件：550℃的恒定腔室温度、2slm的恒定H2载体流速以及200sccm的恒定HCl刻蚀剂流速。通过增大腔室压强超过大约80Torr，刻蚀速率对GeH4流量的依赖性降低。然而，当50sccm的10％GeH4被引入到刻蚀化学药品中时，通过使腔室压强从大约64Torr升高到大约80Torr，无定形刻蚀速率被提高大约两倍。 
图9示出掺杂碳的硅薄膜的无定形区的刻蚀速率随温度的倒数变化的图表，该过程处于以下条件：64Torr的恒定腔室压强、2slm的恒定H2载体流速、200sccm的恒定HCl刻蚀剂流速以及10％GeH4的50sccm的恒定GeH4刻蚀剂流速。即使在很低的温度下，对于这些化学制 品来说，绝对刻蚀速率也非常高。 
图10示出掺杂碳的硅薄膜的无定形区的厚度随积累的刻蚀时间变化的图表，该过程处于以下条件：64Torr的恒定腔室压强、550℃的恒定腔室温度、2slm的恒定H2载体流速以及200sccm的恒定HCl刻蚀剂流速。图10中绘制的图线的斜率对应于无定形Si:C薄膜的刻蚀速率。如所指出，所淀积薄膜的中心处的刻蚀速率大于所淀积薄膜的边缘处的刻蚀速率。因此在优选实施例中，晶片被“过刻蚀(overetch)”以增加从更慢刻蚀的晶片边缘去除无定形Si:C的可能性。通过将图10中绘制的图线外推至y轴，有可能估计初始无定形薄膜厚度和生长速率。类似地，通过将图10中绘制的图线外推至x轴，有可能估计完全刻蚀无定形材料所需要的时间。图10图示说明通过所提供的工艺参数获得了大约140
Figure G2007800198311D0016081047QIETU
min-1的刻蚀速率。 
 图11示出晶片上淀积的掺杂碳的硅薄膜的无定形区的刻蚀速率随晶片上的径向位置变化的图表，该过程处于以下条件：550℃的恒定腔室温度、64Torr的恒定腔室压强、2slm的恒定H2载体流速以及200sccm的恒定HCl刻蚀剂流速。图11显示晶片边缘处的刻蚀速率比晶片中心处的刻蚀速率稍微慢一些。 
 图12示出针对不同刻蚀循环持续时间，晶片上淀积的掺杂碳的硅薄膜的无定形区的厚度随晶片上的径向位置变化的图表，该过程处于以下条件：550℃的恒定腔室温度、80Torr的恒定腔室压强、2slm的恒定H2载体流速、200sccm的恒定HCl刻蚀剂流速以及6.5sccm的恒定GeH4刻蚀剂流速。 
 图13示出针对不同GeH4刻蚀剂的刻蚀化学药品和不同刻蚀循环持续时间，晶片上淀积的掺杂碳的硅薄膜的无定形区的厚度随晶片上的径向位置变化的图表。如图13所图示说明，更长的刻蚀循环和更高的GeH4流速导致更不均匀的刻蚀。在改进的实施例中，通过提供最终刻蚀循环的延长的持续时间来补偿这一效应，由此提供充分的“过刻蚀”以去除晶片中心处剩余的无定形Si:C。相应地，希望在每个循环中淀积和刻蚀相对小的厚度，优选在大约1nm/循环至10nm/循环之间，更优选地在大约2nm/循环至5nm/循环之间。如上所述，已经利用类似表A的条件来实现 4-11nm/min的净淀积速率。 
图14是图示说明示例性局部成形的掺杂碳的硅结构的照片，该掺杂碳的硅结构是通过在图案化衬底上实施一次淀积循环和一次刻蚀循环所产生的。如图所示，晶体Si:C:P出现在外延衬底区上，而无定形Si:C:P出现在氧化物上。在无定形/外延的界面上出现无定形袋区，因为淀积是以依赖于暴露的结晶取向的不同生长速率发生的。在图14所图示说明的结构中，无定形刻蚀速率与外延刻蚀速率之间的比率超过20。图16是图示说明示例性局部成形的掺杂碳的硅结构的照片，该掺杂碳的硅结构是通过在图案化衬底上实施多次淀积和刻蚀循环所产生的。与图14相比，基本上所有的无定形Si:C:P都已经从氧化物表面上去除，导致伪选择性外延形成。图17图示说明已经利用本文公开的某些技术选择性淀积的外延掺杂碳的硅薄膜的原子力显微分析。 
图15示出元素浓度随示例性局部成形的掺杂碳的硅薄膜的厚度变化的图表，该掺杂碳的硅薄膜是利用本文公开的一些技术形成的。如图所示，由于在刻蚀阶段使用GeH4，相对最适量的锗被合并到Si:C薄膜中。优选地，锗的合并量小于大约5％的原子数百分比，更优选地小于大约2％的原子数百分比，而最优选地小于大约1％的原子数百分比。 
 图18示出利用本文公开的某些技术淀积的掺杂碳的硅薄膜的X射线衍射摇摆曲线。这些曲线指示不同量的淀积/刻蚀循环，并且对应于增大的甲基硅甲烷(monomethylsilane)(“MMS”)流量，这对应于硅外延薄膜中更高的取代性C浓度。 
本文公开的用于选择性外延淀积Si:C薄膜的技术提供超越传统技术的若干优点。例如，从绝缘体区循环去除多晶的或无定形的Si:C有助于改善无定形Si:C和外延Si:C之间的界面。特别地，循环工艺允许外延生长发生在界面区，否则在界面区将发生非外延生长。此外，在一些实施例中刻蚀过程中的温度尖峰被忽略，从而在等于或仅稍微高于淀积循环温度的温度下进行刻蚀循环，这时更低的温度带来很多优点。通过最小化温度(和/或压强)斜坡和稳定时间来提高产量。淀积温度可以仍然足够低以实现高的(例如，1.0-3.6％C百分含量)替代碳含量，且在刻蚀过程中大部分取代性碳和电活性掺杂剂保留在原位置，由此导致所得 的薄膜中高的取代性碳浓度和掺杂剂浓度。 
 一些特征有助于高生产能力。例如，已经发现使用丙硅烷可以在非常低的温度下提高淀积速率，因此最小化淀积阶段的持续时间，而不牺牲例如由更低温度和更高淀积速率所导致淀积的高取代性掺杂剂浓度。前体的次序和选择也促进无定形绝缘区上的大部分或甚至完全的无定形淀积，同时还导致单晶区和无定形区上相对均匀的厚度(厚度比小于1.6:1)，由此最小化刻蚀阶段中的整体刻蚀时间。 
 虽然前述详细的说明公开了本发明的若干实施例，但应该理解这一公开是示例性的，并不限制本发明。应该了解所公开的具体构型和操作可以不同于上述的那些，且本文所述的这些方法可以用于除半导体器件的制作以外的其它背景中。

Claims (46)

1.一种在半导体窗口中选择性形成半导体材料的方法，其包括：
在化学气相淀积室中提供衬底，所述衬底包括绝缘表面和单晶半导体表面；
在所述衬底的所述绝缘表面和所述单晶半导体表面上均厚淀积半导体材料，从而使所述绝缘表面上的非外延半导体材料与所述单晶半导体表面上的外延半导体材料的厚度比率小于1.6∶1；以及
通过将所述均厚淀积的半导体材料暴露于包含锗源的刻蚀化学物质，从所述绝缘表面上选择性去除所述非外延半导体材料，
其中在所述化学气相淀积室中进行均厚淀积和选择性去除。
2.如权利要求1所述的方法，其进一步包括在多个循环中重复均厚淀积和选择性去除，其中每个循环在所述单晶半导体表面上添加一定厚度的外延材料。
3.如权利要求2所述的方法，其中所述半导体材料包括掺杂碳的硅。
4.如权利要求3所述的方法，其中所述掺杂碳的硅包括原子数百分比为0.1％至3.6％的替代碳。
5.如权利要求2所述的方法，其中所述单晶半导体表面包括凹陷的源/漏区，且所述外延材料对中间沟道区施加应变。
6.如权利要求5所述的方法，其中选择性去除包括从所述凹陷的源/漏区的侧壁去除外延材料，而留下所述凹陷的源/漏区底部的外延材料。
7.如权利要求2所述的方法，其中均厚淀积包括非选择性淀积。
8.如权利要求2所述的方法，其中均厚淀积包括使不含卤化物的蒸汽源流动。
9.如权利要求2所述的方法，其中均厚淀积包括在所述绝缘表面上主要形成无定形半导体材料。
10.如权利要求2所述的方法，其中每次均厚淀积步骤在所述绝缘表面上淀积的非外延材料厚度与在所述单晶半导体表面上淀积的外延材料厚度之比在1.0∶1至1.3∶1范围内。
11.如权利要求2所述的方法，其中所述外延材料包括原位掺杂磷和碳的硅。
12.如权利要求11所述的方法，其中所述外延材料具有在0.4mΩ-cm至2mΩ-cm之间的电阻系数。
13.如权利要求2所述的方法，其中均厚淀积和选择性去除均在相互之间温差在±10℃内的条件下进行。
14.如权利要求2所述的方法，其中均厚淀积和选择性去除均在相互之间温差在±5℃内的条件下进行。
15.如权利要求1所述的方法，其中选择性去除包括使锗源和卤化物源流动进入所述化学气相淀积室。
16.如权利要求1所述的方法，其中均厚淀积包括使丙硅烷流动进入所述化学气相淀积室。
17.如权利要求16所述的方法，其中均厚淀积进一步包括使适当的碳源和适当的电掺杂剂源流动进入所述化学气相淀积室。
18.一种选择性形成外延半导体材料的方法，其包括：
均厚淀积半导体材料，以在衬底的单晶半导体区上形成外延材料，并在所述衬底的绝缘区上形成非外延材料；以及
通过将所述均厚淀积的半导体材料暴露于刻蚀化学物质以从所述绝缘区上选择性去除所述非外延材料，所述刻蚀化学物质包括卤化物源和锗源；以及
重复至少一次均厚淀积和选择性去除。
19.如权利要求18所述的方法，其中均厚淀积包括使丙硅烷流动进入容纳所述衬底的化学气相淀积室中。
20.如权利要求18所述的方法，其中均厚淀积包括在每次循环中淀积1nm至10nm。
21.如权利要求18所述的方法，其中均厚淀积和选择性去除是在化学气相淀积室中进行的等温和等压处理。
22.如权利要求18所述的方法，其中所述半导体区包括凹陷区。
23.如权利要求22所述的方法，其中所述凹陷区中的所述外延材料对相邻的所述衬底的区域施加张力。
24.如权利要求18所述的方法，其中所述半导体材料包括掺杂碳的硅。
25.一种在衬底上的选择位置中形成含硅材料的方法，所述方法包括：
提供衬底，所述衬底具有暴露在场氧隔离区之中的单晶半导体窗口；
通过使丙硅烷流动经过所述衬底，在单晶材料的所述窗口和所述场氧隔离区之上均厚淀积含硅材料；以及
通过将所述均厚淀积的半导体材料暴露于包含锗源的刻蚀化学物质，从所述场氧隔离区上选择性去除所述含硅材料；以及
在多个循环中重复均厚淀积和选择性去除。
26.如权利要求25所述的方法，其中均厚淀积所述含硅材料包括使带有丙硅烷的碳源蒸汽流动经过所述衬底，且所述含硅材料包括掺杂碳的硅。
27.如权利要求26所述的方法，其中选择性去除包括以比从所述单晶半导体窗口上去除外延材料更快的速率从所述场氧隔离区上刻蚀非外延材料。
28.如权利要求27所述的方法，其中所述窗口包括凹陷区，且选择性去除进一步包括从所述凹陷区的侧壁上去除外延材料，而在所述凹陷区的底部留下外延材料。
29.如权利要求25所述的方法，其中选择性去除进一步包括使所述衬底暴露于卤化物刻蚀剂。
30.如权利要求25所述的方法，其中所述单晶半导体窗口包括相对于所述场氧隔离区的上表面的凹陷区。
31.如权利要求25所述的方法，其中均厚淀积和选择性去除在等温和/或等压条件下进行。
32.如权利要求25所述的方法，其中均厚淀积和选择性去除产生在4nm/min至11nm/min之间的所述含硅材料的净生长速率。
33.一种选择性形成外延半导体材料的方法，其包括：
提供带有绝缘区和其中形成有半导体窗口的衬底；
在所述绝缘区上淀积无定形半导体材料，并在所述半导体窗口上淀积外延半导体材料；以及
通过将所述均厚淀积的半导体材料暴露于包含锗源的刻蚀化学物质，从所述绝缘区上选择性刻蚀所述无定形半导体材料，而在所述半导体窗口中留下至少一些外延半导体材料；以及
在多个循环中重复均厚淀积和选择性去除。
34.如权利要求33所述的方法，其中所述半导体窗口包括在所述绝缘区的上表面之下的凹陷区，且重复包括用外延半导体材料填充所述凹陷区。
35.如权利要求34所述的方法，其中淀积包括用掺杂碳的硅填充所述凹陷区以形成凹陷的源/漏结构。
36.如权利要求35所述的方法，其中淀积进一步包括原位提供电掺杂剂给所述凹陷的源/漏结构。
37.如权利要求35所述的方法，其中淀积包括形成掺杂碳的硅。
38.如权利要求37所述的方法，其中淀积进一步包括在所述掺杂碳的硅上形成无碳覆盖层。
39.如权利要求33所述的方法，其中重复包括形成升高的源/漏结构。
40.如权利要求33所述的方法，其中淀积包括淀积掺杂磷和碳的硅。
41.如权利要求33所述的方法，其中所述半导体窗口包括在所述绝缘区的上表面之下的凹陷区，且所述凹陷区中的所述外延半导体材料对相邻区域施加横向的拉伸应变。
42.如权利要求41所述的方法，其中所述相邻区域是晶体管沟道区。
43.如权利要求41所述的方法，其中选择性去除进一步包括从所述凹陷区的侧壁上去除外延材料，而在所述凹陷区的底部留下外延材料。
44.如权利要求33所述的方法，其中选择性刻蚀包括将所述衬底暴露于氯源和锗源。
45.如权利要求33所述的方法，其中在每个淀积步骤，所述绝缘区上的无定形半导体材料与所述半导体窗口上的所述外延半导体材料的厚度比率小于1.6∶1。
46.如权利要求45所述的方法，其中所述比率在1.0∶1至1.3∶1之间。
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