JP5431646B2 - 成形チップの製造方法および装置 - Google Patents

成形チップの製造方法および装置 Download PDF

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Publication number
JP5431646B2
JP5431646B2 JP2006526964A JP2006526964A JP5431646B2 JP 5431646 B2 JP5431646 B2 JP 5431646B2 JP 2006526964 A JP2006526964 A JP 2006526964A JP 2006526964 A JP2006526964 A JP 2006526964A JP 5431646 B2 JP5431646 B2 JP 5431646B2
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Japan
Prior art keywords
led
matrix material
leds
forming cavity
coating material
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Expired - Lifetime
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JP2006526964A
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English (en)
Japanese (ja)
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JP2007506279A (ja
JP2007506279A5 (enExample
Inventor
エス．レオン マイケル
ジェイ．ターサ エリック
イベットソン ジェームズ
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Wolfspeed Inc
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Cree Inc
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Publication of JP2007506279A5 publication Critical patent/JP2007506279A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/851—Wavelength conversion means
    • H10H20/8511—Wavelength conversion means characterised by their material, e.g. binder
    • H10H20/8512—Wavelength conversion materials
    • H10H20/8513—Wavelength conversion materials having two or more wavelength conversion materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/851—Wavelength conversion means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0361—Manufacture or treatment of packages of wavelength conversion means

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Casting Or Compression Moulding Of Plastics Or The Like (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2006526964A 2003-09-18 2004-09-13 成形チップの製造方法および装置 Expired - Lifetime JP5431646B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/666,399 2003-09-18
US10/666,399 US7915085B2 (en) 2003-09-18 2003-09-18 Molded chip fabrication method
PCT/US2004/029916 WO2005029580A2 (en) 2003-09-18 2004-09-13 Connector

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2012026326A Division JP2012138587A (ja) 2003-09-18 2012-02-09 成形チップの製造方法および装置
JP2012026327A Division JP6058894B2 (ja) 2003-09-18 2012-02-09 成形チップの製造方法および装置

Publications (3)

Publication Number Publication Date
JP2007506279A JP2007506279A (ja) 2007-03-15
JP2007506279A5 JP2007506279A5 (enExample) 2007-11-08
JP5431646B2 true JP5431646B2 (ja) 2014-03-05

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Family Applications (3)

Application Number Title Priority Date Filing Date
JP2006526964A Expired - Lifetime JP5431646B2 (ja) 2003-09-18 2004-09-13 成形チップの製造方法および装置
JP2012026326A Pending JP2012138587A (ja) 2003-09-18 2012-02-09 成形チップの製造方法および装置
JP2012026327A Expired - Lifetime JP6058894B2 (ja) 2003-09-18 2012-02-09 成形チップの製造方法および装置

Family Applications After (2)

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JP2012026326A Pending JP2012138587A (ja) 2003-09-18 2012-02-09 成形チップの製造方法および装置
JP2012026327A Expired - Lifetime JP6058894B2 (ja) 2003-09-18 2012-02-09 成形チップの製造方法および装置

Country Status (5)

Country Link
US (6) US7915085B2 (enExample)
EP (2) EP1665361B1 (enExample)
JP (3) JP5431646B2 (enExample)
TW (1) TWI358837B (enExample)
WO (1) WO2005029580A2 (enExample)

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US9159888B2 (en) * 2007-01-22 2015-10-13 Cree, Inc. Wafer level phosphor coating method and devices fabricated utilizing method
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