JP4865197B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP4865197B2
JP4865197B2 JP2004194690A JP2004194690A JP4865197B2 JP 4865197 B2 JP4865197 B2 JP 4865197B2 JP 2004194690 A JP2004194690 A JP 2004194690A JP 2004194690 A JP2004194690 A JP 2004194690A JP 4865197 B2 JP4865197 B2 JP 4865197B2
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Japan
Prior art keywords
semiconductor device
semiconductor element
semiconductor
wiring
electrode
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Expired - Lifetime
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JP2004194690A
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English (en)
Japanese (ja)
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JP2006019433A5 (https=
JP2006019433A (ja
Inventor
洋一郎 栗田
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Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2004194690A priority Critical patent/JP4865197B2/ja
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to US11/159,157 priority patent/US7795721B2/en
Publication of JP2006019433A publication Critical patent/JP2006019433A/ja
Publication of JP2006019433A5 publication Critical patent/JP2006019433A5/ja
Priority to US12/169,930 priority patent/US8193033B2/en
Priority to US12/850,232 priority patent/US8207605B2/en
Application granted granted Critical
Publication of JP4865197B2 publication Critical patent/JP4865197B2/ja
Priority to US13/495,494 priority patent/US8541874B2/en
Priority to US13/972,162 priority patent/US8890305B2/en
Priority to US14/524,718 priority patent/US9324699B2/en
Priority to US15/072,803 priority patent/US20160204092A1/en
Priority to US16/375,282 priority patent/US10672750B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
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    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
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    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
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    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
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    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
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    • H10W74/00—Encapsulations, e.g. protective coatings
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    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
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    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
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    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
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    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body
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    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
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    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
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    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
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    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
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    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2004194690A 2004-06-30 2004-06-30 半導体装置およびその製造方法 Expired - Lifetime JP4865197B2 (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP2004194690A JP4865197B2 (ja) 2004-06-30 2004-06-30 半導体装置およびその製造方法
US11/159,157 US7795721B2 (en) 2004-06-30 2005-06-23 Semiconductor device and method for manufacturing the same
US12/169,930 US8193033B2 (en) 2004-06-30 2008-07-09 Semiconductor device having a sealing resin and method of manufacturing the same
US12/850,232 US8207605B2 (en) 2004-06-30 2010-08-04 Semiconductor device having a sealing resin and method of manufacturing the same
US13/495,494 US8541874B2 (en) 2004-06-30 2012-06-13 Semiconductor device
US13/972,162 US8890305B2 (en) 2004-06-30 2013-08-21 Semiconductor device
US14/524,718 US9324699B2 (en) 2004-06-30 2014-10-27 Semiconductor device
US15/072,803 US20160204092A1 (en) 2004-06-30 2016-03-17 Semiconductor device
US16/375,282 US10672750B2 (en) 2004-06-30 2019-04-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004194690A JP4865197B2 (ja) 2004-06-30 2004-06-30 半導体装置およびその製造方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2009114222A Division JP5171726B2 (ja) 2009-05-11 2009-05-11 半導体装置
JP2009298355A Division JP5091221B2 (ja) 2009-12-28 2009-12-28 半導体装置

Publications (3)

Publication Number Publication Date
JP2006019433A JP2006019433A (ja) 2006-01-19
JP2006019433A5 JP2006019433A5 (https=) 2007-10-11
JP4865197B2 true JP4865197B2 (ja) 2012-02-01

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JP2004194690A Expired - Lifetime JP4865197B2 (ja) 2004-06-30 2004-06-30 半導体装置およびその製造方法

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US (8) US7795721B2 (https=)
JP (1) JP4865197B2 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20200031322A (ko) 2018-09-14 2020-03-24 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
US10991673B2 (en) 2018-01-04 2021-04-27 Kabushiki Kaisha Toshiba Electronic device

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JP4865197B2 (ja) 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP4880218B2 (ja) * 2004-12-22 2012-02-22 三洋電機株式会社 回路装置
JP2006216911A (ja) * 2005-02-07 2006-08-17 Renesas Technology Corp 半導体装置およびカプセル型半導体パッケージ
JP4507101B2 (ja) 2005-06-30 2010-07-21 エルピーダメモリ株式会社 半導体記憶装置及びその製造方法
JP4787559B2 (ja) * 2005-07-26 2011-10-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US20070252260A1 (en) * 2006-04-28 2007-11-01 Micron Technology, Inc. Stacked die packages
JP2008016508A (ja) * 2006-07-03 2008-01-24 Nec Electronics Corp 半導体装置およびその製造方法
JP2008091638A (ja) 2006-10-02 2008-04-17 Nec Electronics Corp 電子装置およびその製造方法
WO2008066028A1 (en) * 2006-11-30 2008-06-05 Panasonic Corporation Interposer with built-in passive part
JP4897451B2 (ja) * 2006-12-04 2012-03-14 ルネサスエレクトロニクス株式会社 半導体装置
JP5183949B2 (ja) 2007-03-30 2013-04-17 日本電気株式会社 半導体装置の製造方法
JP5125185B2 (ja) * 2007-04-03 2013-01-23 株式会社ニコン 半導体装置
JP2008294423A (ja) 2007-04-24 2008-12-04 Nec Electronics Corp 半導体装置
KR100909322B1 (ko) * 2007-07-02 2009-07-24 주식회사 네패스 초박형 반도체 패키지 및 그 제조방법
JP5068133B2 (ja) * 2007-10-17 2012-11-07 新光電気工業株式会社 半導体チップ積層構造体及び半導体装置
KR20090056044A (ko) * 2007-11-29 2009-06-03 삼성전자주식회사 반도체 소자 패키지 및 이를 제조하는 방법
KR100925665B1 (ko) * 2007-12-10 2009-11-06 주식회사 네패스 시스템 인 패키지 및 그 제조 방법
US8456002B2 (en) 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US8343809B2 (en) * 2010-03-15 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
US7767496B2 (en) 2007-12-14 2010-08-03 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure for encapsulated die having pre-applied protective layer
US8183095B2 (en) 2010-03-12 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US9318441B2 (en) 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
US7867819B2 (en) 2007-12-27 2011-01-11 Sandisk Corporation Semiconductor package including flip chip controller at bottom of die stack
WO2009084300A1 (ja) 2007-12-28 2009-07-09 Ibiden Co., Ltd. インターポーザー及びインターポーザーの製造方法
EP2187438A1 (en) 2007-12-28 2010-05-19 Ibiden Co., Ltd. Interposer and manufacturing method of the interposer
US8273603B2 (en) * 2008-04-04 2012-09-25 The Charles Stark Draper Laboratory, Inc. Interposers, electronic modules, and methods for forming the same
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US20190229104A1 (en) 2019-07-25
US8207605B2 (en) 2012-06-26
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US9324699B2 (en) 2016-04-26
US8890305B2 (en) 2014-11-18
US20130334705A1 (en) 2013-12-19
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US20100314749A1 (en) 2010-12-16
US20080265434A1 (en) 2008-10-30

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