TWI485826B - 晶片堆疊結構以及晶片堆疊結構的製作方法 - Google Patents

晶片堆疊結構以及晶片堆疊結構的製作方法 Download PDF

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TWI485826B
TWI485826B TW101118718A TW101118718A TWI485826B TW I485826 B TWI485826 B TW I485826B TW 101118718 A TW101118718 A TW 101118718A TW 101118718 A TW101118718 A TW 101118718A TW I485826 B TWI485826 B TW I485826B
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Taiwan
Prior art keywords
wafer
layer
carrier
stack structure
fabricating
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TW101118718A
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English (en)
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TW201349408A (zh
Inventor
Sheng Tsai Wu
John H Lau
Heng Chieh Chien
Ra Min Tain
Ming Ji Dai
Yu Lin Chao
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Ind Tech Res Inst
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Priority to TW101118718A priority Critical patent/TWI485826B/zh
Priority to US13/586,890 priority patent/US8519524B1/en
Publication of TW201349408A publication Critical patent/TW201349408A/zh
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Publication of TWI485826B publication Critical patent/TWI485826B/zh

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Description

晶片堆疊結構以及晶片堆疊結構的製作方法
本發明是有關於一種晶片堆疊結構與晶片堆疊製程，且特別是有關於一種三維晶片堆疊結構(three-dimensional Chip stacking structure)與三維晶片堆疊製程。
近代電子產業隨著摩爾定律規範(Moore’s Law)而蓬勃發展。然而，隨著電子產品的運算速度提升等需求，技術的瓶頸也逐漸產生。為了讓電子產品的性能跟上需求，於是，三維積體電路構裝(3D IC integration)技術成為現今解決問題的辦法之一。
三維積體電路構裝技術相較於一般傳統封裝形式擁有許多優點，例如元件尺寸較小、較少的訊號損失與較好的電性性能，這些都是因為使用矽導通孔(Through Silicon Via,TSV)的緣故。
矽導通孔已成為三維積體電路構裝技術的重要核心之一，必須審慎考量在矽導通孔製程成本的問題。典型含矽導通孔的中介層(TSV interposer)的三維積體電路整合系統級封裝(3D IC SiP)結構，其中，中介層利用微凸塊(microbump)結構，在上下方皆可承載晶片，且透過焊錫凸塊(solder bump)結構而可與基板(substrate)或印刷電路板(PCB)連結。
通常製作矽導通孔的結構需要五個步驟：
第一，利用雷射穿孔(laser drilling)或是深反應離子蝕刻(deep reactive ion etch,DRIE)製程先讓通孔成型。
第二，利用電漿增強型化學氣相沈積(PECVD)方法沈積絕緣層(dielectric deposition)。
第三，利用物理氣相沈積(PVD)方法沈積阻障層/電鍍種子層(barrier/seed layer)。
第四，使用電鍍銅填滿通孔(via Cu-filling)。
第五，利用化學機械研磨(chemical and mechanical polishing,CMP)製程移除突出或多餘的材料。
比較上述五個製程成本高低分別為：PVD>PECVD>CMP>Plating>Etching。
詳細而言，三維積體電路構裝技術為提升電子產品性能的最有效架構之一，可允許多個晶片間的相互連結，將更多的運算能力、記憶體和其他功能整合在同一極小裝置內。然而，習知利用矽導通孔的三維積體電路構裝需要使用PVD、PECVD等製程。如此一來，存在著高寬比範圍難以突破的技術限制(通孔無法填滿銅)。更因為昂貴的真空、乾式製程設備和耗材等問題，導致矽導通孔的製程成本十分昂貴。
有鑑於此，如何解決在三維積體電路構裝技術中，矽導通孔成本昂貴之問題是非常急迫且需要的。
本發明提供一種晶片堆疊結構，具有簡單的結構。
本發明提供一種晶片堆疊結構的製作方法，具有低製作成本。
此晶片堆疊結構，包括：承載器、第一重佈線層、第二重佈線層、至少一第一晶片、至少一第二晶片以及至少一導電物。承載器具有彼此對向的第一表面與第二表面，承載器具有至少一貫通孔。第一重佈線層設置於承載器的第一表面。第二重佈線層設置於承載器的第二表面。第一晶片設置於承載器的第一表面且電性連接第一重佈線層。第二晶片設置於承載器的第二表面且電性連接第二重佈線層。導電物設置於第一晶片與第二晶片的其中之一，導電物位於貫通孔中，且藉由導電物而電性連接第一晶片與第二晶片，其中，導電物與包圍貫通孔的承載器的內壁之間相距一間隙。
此晶片堆疊結構的製作方法為：提供承載器，具有彼此對向的第一表面與第二表面，承載器具有至少一貫通孔，且承載器的第一表面設置有第一重佈線層，承載器的第二表面設置有第二重佈線層；提供至少一第一晶片，對向於承載器的第一表面；提供至少一第二晶片，對向於承載器的第二表面，其中，第一晶片與第二晶片的其中之一設置有至少一導電物；以及使導電物通過貫通孔，而電性連接第一晶片與第二晶片，其中，導電物與包圍貫通孔的承載器的內壁之間相距一間隙。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1為本發明的實施例的晶片堆疊結構的示意圖。請參照圖1，晶片堆疊結構100包括：承載器110、第一重佈線層120、第二重佈線層130、至少一第一晶片140、至少一第二晶片150以及至少一導電物160。承載器110具有彼此對向的第一表面112與第二表面114，承載器110具有至少一貫通孔H。第一重佈線層120設置於承載器110的第一表面112。第二重佈線層130設置於承載器110的第二表面114。第一晶片140設置於承載器110的第一表面112且電性連接第一重佈線層120。第二晶片150設置於承載器110的第二表面114且電性連接第二重佈線層130。導電物160設置於第一晶片140與第二晶片150的其中之一，導電物160位於貫通孔H中，且藉由導電物160而電性連接第一晶片140與第二晶片150，其中，導電物160與包圍貫通孔H的承載器110的內壁之間相距間隙D。
所謂的「導電物160設置於第一晶片140與第二晶片150的其中之一」的意義是，導電物160可與第一晶片140製作在一起，或者，導電物160可與第二晶片150製作在一起。導電物160可以是導電線、導電柱或導電墊，適於穿過承載器100的貫通孔H。另外，導電物160可以是是選自於金、銅、鎳、銀及其組合。在後述圖5A~圖5H、 會再詳細說明將導電物160製作在第一晶片140或第二晶片150的製程。
請參照圖1，第一晶片140與第二晶片150是經由位於貫通孔H中的導電物160而彼此電性連接的，且導電物160與包圍貫通孔H的承載器110的內壁之間相距間隙D，詳言之，晶片堆疊結構100的貫通孔H中未進行任何的金屬化製程。
再者，間隙D中可填充有空氣或惰性氣體，當填充惰性氣體時，可使導電物160不易氧化，而保持晶片堆疊結構100的運作順暢。另外，間隙D中還可填充有絕緣填料，可提升晶片堆疊結構100的結構強度。
圖2A為圖1的第一晶片的局部放大示意圖。請同時參照圖1與圖2A，第一晶片140可包括：第一基材142、第一線路層144、第一圖案化絕緣層146以及第一微凸塊148。第一線路層144設置於第一基材142上。第一圖案化絕緣層146覆蓋第一線路層144，第一圖案化絕緣層146暴露出部分的第一線路層144。第一微凸塊148設置接觸於暴露出的第一線路層144上，導電物160可連接於第一微凸塊148。
請再參照圖2A，第一基材142可以是矽晶圓，包含：矽基底142a與氧化矽層142b。而第一微凸塊148可以包括多個膜層148a、148b、148c堆疊構成，例如：膜層148a為TiW膜層，膜層148b為Cu膜層，膜層148c為Ni膜層。
圖2B為圖1的第二晶片的局部放大示意圖。請同時 參照圖1與圖2B，第二晶片150可包括：第二基材152、第二線路層154、第二圖案化絕緣層156及第二微凸塊158。第二線路層154設置於第二基材142上。第二圖案化絕緣層156覆蓋第二線路層154，第二圖案化絕緣層156暴露出部分的第二線路層154。第二微凸塊158設置接觸於暴露出的第二線路層154上。
請再參照圖2B，第二基材152可以是矽晶圓，包含：矽基底152a與氧化矽層152b。而第二微凸塊158可以包括多個膜層158a、158b、158c堆疊構成，例如：膜層158a為TiW膜層，膜層158b為Cu膜層，膜層158c為Ni膜層。
如圖2A與圖2B所繪示的實施例是，第一晶片140上製作有導電物160，第二晶片150上未製作導電物160。然而，也可以是以下的多種實施狀態，亦即：第二晶片150上製作有導電物160，第一晶片140上未製作導電物160；或者，也可以是：第一晶片140與第二晶片150上都製作有導電物160，但成為彼此交錯的方式。無論以何種方式來製作導電物160，最終之目的是：使導電物160可以順利地插入到貫通孔H中，以進行承載器110、第一晶片140與第二晶片150的組裝作業。
請再參照圖1，第一微凸塊148還可以連接於第一晶片140與第一重佈線層120之間，以使多個第一晶片140彼此之間可以透過第一重佈線層120而彼此電性連接且傳遞電子訊號。第一微凸塊148能夠使第一晶片140穩定地接合於承載器100的第一表面112，以提升晶片堆疊結構100的結構強度。
同樣地，第二微凸塊158可連接於第二晶片150與第二重佈線層130之間，以使多個第二晶片150彼此之間可以透過第二重佈線層130而彼此電性連接且傳遞電子訊號。第二微凸塊158能夠使第二晶片150穩定地接合於承載器100的第二表面112，以提升晶片堆疊結構100的結構強度。
請參照圖1，晶片堆疊結構100還可包括：載板170(carrier)以及焊球180。載板170具有第三重佈線層172，載板170可以是其上具有電路圖案的印刷電路板。焊球180設置於第二重佈線層130與第三重佈線層172之間。
承上所述，晶片堆疊結構100具有簡單的結構，藉由貫通孔H搭配導電物160，可取代習知昂貴的矽導通孔結構(TSV)。在承載器110上的貫通孔H不需額外的金屬層化(metallization)製程，進而能夠有效地降低晶片堆疊結構100的製程成本。
圖3A與圖3B為本發明的晶片堆疊結構的製作方法的示意圖。請同時參照圖1、圖3A~圖3B，晶片堆疊結構的製作方法可包括以下步驟，這些步驟之間的順序，所屬技術領域中具有通常知識者可進行適當的調整。並且，相同的元件標示以相同的符號。
如圖2與圖3A所示，提供承載器110，具有彼此對向的第一表面112與第二表面114，承載器110具有至少一貫通孔H，且承載器110的第一表面112設置有第一重佈線層120，承載器110的第二表面114設置有第二重佈線層130。
如圖2與圖3B所示，提供至少一第一晶片140，對向於承載器110的第一表面112；並且，提供至少一第二晶片150，對向於承載器110的第二表面114，其中，該第一晶片140與第二晶片150的其中之一設置有至少一導電物160。在此實施例中，使第一晶片140具有導電物160。
如圖3B的箭頭所示，使導電物160通過貫通孔H，而電性連接第一晶片140與第二晶片150，其中，導電物160與包圍貫通孔H的承載器110的內壁之間相距間隙D。
可利用定位標記與定位裝置，而能夠使導電物160精準地對準貫通孔H，而能夠將承載器110、第一晶片140與第二晶片150組裝在一起，而製作成晶片堆疊結構100。至於晶片堆疊結構100每一個元件的詳細實施型態，已如上所述，在此即不予以重述。
請參照圖2與圖3B，形成貫通孔H的方法可以是雷射鑽孔法、或離子蝕刻法。當使用離子蝕刻法時，可以使用深反應離子蝕刻(deep reactive ion etch,DRIE)製程。上述的晶片堆疊結構100僅需在承載器110上形成貫通孔H，並不需要如習知的矽導通孔結構(TSV)一樣，在貫通孔H中再電鍍沈積導電層。
圖4A~圖4G本發明的承載器的一個實施例的製作流程示意圖。請參照圖4A~圖4G，提供承載器110的方法包括以下步驟。
首先，如圖4A所示，提供承載晶圓110A，具有彼此對向的第一表面112與第二表面114，且於承載晶圓110A 的第一表面112上形成具有預定深度的非貫通孔UH。可利用雷射鑽孔法或深反應離子蝕刻來進行上述非貫通孔UH的製作。
接著，如圖4B所示，於第一表面112形成第一重佈線層120。形成第一重佈線層120的方式，可以是採用物理濺鍍製程沈積金屬，再利用微影蝕刻方式來形成具有圖案線路的第一重佈線層120。另外，於第一表面112形成第一重佈線層120時，還可以於第一表面112形成第一微凸塊148，此第一微凸塊148(繪示於圖1、圖2A中)。連接於第一重佈線層120。
再來，如圖4C所示，提供支持晶圓SW，接合於承載晶圓110A的第一表面112，而支持承載晶圓110A。
接著，如圖4D所示，從承載晶圓110A的第二表面114移除承載晶圓110A的部分厚度(虛線部分標示處)，使非貫通孔UH自第二表面114暴露出來，而形成貫通孔H。可利用化學機械研磨來進行此一步驟。
再來，如圖4D所示，於第二表面114形成第二重佈線層130。形成第二重佈線層130的方式，可以是採用物理濺鍍製程沈積金屬，再利用微影蝕刻方式來形成具有圖案線路的第二重佈線層130。另外，於第二表面114形成第二重佈線層130時，還可以於第二表面114形成第二微凸塊158(繪示於圖1、圖2B中)，第二微凸塊158連接於第二重佈線層130。
接著，如圖4E所示，提供一焊球180，連接於第二重佈線層130。
繼之，如圖4F所示，將承載晶圓110A經由焊球180而設置於切割膠帶T上、且移除支持晶圓SW。
之後，如圖4G所示，對承載晶圓110A進行切割(如圖4G中的切割虛線所示)，而形成具有至少貫通孔H的承載器110。
以上僅為提供承載器110的一個製作流程的例子，所屬技術領域具有通常知識者，在參照本案上述的說明之後，可以做出適當的設計變更，均包含在本發明的申請專利範圍之內。
圖5A~圖5H為含有導電物的第一晶片或第二晶片的製作流程示意圖。請參照圖1、圖2A~圖2B、圖5A~圖5I來理解相關的製作流程。可以在第一晶片140上製作導電物160；或者，可於第二晶片150上製作導電物160；或者，可於第一晶片140與第二晶片150上都製作導電物160。只要能夠使承載器110、第一晶片140、第二晶片150進行組裝即可。
關於第一晶片140與第二晶片150的其中之一的製作方法可包括以下步驟。
首先，如圖5A所示，提供一晶圓200，晶圓200可先經過清潔製程，以利後續的微影蝕刻製程與電鍍製程。
接著，如圖5B所示，於晶圓200上形成電鍍種子層210。可利用物理濺鍍的方式來形成。電鍍種子層210的材料可以是銅。
再來，如圖5C所示，形成圖案化光阻層230覆蓋該 電鍍種子層210，且圖案化光阻層230具有暴露出電鍍種子層210的孔洞232。
接著，如圖5D所示，進行電鍍製程，而形成導電物160，此導電物160連接於暴露出的電鍍種子層210上。導電物160可包含：焊料層160a(solder joint)與銅層160b。
繼之，如圖5E所示，移除圖案化光阻層230。還可如圖5F所示，將焊料層160a進行迴焊製程，而使焊料層160a形成圓滑的形狀。
再來，如圖5G所示，繪示了多個形成於晶圓200上的多個導電物160，晶圓200上形成有多個第一晶片140或第二晶片150。如圖5H所示，對晶圓200進行切割，而可形成具有導電物的160第一晶片140、或具有導電物160的第二晶片150。
之後，即可將承載器110、第一晶片140、第二晶片150進行組裝，而構成上述的晶片堆疊結構100。
綜上所述，本申請的晶片堆疊結構具有簡單的結構，藉由貫通孔搭配導電物，可取代習知昂貴的矽導通孔結構。由於在承載器上的貫通孔不需額外的金屬層化製程，進而能夠有效地降低晶片堆疊結構的製程成本。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧晶片堆疊結構
110‧‧‧承載器
110A‧‧‧承載晶圓
112‧‧‧第一表面
114‧‧‧第二表面
120‧‧‧第一重佈線層
130‧‧‧第二重佈線層
140‧‧‧第一晶片
142‧‧‧第一基材
142a、152a‧‧‧矽基底
142b、152b‧‧‧氧化矽層
144‧‧‧第一線路層
146‧‧‧第一圖案化絕緣層
148‧‧‧第一微凸塊
148a、148b、148c‧‧‧膜層
150‧‧‧第二晶片
152‧‧‧第二基材
154‧‧‧第二線路層
156‧‧‧第二圖案化絕緣層
158‧‧‧第二微凸塊
158a、158b、158c‧‧‧膜層
160‧‧‧導電物
160a‧‧‧焊料層
160b‧‧‧銅層
170‧‧‧載板
172‧‧‧第三重佈線層
180‧‧‧焊球
200‧‧‧晶圓
210‧‧‧電鍍種子層
230‧‧‧圖案化光阻層
232‧‧‧孔洞
D‧‧‧間隙
H‧‧‧貫通孔
SW‧‧‧支持晶圓
T‧‧‧切割膠帶
UH‧‧‧非貫通孔
圖1為本發明的實施例的晶片堆疊結構的示意圖。
圖2A為圖1的第一晶片的局部放大示意圖。
圖2B為圖1的第二晶片的局部放大示意圖。
圖3A與圖3B為本發明的晶片堆疊結構的製作方法的示意圖。
圖4A~圖4G本發明的承載器的一個實施例的製作流程示意圖。
圖5A~圖5H為含有導電物的第一晶片或第二晶片的製作流程示意圖。
100‧‧‧晶片堆疊結構
110‧‧‧承載器
112‧‧‧第一表面
114‧‧‧第二表面
120‧‧‧第一重佈線層
130‧‧‧第二重佈線層
140‧‧‧第一晶片
148‧‧‧第一微凸塊
150‧‧‧第二晶片
158‧‧‧第二微凸塊
160‧‧‧導電物
170‧‧‧載板
172‧‧‧第三重佈線層
180‧‧‧焊球
D‧‧‧間隙
H‧‧‧貫通孔

Claims (29)

  1. 一種晶片堆疊結構，包括：一承載器，具有彼此對向的一第一表面與一第二表面，該承載器具有至少一貫通孔；一第一重佈線層，設置於該承載器的該第一表面；一第二重佈線層，設置於該承載器的一第二表面；至少一第一晶片，設置於該承載器的該第一表面且電性連接該第一重佈線層；至少一第二晶片，設置於該承載器的該第二表面且電性連接該第二重佈線層；至少一導電物，設置於該第一晶片與該第二晶片的其中之一，該導電物位於該貫通孔中，且藉由該導電物而電性連接該第一晶片與該第二晶片，其中，該導電物與包圍該貫通孔的該承載器的內壁之間相距一間隙。
  2. 如申請專利範圍第1項所述的晶片堆疊結構，其中，該第一晶片包括：一第一基材；一第一線路層，設置於該第一基材；一第一圖案化絕緣層，覆蓋該第一線路層，該第一圖案化絕緣層暴露出部分的該第一線路層；以及一第一微凸塊，設置於暴露出的該第一線路層上，其中，該導電物連接於該第一微凸塊。
  3. 如申請專利範圍第2項所述的晶片堆疊結構，其中，該第一微凸塊包括多個膜層堆疊構成。
  4. 如申請專利範圍第1項所述的晶片堆疊結構，其中，該第二晶片包括：一第二基材；一第二線路層，設置於該第二基材；一第二圖案化絕緣層，覆蓋該第二線路層，該第二圖案化絕緣層暴露出部分的該第二線路層；以及一第二微凸塊，設置於暴露出的該第二線路層上。
  5. 如申請專利範圍第4項所述的晶片堆疊結構，其中，該第二微凸塊包括多個膜層堆疊構成。
  6. 如申請專利範圍第1項所述的晶片堆疊結構，其中，該導電物包括：導電線、導電柱或導電墊。
  7. 如申請專利範圍第1項所述的晶片堆疊結構，其中，該導電物的材質是選自於金、銅、鎳、銀及其組合。
  8. 如申請專利範圍第1項所述的晶片堆疊結構，其中，該第一晶片包括：至少一第一微凸塊，連接於該第一晶片與該第一重佈線層之間。
  9. 如申請專利範圍第1項所述的晶片堆疊結構，其中，該第二晶片包括：至少一第二微凸塊，連接於該第二晶片與該第二重佈線層之間。
  10. 如申請專利範圍第1項所述的晶片堆疊結構，更包括：一載板，具有一第三重佈線層；以及 一焊球，設置於該第二重佈線層與該第三重佈線層之間。
  11. 如申請專利範圍第1項所述的晶片堆疊結構，其中，該間隙填充有空氣或惰性氣體。
  12. 如申請專利範圍第1項所述的晶片堆疊結構，其中，該間隙填充有絕緣填料。
  13. 一種晶片堆疊結構的製作方法，包括：提供一承載器，具有彼此對向的一第一表面與一第二表面，該承載器具有至少一貫通孔，且該承載器的該第一表面設置有一第一重佈線層，該承載器的該第二表面設置有一第二重佈線層；提供至少一第一晶片，對向於該承載器的該第一表面；提供至少一第二晶片，對向於該承載器的該第二表面，其中，該第一晶片與該第二晶片的其中之一設置有至少一導電物；以及使該導電物通過該貫通孔，而電性連接該第一晶片與該第二晶片，其中，該導電物與包圍該貫通孔的該承載器的內壁之間相距一間隙。
  14. 如申請專利範圍第13項所述的晶片堆疊結構的製作方法，其中，該第一晶片包括：一第一基材；一第一線路層，設置於該第一基材；一第一圖案化絕緣層，覆蓋該第一線路層，該第一圖 案化絕緣層暴露出部分的該第一線路層；以及一第一微凸塊，設置於暴露出的該第一線路層上，其中，該導電物連接於該第一微凸塊。
  15. 如申請專利範圍第14項所述的晶片堆疊結構的製作方法，其中，該第一微凸塊包括多個膜層堆疊構成。
  16. 如申請專利範圍第13項所述的晶片堆疊結構的製作方法，其中，該第二晶片包括：一第二基材；一第二線路層，設置於該第二基材；一第二圖案化絕緣層，覆蓋該第二線路層，該第二圖案化絕緣層暴露出部分的該第二線路層；以及一第二微凸塊，設置於暴露出的該第二線路層上。
  17. 如申請專利範圍第16項所述的晶片堆疊結構的製作方法，其中，該第二微凸塊包括多個膜層堆疊構成。
  18. 如申請專利範圍第13項所述的晶片堆疊結構的製作方法，其中，該導電物包括：導電線、導電柱或導電墊。
  19. 如申請專利範圍第13項所述的晶片堆疊結構的製作方法，其中，該導電物的材質是選自於金、銅、鎳、銀及其組合。
  20. 如申請專利範圍第13項所述的晶片堆疊結構的製作方法，其中，該第一晶片包括：至少一第一微凸塊，連接於該第一晶片與該第一重佈線層之間。
  21. 如申請專利範圍第13項所述的晶片堆疊結構的製作方法，其中，該第二晶片包括：至少一第二微凸塊，連接於該第二晶片與該第二重佈線層之間。
  22. 如申請專利範圍第13項所述的晶片堆疊結構的製作方法，更包括：提供一載板，具有一第三重佈線層；以及提供一焊球，設置於該第二重佈線層與該第三重佈線層之間。
  23. 如申請專利範圍第13項所述的晶片堆疊結構的製作方法，其中，該間隙填充有空氣或惰性氣體。
  24. 如申請專利範圍第13項所述的晶片堆疊結構的製作方法，其中，該間隙填充有絕緣填料。
  25. 如申請專利範圍第13項所述的晶片堆疊結構的製作方法，其中，形成該貫通孔的方法包括：雷射鑽孔法、或離子蝕刻法。
  26. 如申請專利範圍第13項所述的晶片堆疊結構的製作方法，其中，提供該承載器的方法包括：提供一承載晶圓，具有彼此對向的該第一表面與該第二表面，且於該承載晶圓的該第一表面上形成具有一預定深度的一非貫通孔；於該第一表面形成該第一重佈線層；提供一支持晶圓，接合於該承載晶圓的該第一表面，而支持該承載晶圓； 從該承載晶圓的該第二表面移除該承載晶圓的部分厚度，使該非貫通孔自該第二表面暴露出來，而形成該貫通孔；於該第二表面形成該第二重佈線層；提供一焊球，連接於該第二重佈線層；將該承載晶圓經由該焊球而設置於一切割膠帶上、且移除該支持晶圓；以及對該承載晶圓進行切割，而形成具有至少該貫通孔的該承載器。
  27. 如申請專利範圍第26項所述的晶片堆疊結構的製作方法，其中，於該第一表面形成該第一重佈線層時，更包括：於該第一表面形成一第一微凸塊，該第一微凸塊連接於該第一重佈線層。
  28. 如申請專利範圍第26項所述的晶片堆疊結構的製作方法，其中，於該第二表面形成該第二重佈線層時，更包括：於該第二表面形成一第二微凸塊，該第二微凸塊連接於該第二重佈線層。
  29. 如申請專利範圍第13項所述的晶片堆疊結構的製作方法，其中，該第一晶片與該第二晶片的其中之一的製作方法包括：提供一晶圓；於該晶圓上形成一電鍍種子層；形成一圖案化光阻層覆蓋該電鍍種子層，且該圖案化光阻層具有暴露出該電鍍種子層的一孔洞； 進行一電鍍製程，而形成該導電物，該導電物連接於暴露出的該電鍍種子層上移除該圖案化光阻層；以及切割該晶圓，而形成具有該導電物的該第一晶片或具有該導電物的該第二晶片。
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