JP4880218B2 - 回路装置 - Google Patents
回路装置 Download PDFInfo
- Publication number
- JP4880218B2 JP4880218B2 JP2004370774A JP2004370774A JP4880218B2 JP 4880218 B2 JP4880218 B2 JP 4880218B2 JP 2004370774 A JP2004370774 A JP 2004370774A JP 2004370774 A JP2004370774 A JP 2004370774A JP 4880218 B2 JP4880218 B2 JP 4880218B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating resin
- semiconductor chip
- resin film
- resin layer
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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Description
図1〜図3は、本発明の第1実施形態における半導体集積回路装置およびその製造工程を示す断面図である。
(i)−CO−A1−CO−
(但しA1は、芳香環を含有する2価の結合基を示す。)
(ii)−O−A2−O−
(但しA2は、芳香環を含有する2価の結合基を示す。)
(iii)−CO−A3−O−
(但しA3は、芳香環を含有する2価の結合基を示す。)
絶縁樹脂膜2には、フィラーまたは繊維等の充填材を含めることができる。フィラーとしては、例えば粒子状または繊維状のSiO2、SiN、AlN、Al2O3などを用いることができる。絶縁樹脂膜2にフィラーや繊維を含めることにより、絶縁樹脂膜2を加熱して半導体チップ1を熱圧着した後、絶縁樹脂膜2を例えば室温に冷却する際に、絶縁樹脂膜2の反りを低減することができる。これにより、半導体チップ1と絶縁樹脂膜2との密着性を高めることができる。また、絶縁樹脂膜2に繊維を含めた場合、絶縁樹脂膜2の剛性を高めることができるため、絶縁樹脂膜2と半導体チップ1との密着性を高めることができる。このような観点からは、絶縁樹脂膜2を構成する材料としてアラミド不織布が好ましく用いられる。これにより、加工性を良好にすることができる。
バイアス(W): 100
RFパワー(W): 500
圧力(Pa): 20
処理時間(sec): 20
絶縁樹脂膜2の下面をプラズマ処理することにより、半導体チップ1との接触部分の密着性が向上するため、半導体チップ1と絶縁樹脂膜2との接合信頼性をさらに向上させることができる。
(第2実施形態)
図4は、本発明の第2実施形態における半導体集積回路装置を示す断面図である。第1実施形態と異なる箇所は、導電層3を、半導体チップ1の外側の絶縁樹脂膜2部分(半導体チップ1の外側の絶縁樹脂膜2部分)にも形成していることである。
2 絶縁樹脂膜(第1の絶縁樹脂層)
3,3a 導電層
4,4a 半田ボール(電極)
5 回路基板(プリント配線基板)
6 絶縁樹脂層(第2の絶縁樹脂層)
60a 半導体装置
100a 回路装置
Claims (4)
- 第1の絶縁樹脂層と、
前記第1の絶縁樹脂層の一方の面に設けられた半導体チップと、
前記第1の絶縁樹脂層の他方の面に設けられた導電層と、
前記導電層と回路基板を接続するとともに、前記導電層を介して前記半導体チップと電気的に接続する電極と、
前記導電層と前記回路基板との間に、前記電極を埋め込むように設けられた第2の絶縁樹脂層と、
を備え、
前記半導体チップの側面が、前記第1の絶縁樹脂層で覆われているとともに、前記回路基板の側の前記半導体チップの主面より前記回路基板の側の領域において、前記第2の絶縁樹脂層が、前記第1の絶縁樹脂層の側壁の底面側の一部を覆うことを特徴とした回路装置。 - 前記導電層は、前記半導体チップの外側の前記第1の絶縁樹脂層部分にも設けられていることを特徴とした請求項1に記載の回路装置。
- 前記第1の絶縁樹脂層の一方の面がプラズマ処理面であることを特徴とする請求項1または2に記載の回路装置。
- 前記第1の絶縁樹脂層が、フィラーを含むことを特徴とした請求項1〜3のいずれか一項に記載の回路装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004370774A JP4880218B2 (ja) | 2004-12-22 | 2004-12-22 | 回路装置 |
US11/313,743 US8093699B2 (en) | 2004-12-22 | 2005-12-22 | Circuit device with circuit board and semiconductor chip mounted thereon |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2004370774A JP4880218B2 (ja) | 2004-12-22 | 2004-12-22 | 回路装置 |
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JP2006179652A JP2006179652A (ja) | 2006-07-06 |
JP4880218B2 true JP4880218B2 (ja) | 2012-02-22 |
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JP2004370774A Expired - Fee Related JP4880218B2 (ja) | 2004-12-22 | 2004-12-22 | 回路装置 |
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