TW201521160A - 封裝表面具接合元件的微電子元件 - Google Patents

封裝表面具接合元件的微電子元件 Download PDF

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Publication number
TW201521160A
TW201521160A TW103131875A TW103131875A TW201521160A TW 201521160 A TW201521160 A TW 201521160A TW 103131875 A TW103131875 A TW 103131875A TW 103131875 A TW103131875 A TW 103131875A TW 201521160 A TW201521160 A TW 201521160A
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Taiwan
Prior art keywords
semiconductor die
portions
bonding wires
flexible material
layer
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TW103131875A
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English (en)
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TWI540693B (zh
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Belgacem Haba
Richard Dewitt Crisp
Wael Zohni
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Invensas Corp
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Publication of TWI540693B publication Critical patent/TWI540693B/zh

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Abstract

本發明係揭露一種微電子結構，其包含在第一表面具有導電元件的半導體晶粒；複數條焊線，其具有接合到導電元件的複數個底座、以及遠離底座的複數個自由端，自由端係遠離基板以及底座並有端表面，且複數條焊線係定義在底座以及端表面之間的邊緣表面；一柔性材料層，沿著複數條焊線之至少鄰近底座的邊緣表面延伸，並填充於複數條焊線之複數個第一部分之間的空間，使得複數條焊線之複數個第一部分係藉由柔性材料層而彼此相分離。複數條焊線之第二部分係由端表面以及邊緣表面之鄰近端表面的部分所定義，該部分係從柔性材料層之第三表面延伸出。

Description

封裝表面具接合元件的微電子元件
本申請案之主題係有關於含有半導體晶片的一微電子元件，其具有與外部微電子器件組裝時能有改良的可靠性的結構，此微電子元件係含有相容的連接結構，以及有關於製造此微電子元件的方法。
微電子晶片係平坦本體，其前表面上設置有接觸件以連接至晶片之內部電路。晶片係通常封裝以形成具有能電性連接至晶片接觸件之端子的微電子封裝然後，封裝件的端子可連接至外部微電子器件，例如電路面板。
微電子裝置，例如微電子晶片，係通常需要許多輸入以及輸出連接部，以連接其他電子元件。半導體晶片或是其他相似的元件之輸入以及輸出接觸件係通常設置成網格狀圖樣，其實質上覆蓋該元件之表面(通常被稱為面陣列)；或是呈複數長條列，其平行於且鄰近元件的前表面之每一邊緣或是該前表面之中心而延伸。通常，此種裝置(例如晶片)必須實 體地設置在基板(例如印刷電路板)上，而元件之接觸件必須電性連接至電路板之導電零件。
微電子晶片係一般提供在封裝件中裡，以利於在晶片製造 期間的處理以及在將晶片安裝在外部基板(例如電路板或是其他電路面板)上之期間的處理。例如，許多微電子晶片係提供在封裝件裡以適合表面安裝(surface mounting)。此一般類型之多種封裝件已經使用於各種應用。最常見的，此種封裝件係包含一介電元件，一般稱為"晶片載體"，其在具有介電質上鍍或是蝕刻出金屬結構以形成的端子。這些端子通常係藉由零件連接至晶片本身之接觸件，例如沿著晶片載體延伸的薄導線；或是藉由晶片之接觸件以及端子或是導線之間延伸的細引線或是線路連接至晶片本身之接觸件。在表面安裝操作中，封裝件係放置到電路板上使得封裝件上的每一個端子係對準電路板上的對應接觸墊。在端子以及接觸墊之間係提供焊料或是其他接合材料。藉由加熱組件熔化或是"回焊"焊料或是其他方式活化接合材料，可使此封裝件永久地接合。
許多封裝件包含焊球形式的焊料塊而附著至封裝件之端子， 通常焊球的直徑是約0.1毫米到約0.8毫米之間(5至30mils之間)。封裝件之底表面有突出的焊球陣列的一般稱為球柵陣列或是"BGA"封裝技術。其他封裝技術，被稱為平面柵陣列或是"LGA"封裝技術，係藉由焊料形成的薄層或是平面以牢固基板。此類型的封裝件可以非常薄。特定的封裝技術，一般被稱為"晶片級封裝(chip scale package)"，其佔據電路板之區域等於或是僅略大於在封裝件中的元件區域。此優點在於其降低組件的總尺寸且基板上的各種裝置之間允許使用短的互連線路，其係限制裝置之間的訊號傳 遞時間，如此有利於組件在高速下操作。
在此封裝件中，複數個元件之熱膨脹("CTE")係數的不匹配或是差異對可靠性以及效能有不利的影響。舉例而言，半導體晶片比起其設置的基板或是印刷電路板有更低的CTE。當晶片在其使用期間加熱以及冷卻時，複數個元件將會根據其不同的CTE而有膨脹或收縮。在此範例中，基板比半導體晶粒有較多的膨脹且膨脹速率也較快。此可能造成用於安裝且電性連接半導體晶粒以及基板的焊料塊(或是其他結構)的應力。此種應力會造成焊料塊從半導體晶粒或是基板兩者或其中一者斷裂，從而中斷其原本有利的訊號傳輸。針對CTE變化，已經有使用各種結構來補償，然而對於逐漸增加利用於微電子封裝的微細間距陣列，目前並無法提供適當足夠的補償。
本發明的一態樣係有關於一微電子結構，其包含第一半導體晶粒，其具有第一表面、與第一表面相背對的第二表面、以及在第一表面上的複數個導電元件。該結構亦包含複數條焊線，其具有複數個底座分別接合到複數個導電元件。複數條焊線更具有遠離複數個底座的複數個自由端，自由端係遠離基板以及底座，並在其上有端表面。複數條焊線係定義在底座以及端表面之間延伸的邊緣表面。一柔性材料層係位於複數條焊線之底座之外部的半導體晶粒之第一表面上且從其延伸出。柔性材料層更沿著複數條焊線之邊緣表面之至少鄰近底座的第一部分延伸，並填充於複數條焊線之第一部分之間的空間，使得複數條焊線之複數個第一部分係藉 由柔性材料層而彼此相分離。柔性材料層更具有一第三表面，其係背對半導體晶粒之第一表面。複數條焊線之第二部分係由端表面以及鄰近端表面且未被第三表面覆蓋而延伸遠離之部分所定義。
複數條焊線之第一部分可被柔性材料完全地封裝。進一步 地，複數條焊線之第二部分可相對於底座而移動。在一範例中，柔性材料層具有2.5G Pa或是更小的楊氏模數。
複數條焊線之第二部分係沿著複數條焊線之軸線延伸，其 設置係相對於第三表面呈至少30度角。複數條焊線之端表面可高於第三表面50μm之距離。進一步地，複數條焊線之端表面可高於第三表面50μm之距離。
半導體晶粒係進一步定義在第一表面以及第二表面之間延 伸的邊緣表面，而柔性材料層係進一步包含從第三表面延伸至半導體晶粒之第一表面的邊緣表面，藉此以與半導體晶粒之邊緣表面實質上共平面。 複數條焊線中的至少一個之形狀係使得焊線定義自由端以及底座之間的軸線，並使得此焊線定義一平面。在此範例中，至少一焊線之彎曲部係在此平面內遠離軸線而延伸。至少一焊線之形狀係進一步使得該焊線之實質上直線部沿著軸線在自由端以及彎曲部之間延伸。
微電子結構係進一步包含導電金屬塊，其接合複數條焊線 之第二部分並接觸柔性材料層之第三表面。在此範例中，導電金屬塊中的至少一個係分別封裝複數條焊線中的其中一個之至少一些第二部分。導電金屬塊可藉由回焊將複數條焊線之第二部分與外部導電零件相接合。
在範例中，半導體晶粒可為具有第一區以及環繞第一區之 第二區的第一半導體晶粒。第一半導體晶粒之導電元件可在第二區內。在此範例中，微電子結構進一步可包含第二半導體晶粒，其設置在第一區內的第一半導體晶粒上。第二半導體晶粒可電性連接第一半導體晶粒之至少一些導電元件。柔性材料層可覆蓋第二半導體晶粒。
在另一範例中，半導體晶粒可為具有第一區以及環繞第一區之第二區的第一半導體晶粒。第一半導體晶粒之導電元件可在第二區內。此微電子結構進一步可包含第二半導體晶粒，其設置在第一區內的第一半導體晶粒上。第二半導體晶粒可具有第一表面以及背對第一表面的第二表面，以及在背對第一半導體晶粒之第一表面的第一表面上的複數個導電元件。額外的複數條焊線可具有分別接合第二半導體晶粒之其中一導電元件的複數個底座。複數條額外焊線可進一步具有遠離複數個底座的複數個自由端，自由端可遠離第二半導體晶粒之第一表面以及底座，並在其上有複數個端表面。複數條焊線可定義在底座以及端表面之間延伸的邊緣表面。柔性材料層可進一步位在複數條額外焊線之底座之外部的第二半導體晶粒之第一表面上並從其延伸出，且柔性材料層可進一步沿著複數條額外焊線之邊緣表面之第一部分延伸。複數條額外焊線之第二部分可由端表面以及從端表面延伸出的邊緣表面之部分所定義，該部分係未被在第三表面上的柔性材料層所覆蓋且延伸遠離第三表面上的柔性材料層。
本發明的另一態樣係有關於微電子封裝件，其包括具有第一半導體晶粒的微電子元件，此第一半導體晶粒具有第一表面背對第一表面的第二表面、以及在第一表面上的複數個導電元件。該元件可進一步具有複數條焊線，其具有分別接合在第一表面上的導電元件中的其中一個的 底座、以及複數個端表面，端表面係遠離基板以及底座。每一焊線係從底座延伸至端表面。柔性材料層係位於基板之第一表面之的第一部分上並從其延伸出，並填充於複數條焊線之複數個第一部分之間的空間，使得複數條焊線之複數個第一部分係藉由此柔性材料層而彼此相分離。柔性材料層具有背對基板之第一表面的第三表面，而複數條焊線之第二部分係由複數條焊線之端表面上未被第三表面上的柔性材料層覆蓋的至少一部分所定義。 封裝件進一步包含一基板，其具有第四表面以及在第四表面上暴露的複數個端子。微電子元件係安裝於具有第三表面之基板上，第三表面係面向第四表面，至少一些焊線之第二部分係分別與複數個端子中的其中一個相接合。
複數條焊線之第二部分可藉由導電金屬塊電性地以及機械 性地與複數個端子相接合。微電子封裝件可進一步包含一成型介電層，其形成在基板之第四表面之至少一部分上並從其延伸出，藉此沿著微電子元件之至少一部分延伸。成型介電層之楊氏模數可大於柔性材料層之楊氏模數。柔性材料層可具有低於2.5G Pa的楊氏模數。
複數條焊線可進一步定義在底座以及端表面延伸的邊緣表 面，而柔性材料層可沿著複數條焊線之至少鄰近底座之邊緣表面之部分且在複數條焊線之第一部分內延伸。從端表面延伸出的複數條焊線之邊緣表面之部分在第三表面上可不被柔性材料層之全部周長覆蓋。
本發明的另一態樣係有關於製造微電子結構的方法。本方 法包含在半導體晶粒上形成複數條焊線，此半導體晶粒係具有第一表面以及背對第一表面的第二表面、以及在第一表面上的複數個導電元件。複數 條焊線係形成具有複數個底座以及複數個端表面，複數個底座係分別接合到導電元件，端表面係遠離基板以及底座。複數條焊線之邊緣表面係在底座以及端表面之間延伸。本方法進一步包含形成一柔性材料層，其覆蓋複數條焊線之底座之外部的半導體晶粒之第一表面上且從其延伸出。柔性材料層係進一步形成沿著複數條焊線之第一部分之部分邊緣表面延伸，並填充於複數條焊線之第一部分之間的空間，以將複數條焊線之複數個第一部分彼此相分離。柔性材料層係進一步形成有背對上述基板之第一表面的第三表面，而複數條焊線之第二部分係至少由複數個端表面以及複數條焊線之邊緣表面上未被第三表面上的導電材料層覆蓋的一部分所定義。
本方法可進一步包含將在基板上安裝上述微電子封裝件， 其第三表面係面向基板之表面。基板之表面可具有複數個端子，而上述的安裝可包含將複數條焊線之第二部分之至少一些與複數個端子相接合。複數條焊線之第二部分可與此些端子相接合，此些端子含有與複數條焊線之第二部分接合之導電金屬塊的回焊。至少回焊之後，導電金屬塊中的至少一個可分別封裝複數條焊線之至少一些第二部分。在另一範例，複數條焊線之第二部分可與此些端子接合，此些端子含有與端子接合的導電金屬塊之回焊。
本方法可進一步包含在基板之表面之一部分上方形成一成 型電介質並從此位置延伸出，藉此沿著柔性材料層之至少一部分以及沿著半導體晶粒之至少一部分延伸。
柔性材料層可沉積在半導體晶粒上，藉此覆蓋複數條焊線(包含其端表面)，以及形成柔性材料層之步驟可進一步包含移除柔性材料層 之一部分以形成第三表面，且藉此不覆蓋複數條焊線之第二部分。或者，形成柔性材料層之步驟可包含將柔性材料在半導體晶粒上成型，藉此形式第三表面使得複數條焊線之第二部分從此延伸。
形成此焊線可包含使用接合工具之細管將線路段壓至接觸 副表面，以切斷與複數個導電元件中的其中一個接合的線路段，藉此形式遠離底座的焊線之端表面。
10‧‧‧微電子結構
10'‧‧‧微電子結構
10"‧‧‧微電子結構
12‧‧‧半導體晶粒
14‧‧‧第一表面
16‧‧‧第二表面
23‧‧‧邊緣表面
24‧‧‧組件
28‧‧‧導電元件
30‧‧‧接觸部
32‧‧‧焊線
34‧‧‧底座
35‧‧‧底座端
36‧‧‧自由端
37‧‧‧邊緣表面
38‧‧‧端表面
40‧‧‧延伸部
42‧‧‧柔性材料層
44‧‧‧主表面
45‧‧‧表面
46‧‧‧基板
50‧‧‧軸線
52‧‧‧第一部分
54‧‧‧第二部分
56‧‧‧頂點
58‧‧‧角度
60‧‧‧軸線
62‧‧‧尖端
64‧‧‧電路
66‧‧‧焊料塊
68‧‧‧介電層
70‧‧‧細管
74‧‧‧線路
76‧‧‧面
78‧‧‧區域
80‧‧‧區域
90‧‧‧PCB(印刷電路板)
92‧‧‧接觸墊
110‧‧‧微電子元件
112‧‧‧半導體晶粒
114‧‧‧第一表面
118‧‧‧第一區
120‧‧‧第二區
122‧‧‧半導體晶粒
128‧‧‧導電元件
132‧‧‧焊線
140‧‧‧延伸部
142‧‧‧柔性層
144‧‧‧第三表面
210‧‧‧微電子元件
212‧‧‧半導體晶粒
214‧‧‧表面
218‧‧‧第一區
220‧‧‧第二區
222‧‧‧半導體晶粒
228‧‧‧導電元件
232a‧‧‧焊線
232b‧‧‧焊線
240‧‧‧延伸部
242‧‧‧柔性材料層
本發明之上述及其他特徵及優勢將藉由參照附圖詳細說明其例示性實施例而變得更顯而易知，其中：第1圖為本發明之一態樣的微電子元件之剖面圖。
第2圖為含有第1圖之微電子元件的微電子封裝件之剖面圖。
第3A至3C圖為複數條焊線之範例之示意圖，此焊線可使用於第1圖之微電子元件。
第4圖為第3A至3C圖之焊線範例之尖端之細部圖。
第5圖為本發明之另一範例之另一微電子元件之剖面圖。
第6圖為本發明之另一範例之另一微電子元件之剖面圖。
第7至12圖為本發明的另一態樣之製造微電子元件的方法之步驟期間處理單元的各種剖面圖。
第13圖為可用在第7至12圖所示的本方法之變化型的一方法步驟。
第14圖以及第15圖為用於製造焊線的方法的連續步驟之示意圖，此 種焊線可與第7至12圖所示之方法以及第13圖之步驟變化型相結合。
於此使用，詞彙“與/或”包含一或多個相關條列項目之任何或所有組合。當“至少其一”之敘述前綴於一元件清單前時，係修飾整個清單元件而非修飾清單中之個別元件。
在圖式中，相似參考標號係用於指示相似元件，第1圖為本發明實施例之微電子元件之形式的微電子結構10。第1圖之實施例係微電子元件，其為半導體晶粒12之形式(亦稱為半導體晶片)。微電子元件具有複數條焊線32從接觸件28延伸至延伸部40，延伸部40係在覆蓋且讓複數條焊線32之剩餘部分彼此相分離的柔性材料層42上延伸。焊線32有一部分係鄰近半導體晶粒12。然後，結構10可使用於電腦或是其他電子應用裝置，可單獨使用或與其他元件組合使用。
第1圖之微電子元件10包含具有第一表面14以及第二表面16的半導體晶粒12。針對本案之目的，所述第一表面14可相對或是遠離第二表面16。此種描述中，與本文中所使用的其他元件之相對位置之描述相同，指示元件之垂直或是水平位置係僅為說明性目的，以對應圖式內元件之位置，但非為限制之目的。
在半導體晶粒12之第一表面14上有導電元件28。就本案描述而言，當描述導電元件在具有介電結構的另一元件之表面上時，其係指電性導電結構係用於接觸在一垂直於介電結構之表面方向上移動的理論點，且從介電結構外部朝向介電結構表面移動。如此，介電結構之表面上 的一端子或其他導電結構可從此表面突出；或者，可與此表面齊平；或者，可相對於此表面內凹並由介電結構的孔洞或凹槽所暴露。導電元件28可為固體金屬材料之平坦、薄的元件，固體金屬材料可為銅、金、鎳、或是其他可用於此應用得材料，例如含有銅、金、鎳或是其組合中的至少一種的各種合金。在一範例中，導電元件28可為實質上圓形。
微電子元件10進一步包含接合到至少一些導電元件28的 複數條焊線32。複數條焊線32係在底座34與導電元件28相接合，並延伸至對應的自由端36，此自由端36係遠離底座34以及半導體晶粒12之第一表面14。複數個自由端36係位在複數條焊線32之延伸部40內。複數條焊線32之複數端36之特徵在於其自由性，不連接或是不接合到半導體晶粒12或是任何其他在微電子元件10內連接至半導體晶粒12的導電零件。換句話說，自由端36可透過焊球或是其他在此討論的零件直接或是間接地電性連接微電子元件10外部的器件之導電元件，例如印刷電路板(PCB)或是具有導電接觸件或是端子的另一基板。事實上，複數自由端36係由柔性材料層42(以下將描述)保持在預設中性位置；而接合或電性連接至另一外部器件的複數自由端36並非意謂其不是"自由的"。相反地，當底座34係直接或是間接電性連接至半導體晶粒12，其並非自由的，如上所述。如第1圖所示，底座34可實質上呈圓形，從底座34以及自由端36之間定義的焊線32之邊緣表面37向外延伸(如第3A至3C圖所示)。
根據用以形成焊線32之材料類型、焊線32以及導電元件 28之間的連接所需的強度、或是用以形成焊線32的特别製程，底座34之特定尺寸以及形狀可有所變化。在Otremba的美國專利7,391,121號以及美 國專利公開號2012/0280386(簡稱386公開案)以及2005/0095835(簡稱835公開案，其描述被認為是線路接合之形式的楔形接合步驟)，其揭露全部係納入此處作為製造複數條焊線32的範例方法之參考。
複數條焊線32可用導電材料製成，例如銅、金、鎳、焊料、 鋁或其他相似材料。另外，複數條焊線32可組合材料製成，例如，導電材料(例如銅或是鋁)之線心結合在線心外的塗層。塗層可為第二導電材料，例如鋁、鎳或其他相似材料。或者，塗層可為絕緣材料，例如絕緣套。在一範例中，用以形成複數條焊線32的線路可具有約15μm至150μm之間的厚度，即橫跨線路長度的維度上。在其他範例，係包含使用楔形接合，而複數條焊線32可具有約500μm的厚度。一般而言，焊線係形成導電元件上，例如使用專門設備在接觸部30內形成的導電元件28。
如下所述，在形成上述類型之焊線的期間，一線路段之前 端係加熱以及緊壓與線路段接合的接收面，通常形成球狀或是類球狀底座34以接合到導電元件28之表面。形成焊線的線路部分之所需長度係從接合工具拉出，然後切割所需長度的焊線。例如，楔形焊接，其可用於形成鋁製的複數條焊線，係為將線路之加熱部分拖拉橫過接收面以形成通常平行於該表面的楔形。如果需要，楔形接合焊線可向上彎曲，以及延伸至切割之前的所需長度或是位置。在一特定實施例，用於形成焊線的線路在橫跨部分可為圓筒狀。否則，從工具輸入用以形成焊線的線路或是楔形接合焊線的線路可具有多邊形橫跨部分，例如矩形或是梯形。
複數條焊線32之延伸部40可形成陣列連接零件之至少一 部分，此陣列係由複數條焊線32之個別延伸部40所形成。此種陣列可形 成在面陣列構造中，其變化型可用上述結構來實現。此種陣列可用於電性地以及機械性地連接微電子元件10至另一微電子結構，例如連接至印刷電路板("PCB")、基板(在微電子元件10之封裝構造中，其範例係顯示在第2圖中)或是其他外部器件或是結構。複數個焊料塊66(如第2圖所示)可藉由電性以及機械性地附著延伸部40，以連接複數條焊線32至此種器件或是結構的複數個導電零件。另外，焊料塊66包含自由端36以及對應的端表面38(如第3A至3C圖所示)。
微電子元件10進一步包含一柔性材料層42，其係以具有低 於約2.5GPa之楊氏模數的介電材料所形成。如第1圖所示，柔性材料層42在半導體晶粒12之第一表面14之部分上方延伸，該部分未被複數條焊線32之底座34所覆蓋或是占用。同樣地，柔性材料層42係在導電元件28之部分上方延伸，該部分不被複數條焊線32之底座34所覆蓋。柔性材料層42亦可部分地覆蓋複數條焊線32，包含底座34以及複數個邊緣表面37之至少一部分。如上所述，複數條焊線32之延伸部40係維持不被柔性材料層42覆蓋，從而製造可用於電性連接至柔性材料層42外部的零件或是元件的複數條焊線32。在圖式顯示的範例中，一表面，例如柔性材料層42之主表面44可與半導體12之第一表面14相分隔足够覆蓋底座34以及複數條焊線32之邊緣表面37之部分的距離，藉此提供機械支撐的平坦水平並使複數條焊線32彼此相分離以及電性絕緣。針對柔性材料層42的其他配置係可能的。例如，柔性材料層可具有多個變化高度的表面。
在第1圖顯示的焊線32範例，其在第3A以及4圖更詳細 地顯示，係定義特别的彎曲形狀，其藉由利用一副表面製造複數條焊線32 之製程而設置在複數條焊線32上。以下，此方法係進一步參考第7至13圖進行說明。複數條焊線32之形狀可使得複數個端表面38沿著軸線50對準焊線32之鄰近底座34的底座端。第3A圖所顯示的焊線32之範例中，軸線係通常垂直導電元件28使得端表面38之位置係直接高於底座端35。 一此種構造係有用於形成陣列的複數條焊線32，其中連接在柔性材料層42之主表面44上的陣列係旨在具有一間距，與複數條焊線32分别相接合的導電元件28之間距相匹配。在此種構造中，軸線50亦可與接觸部30呈一角度，使得端表面38從底座端35略偏移但是仍然高於底座34。在此範例中，軸線50可與接觸部30呈85°至90°角度。
可配置焊線32使得端表面38上的第一部分52可通常沿著 軸線50之一部分延伸。第一部分52的長度係介於焊線32之總長度(例如，以軸線50長度來定義)之約10%至50%之間。焊線32之第二部分54可彎曲或是折彎，藉此從鄰近第一部分52之位置延伸至與軸線50相分隔的頂點56以遠離軸線。第二部分54係進一步彎曲藉此沿著軸線50位於或是靠近底座端35，亦從底座端35側延伸至頂點56以遠離軸線50。應注意的是，第一部分52不需要是直線或是精確地接續軸線50，其可以有一些曲率或變化。應注意的是，彎曲的第一部分52以及第二部分54之間可有突然或是平滑的彎曲變化。然而，應注意的是第1以及3A圖的複數條焊線32，包含第二部分54位於軸線50所在的單一平面。
進一步，可配置焊線32之第一部分52以及第二部分54使 得未與軸線50相交的任何部分皆在軸線50之單側上。亦即，例如，一些第一部分52以及第二部分54可在軸線50之一側，其係相對於第二部分54 所定義的彎曲形狀之頂點56；然而，此部分的任何一部分將在焊線32之與軸線50至少部分地相交叉的區域中。換句話說，焊線32之第一部分52以及第二部分54可不完全地與軸線50交叉使得那些部分內的邊緣表面37係僅與軸線50之單側上的軸線50相分隔。在第3A圖之範例中，平面係沿著繪製焊線32的頁面上呈現。
第3B以及3C圖係顯示具有複數端36的複數條焊線32之 範例，其未直接高於底座34。亦即，考量到半導體晶粒12之第一表面14延伸在兩個側面方向，藉此實質上定義複數條焊線32中的其中一個之平面，而複數條焊線32中的其中一個的端36可從底座34之對應的側面位置在這些側面方向中的至少一個位移。如第3B以及3C圖所示，複數條焊線32可為相同的一般形狀，例如第3A圖之焊線，也可以具有一端36，其對準焊線32鄰近底座34以定義軸線50的部分。同樣地，複數條焊線32可包含第一部分52以及第二部分54，第一部分52通常沿著軸線50延伸，而第二部分54係彎曲藉此定義在單側上與軸線50相分隔的頂點56，以定義沿著軸線50延伸的平面。然而，第3B以及3C圖的複數條焊線32可配置使得如上所述定義的軸線50與接觸部30呈一角度，例如低於85°。在另一範例中，角度58可約30°至75°之間。
焊線32可使得焊線之第二部分54內定義的頂點56在角度 58外，如第3B圖所示，或是在角度58內，如第3C圖所示。進一步，軸線50可與接觸部30呈一角度，使得焊線32之端表面38相對於接觸部30在多個側面方向上橫向地位移。在此範例中，由第二部分54以及軸線50定義的平面本身與導電元件28及/或第一表面14呈一角度。此角度可實質 上等於或是不同角度58。亦即，端36相對於底座34的位移可在兩個側面方向上，在每一方向上可有相同或是不同的位移距離。
在一範例中，微電子元件10中，各種焊線32可在不同方 向上位移以及有不同位移量。此種配置係讓微電子元件10具有一陣列的延伸部40，相比於半導體晶粒12之第一表面14之水平，此陣列的延伸部40係不同地配置在表面44之水平上。例如，比起半導體晶粒12之第一表面14，陣列可覆蓋較小的整體區域或是在表面44上有較小間距。在第1圖之微電子元件10之變化中，複數條焊線32可如第3B圖、第3C圖或兩者之結合所示呈一角度。
如第4圖所示，至少一些焊線之之自由端36可具有不對稱 構造的端表面38，其定義為複數條焊線32之在至少一方向上比鄰近部分窄的尖端62。自由端36之窄尖端62可藉由以下說明的製程以設置在焊線32上。如圖所示，窄尖端62可偏移使得穿過中心的軸線60從軸線62穿過焊線32之鄰近部分之中心而偏移。進一步，端表面38之質心64可沿著軸線60而從鄰近焊線部分偏移。焊線32之尖端62亦可在垂直第11圖所示的維度方向上變窄；或是與焊線32之鄰近相同寬度或是較廣。複數條焊線32之延伸部40可包含具有尖端的焊線之所有的或是部分的尖端62，或是可包含全部尖端62以及延伸超過尖端62的複數條焊線之部分。
如上所述，複數條焊線32可用於連接微電子元件10至一 外部器件。第2圖係顯示微電子元件10之組件24之範例，其可如第1圖所描述，或是可如第1圖所描述的變化型。複數條焊線32之延伸部40係與藉由焊料塊66與基板46之複數個接觸墊48相接合，焊料塊66係沿著 複數條焊線32之延伸部40以及沿著接觸墊48延伸。基板46可為實質上平坦介電元件的形式。介電元件可為片狀，而且可為薄的。在特定實施例中，介電元件可包含至少一層有機介電材料或是複合介電材料，舉例但非未限制，聚酰亞胺(polyimide)、聚四氟乙烯(PTFE)、環氧樹脂、環氧樹脂、玻璃、玻璃纖維板(FR-4)、BT樹脂、熱塑性或是熱固性塑膠材料。 基板46之厚度較佳地在所需應用可接受的厚度範圍內，例如，約25μm至500μm之間。基板46可進一步包含相對於接觸墊48的端子49，其係在相同或是不同的陣列配置。端子49可藉由基板46內的路由電路64連接接觸墊48。
組件24可進一步包含一成型介電層68，其可成型在基板 46面向微電子元件10之表面上。成型介電層68係為一密封劑，例如，可填充在複數個焊料塊66之間的空間中，並可接觸在基板46以及柔性材料層42之第三表面44之間的區域。成型介電層68可進一步分别沿著基板46向外延伸以及沿著邊緣柔性材料層42與半導體晶粒12之表面45與23向上延伸，在半導體晶粒12之第二表面16上的延伸可選擇地覆蓋微電子元件10。基板46可包含相對於接觸墊48的封裝端子或是其他結構，以利於將封裝組件24與外部器件的連接。
在另一範例，同樣地，微電子元件可在基板46直接接合印 刷電路板("PCB")。此種PCB可組裝在電子裝置內使得微電子元件10與PCB之連接可由將微電子元件10組裝此種元件來完成。進一步，可不須結合成型介電材料來執行此種組裝。
在上述微電子元件10之任一組件或是應用中，根據上述原 理複數條焊線32之結構結合柔性材料層42，可協助改進微電子元件10在封裝組件與基板或與PCB(或是其他器件)附著的可靠性。特別的是，微電子元件10在複數條焊線32之延伸部40以及連接器件(例如接觸墊48)之對應的導電零件之間連接之情形中，連接之可靠性可以比半導體晶粒之接觸件與基板之端子之間直接連接更改善。此改善係透過複數條焊線32彎曲或是折彎以容置半導體晶粒12之導電元件28以及基板46(或是PCB或是其他相似結構)之接觸墊48之間的相對移動，來完成。此移動可能是器件操作、元件移動(，例如，微電子元件10或是組件被使用)、或是微電子元件10或是組件24進行測試所造成。進一步，此種相對移動可能是由器件在使用期間因器件及/或周圍結構產生的熱造成的擴張以及對應的收縮造成的。此種熱膨脹係有關於器件之熱膨脹係數(CTE)，而不同結構中複數個器件之間的相對移動可能因為各種結構或是材料之CTE差異或是不匹配所造成。例如，半導體晶粒可具有約2至5之間的CTE(ppm/℃)。在相同組件中，PCB或是基板可具有15(ppm/℃)或更大的CTE。
任一器件之CTE可為一"複合"CTE，其係指完成結構之CTE， 可近似但不精確地匹配建構此結構的主要材料之CTE，且可取決於結構之架構以及具有不同CTEs的其他材料。例如，半導體晶粒之CTE可大約為建構晶粒的矽或是另一半導體材料。在另一範例，基板46的CTE大約是建構基板46的聚四氟乙烯或是另一介電材料。
因此，當半導體晶粒12以及基板46在組件24之熱循環期 間膨脹以及收縮，因為半導體晶粒12以及基板46對於相同溫度改變下以不同速率以及不同程度膨脹，所以材料之間的CTE可造成半導體晶粒12 之導電元件28以及基板46(或是另一結構，例如PCB或其他相似)之接觸墊48之間的移動。依照器件及/或導電元件28以及接觸墊46之特别配置，此造成接觸墊48相對於導電元件28的位移，特別在基板46、或是半導體晶粒12(即朝向邊緣表面23)或是在其他區域之外圍區。
沿著個別長度的複數條焊線32之可撓性可讓端表面38能 有彈性地相對於底座34移動。此種可撓性可補償複數條焊線32所連接的相關聯導電元件28以及接觸墊46之間的相對移動。然而，因為複數條焊線32係可撓式，所以比起基板46或是其他結構，焊線32無法可靠地支撐半導體晶粒12。例如，未被支撐的複數條焊線32之收縮會導致鄰近的複數條焊線32彼此接觸，造成短路或是其他焊線32或是相關聯器件的損壞。 因此，柔性材料層42係讓複數條焊線32彼此相分離，並沿著其高度增加結構的剛性，並允許複數條焊線32所需的收縮以補償接觸墊46相對於導電元件28的位移。因此，柔性材料層42可用有彈性地可變形(即柔性材料)組成物製成，例如具有低於2.5GPa楊氏模數的材料。進一步，如上所述，柔性材料層42可為介電質，藉此不需要額外的塗層便可將複數條焊線32彼此電性絕緣。適合作為柔性材料層的材料包含矽樹脂、苯並環丁烯(BCB)、環氧樹脂或其他相似材料。
在此結構中，其有利於配置微電子元件10與與基板12的 連接，且此連接係足够堅固以補償柔性層42內複數條焊線32之收縮(其需要柔性層42之變形)。複數條焊線132之延伸部40可達成此種連接。例如，不被柔性材料層42覆蓋藉此以實體分隔，延伸部40係讓導電金屬塊66完全地環繞延伸部40內的複數條焊線32之至少一些邊緣表面37，其可 提供更堅固的連接，比起導電金屬塊66簡單地沿著側邊延伸所達到的連接。為了充分將導電金屬塊66環繞延伸部40，延伸部40可相對柔性材料層42定位使得延伸部40內的複數條焊線32之軸線50係與表面44呈30°至90°之間的角度。藉由將複數條焊線32以及柔性材料層42結構化使得延伸部比表面44高200μm或是更少，可進一步提升接合之強度。例如，延伸部40可具有50μm至200μm之間的高度。
在組件24以及微電子元件10亦包含成型電介質的一些範例中，成型電介質本身可為柔性，具有大於柔性材料層42的楊氏模數，以及在其他範例中可低於半導體晶粒12或是基板46。
第5以及6圖係顯示結合堆疊配置的多個半導體晶粒的微電子元件110以及210之範例。在第5圖之範例中，半導體晶粒112之第一表面114係考慮劃分成第一區118以及第二區120。第一區118係在第二區120內，且包含第一表面114之中央部分以及由此向外延伸。第二區120係實質上環繞第一區118且由此向外延伸至半導體晶粒112之外部邊緣。在此範例中，半導體晶粒112沒有特定特性係實體分離此兩個區域；然而，基於處理或是特徵應用而在此討論之目的，此些區域未標示出。複數條焊線132係連接第二區120內表面114上的導電元件128。
第二半導體晶粒122係設置在第一區118內半導體晶粒112上。在第5圖所示範例中，半導體晶粒122係設置在半導體晶粒112面向下並以導電金屬塊66(例如焊料塊)電性地以及機械性地相接合。在此種結構中，半導體晶粒122表面上的導電元件(其面向第一表面114)可在第一區118內延伸的半導體晶粒112之表面114上與路由電路連接。例如，此種路 由電路可包含導線，其延伸至第二區120且與第二區120內表面114上的一些導電元件128相連接。其他導電元件128係連接至半導體晶粒112之內部器件。因此，複數條焊線132可利於半導體晶粒112與在柔性材料層142之第三表面144上的半導體晶粒122之間的連接。為了達成此種結構，針對待設置高於半導體晶粒122且可被柔性層142覆蓋的複數條焊線132之延伸部140，兩複數條焊線132以及柔性層142可具有充分的高度。對於上述柔性層142內的複數條焊線132可補償器件之間CTE不匹配的微電子元件110，可設置在基板、PCB或是與其他結構上。
在第6圖之範例中，第二半導體晶粒222係設置在第一區 218內的半導體晶粒212。半導體晶粒具有設置在第二區內的導電元件228a，第二區220係環繞有複數條焊線232a與之連接的半導體晶粒222。然而，在此範例中，半導體晶粒222係設置在半導體晶粒212上且面向上，使得其導電元件228b面向遠離半導體晶粒212之表面214。在此結構中，複數條第二焊線232b係連接導電元件228b並遠離導電元件228b而延伸至複數端238。柔性材料層242係覆蓋在複數條焊線232a之外部區域以及半導體晶粒222之外部區域中的半導體晶粒212之表面214。柔性材料層進一步覆蓋半導體晶粒222使得柔性材料層242能分離複數條焊線232a以及232b之複數個邊緣表面237並延伸於複數個邊緣表面237之間。因此，藉由連接複數條焊線232a以及232b之延伸部240以及與以上描述之微電子元件10相似結構的零件，微電子元件210可設置在基板、PCB或是其他結構上。
在此種結構中，複數條焊線232a以及232b係配置在所需充分的高度，以補償如上所述器件之間CTE不匹配。在此結構中，複數條 焊線232a以及232b係配置在所需充分的高度，以針對延伸部240提供所需的高度，並充分補償相連接的零件由於CTE不匹配而產生的位移。例如，因為此種結構在周邊的位移越大，所以在基板上的接觸墊相對於導電元件228a的位移會大於相對於導電元件228b的位移。因此，在僅包含一個半導體晶粒的相似大小的微電子元件內，複數條焊線232b可具有低於的高度。
第7至12圖係顯示製造微電子元件10的方法之各種步驟。 第7圖顯示由半導體晶粒12組成的製造中單元10'，如上所述，其在第一表面14上有導電元件28。在第8圖中，製造中單元10"係顯示複數條焊線32形成在半導體晶粒12之導電元件28上。此複數條焊線可以特別採用的設備來形成，此設備可藉由加熱通過接合細管的線路前端而在一組件中形成複數條連續焊線。此細管係對準複數個導電元件28中的其中一個，進而對準線路之前端。然後，藉由適當移動細管來加壓已加熱的自由端，使得焊線之底座34接合到導電元件28。
當所需長度的線路已經從細管拉出藉此延伸高於半導體晶 粒12之第一表面14到一適當距離，此距離係針對待形成的焊線高度(其亦可包含線路定位以達到其自由端36及/或焊線32本身塑形所需的位置)，此線路係用以將端表面38上的焊線32脫離此部分線路，此部分尚在細管內且用於形成連續焊線。重複此製程直到所需數量的複數條焊線形成。有各種步驟以及結構可用於切斷焊線32，包含放電結球(electronic flame-off，EFO)，各種切割方式或其他相似方式，美國專利申請案13/462,158以及13/404,408，以及美國專利8,372,741已提供範例。以下係參考第14圖以及第15圖以說明切斷焊線之進一步範例。在上述的焊線形成步驟之變化型， 如美國專利申請案13/404,408所述，使用特别採用的設備，藉由邊緣接合步驟(包含楔形接合或是針腳式接合)，複數條焊線32可形成在製造中單元10"上。
形成所需數量的複數條焊線32之後，可在製造中單元10" 上沉積可流動狀態(在變硬或固化之前)的所需材料以形成柔性材料層42，如第9圖所示。將此單元10'放置在適當規劃的模子即完成此步驟，此模子具有柔性材料層42之所需形狀的腔以收納單元10'。形成柔性材料層之此模子以及本方法可用與在基板上的複數條焊線上方形成封裝層的程序(其已在美國專利申請案2010/0232129揭露)相似的程序，本發明係參考其所揭露的全部內容。可形成柔性材料層42使得表面44最初高於複數條焊線32之端表面38並彼此隔開。為了形成延伸部40(包含端表面38)，可移除封裝層42之高於端表面38的部分，並創建低於端表面38的新表面44。或者，可形成柔性材料層42使得表面44最初低於端表面38一距離，如果需要，可定義脫離部分40之所需高度，並藉由研磨、乾蝕刻、雷射蝕刻、濕式蝕刻或其他相似技術除去一部分封裝層42。如果需要，亦可在相同或是額外的步驟中移除複數條焊線32之一部分自由端36，以達到實質上彼此相同的平坦端表面38。
如上所述，上述步驟所產生的微電子元件10或是其變化型， 可封裝在基板上或是設置PCB上。此些後續步驟的任一步驟可用相似方式執行。例如第10圖所示，可藉由沉積導電金屬塊66來製造接合外部器件的微電子元件10，導電金屬塊66可為在複數條焊線32之延伸部40上方的焊料或其他相似材料。可冷卻以及凝固導電金屬塊66使得導電金屬塊66 至少暫時地保持固定在個別延伸部40的位置上。如第11圖所示，第10圖的微電子元件10可將PCB 90對準導電金屬塊66，以及將複數條焊線32之延伸部40對準PCB之接觸墊92。然後，導電金屬塊66係接觸墊片並加熱回焊導電材料以與墊片92相接合，而將微電子元件10固定至PCB 90，如第12圖所示。
在第10至12圖之安裝步驟之變化型中，導電金屬塊66可 沉積在接觸墊92上，如第13圖所示針對微電子元件安裝的製造。然後，微電子元件10可位於PCB 90上方且複數條焊線32之延伸部40對準導電金屬塊66(以及接觸墊92)。可加熱導電金屬塊66造成回焊，而微電子元件10可朝向PCB 90移動使得延伸部40位於導電金屬塊66內，接著冷卻以接合延伸部40。
上述步驟(第10圖、第12圖以及第13圖)之任一個亦可用於接合微電子元件10，在封裝組件24中形成基板46，如第2圖所述。封裝件24上可進一步沉積成型電介質68，如第2圖所示，其可使用在微電子封裝形成成型電介質的成型法或其他方法來完成。或者，可在微電子元件10以及環繞導電金屬塊66的基板46之間沉積底部填充劑。
如第5以及6圖所示，上述方法步驟之變化型亦可用於形成、封裝或是安裝多晶粒配置。在此變化型中，焊線形成(可用在此討論的任何方法完成)之前或之後，第二晶粒22可安裝在晶粒12上。在第6圖之範例中，在焊線形成之前將晶粒222安裝上晶粒212會導致複數條焊線232一次全部形成，而不須後續步驟。晶粒安裝以及焊線形成之後，可如上所述沉積柔性層242以及342，而且可安裝封裝件，如先前討論且使用單一 晶粒微電子元件10的相同方式。
第14以及15圖係顯示用於焊線形成之特别方法步驟期間 的製造中單元10'。如第14圖所示，線路接合工具之細管70係接近基板12之第一表面14。第4圖係大略地顯示細管70，其係隨著相關聯的接合工具(圖中未顯示)，細管70可通常為以上描述之類型且可將複數條焊線32之底座34接合至半導體晶粒12之導電元件28。
在方法步驟之特别設定中，針對待形成的焊線之所需高度， 在所需長度的線路74已經拉出細管70之後，使用細管70之面76以及副表面80切斷77並適當地設置。如第14圖所示，移動細管70以開始切斷以及定位至副表面80上方的位置，其係大略地顯示在第14圖中的元件之表面。在各種應用中，針對以下描述的切斷應用，副表面80可在有充分硬度之元件上，如金屬或其他相似材料。此元件可在一位置上附著接合工具以接續細管70，並在線路接合製程期間移動。在另一範例中，此元件可相對於接合工具固定在半導體晶粒12之區域中。
在第14圖所示的範例中，細管70係位於副表面80上方。 細管70適當地定位後，係朝向副表面80對在副表面80以及細管70之從線路74向外延伸的面76之間的一部分線路74加壓。然後，壓力係施加至線路以使得面76朝向副表面80移動，其係加壓在其之間的線路74，造成線路74之塑性變形，例如，在區域78內的線路之平坦化或是壓縮。透過此變形，線路74之區域78變得比任一側上的線路74之剩餘部分更脆弱，也比底座34以及接觸部30之間的接合更脆弱。例如，相對於任一側上的線路74之其他部分，區域78會較平坦、壓縮或是扭曲。
線路74之區域78變形之後，細管70接著移動回到待形成 的焊線32之自由端36最後的所需位置。相對於所述第3B以及3C圖之範例，此位置可直接在底座43上方或是可橫向地位移。細管70之位置通常可在自由端36之所需側面的區域，可比最後所需的位置更靠近第一表面14。 進一步，此線路可保持部分地彎曲，包含與上述討論之完成的複數條焊線32之形狀相似，其含有第一部分52以及第二部分54。
然後，細管70可遠離表面14移動以施加張力至細管70以 及底座34之間的此段線路74(其可鉗夾或是牢固於細管70內)。此張力使得線路74斷在區域78，如第15圖所示，其將焊線32與線路74之剩餘部分分離，此剩餘部分具有自由端36之端表面38定義在其上的尖端62所形成的區域78之一部分。區域78之剩餘部分係維持在線路74之新的前端72'上。這些步驟可在半導體晶粒12之表面14上的其他導電元件28上重複執行，以形成所需圖樣的焊線32陣列。
在較佳實施例之詳細說明中所提出之具體實施例僅用以方便說明本發明之技術內容，而非將本發明狹義地限制於上述實施例，在不超出本發明之精神及以下申請專利範圍之情況，所做之種種變化實施，皆屬於本發明之範圍。
10‧‧‧微電子結構
12‧‧‧半導體晶粒
14‧‧‧第一表面
16‧‧‧第二表面
23‧‧‧邊緣表面
28‧‧‧導電元件
32‧‧‧焊線
34‧‧‧底座
36‧‧‧自由端
40‧‧‧延伸部
42‧‧‧柔性材料層
44‧‧‧主表面
45‧‧‧表面

Claims (21)

  1. 一種微電子結構，包含：一半導體晶粒，係具有相背對的一第一表面以及一第二表面、以及在該第一表面上的一群組的複數個導電元件；複數條焊線，具有分別與複數個導電元件相接合的複數個底座，該複數條焊線係進一步具有遠離該複數個底座的複數個自由端，該複數個自由端係遠離基板以及該複數個底座，且該複數個自由端上包含有複數個端表面，該複數條焊線係定義在該複數個底座以及該複數個端表面之間延伸的複數個邊緣表面；以及一柔性(Compliant)材料層，係延伸覆蓋於該複數條焊線之該複數個底座以外的該半導體晶粒之該第一表面上，該柔性材料層之延伸，係進一步沿著該複數條焊線之該複數個邊緣表面之至少鄰近該底座的複數個第一部分，以填充該複數條焊線之該複數個第一部分之間的複數個空間，使得該複數條焊線之該複數個第一部分藉由該柔性材料層而彼此相分離，該柔性材料層之一第三表面背對該半導體晶粒之該第一表面，其中該複數條焊線之複數個第二部分係遠離該第三表面而延伸，該複數個第二部分係包含該複數個複數條焊線之該複數個自由端。
  2. 如申請專利範圍第1項所述之微電子結構，其中該複數條焊線之該複數個第一部分係由該柔性材料完全地封裝，其中該複數條焊線之該複數個第二部分可相對於該複數個底座移動。
  3. 如申請專利範圍第1項所述之微電子結構，其中該柔性材料層具有2.5GPa或是更小的楊氏模數。
  4. 如申請專利範圍第1項所述之微電子結構，其中該複數條焊線之該複數個第二部分係沿著該複數條焊線之軸線延伸，該軸線之設置相對於第三表面至少為30度角。
  5. 如申請專利範圍第1項所述之微電子結構，其中該複數條焊線之該複數個端表面之位置係高於第三表面至少50μm之距離。
  6. 如申請專利範圍第1項所述之微電子結構，其中該半導體晶粒係進一步定義在該第一表面以及該第二表面之間延伸的複數個邊緣表面，而該柔性材料層係進一步包含從該第三表面延伸至該半導體晶粒之該第一表面的複數個邊緣表面，藉此與該半導體晶粒之該複數個邊緣表面實質上共平面。
  7. 如申請專利範圍第1項所述之微電子結構，其中該複數條焊線中的至少一個的形狀係使得該焊線能定義該自由端以及該底座之間的軸線，並使得該焊線定義一平面，該至少一焊線之一彎曲部係遠離該平面內的該軸線延伸。
  8. 如申請專利範圍第7項所述之微電子結構，其中該至少一焊線之該形狀進一步使得該焊線之一實質直線部，係在該自由端以及該彎曲部之間沿著該軸線延伸。
  9. 如申請專利範圍第1項所述之微電子結構，更包含複數個導電金屬塊，係接合該複數條焊線之該複數個第二部分，以及接觸該柔性材料層之該第三表面。
  10. 如申請專利範圍第9項所述之微電子結構，其中該複數個導電金屬塊中的至少一個係各自封裝一焊線之至少一些該第二部分。
  11. 如申請專利範圍第9項所述之微電子結構，其中該複數個導電金屬塊係藉由回焊將該複數條焊線之該複數個第二部分與複數個外部導電零件相接合。
  12. 如申請專利範圍第1項所述之微電子結構，其中：該半導體晶粒係為一具有一第一區以及環繞該第一區之一第二區的一第一半導體晶粒；該第一半導體晶粒之該複數個導電元件係在該第二區內；該微電子結構進一步包含一第二半導體晶粒，係設置在該第一區內的該第一半導體晶粒上，該第二半導體晶粒係電性連接該第一半導體晶粒之至少一些導電元件；以及 該柔性材料層係覆蓋該第二半導體晶粒。
  13. 如申請專利範圍第1項所述之微電子結構，其中：該半導體晶粒係為一具有一第一區以及環繞該第一區之一第二區的一第一半導體晶粒；該第一半導體晶粒之該複數個導電元件係在該第二區內；該微電子結構進一步包含一第二半導體晶粒，該第二半導體晶粒係設置在該第一區內的該第一半導體晶粒上，且具有相背對的一第一表面以及一第二表面、以及一群組之複數個導電元件，該複數個導電元件係位在背對該第一半導體晶粒之該第一表面的該第一表面上，其中複數條額外焊線具有複數個底座，係各自接合到該第二半導體晶粒之該複數個導電元件中的其中一個，該複數條額外焊線進一步具有遠離該複數個底座的複數個自由端，該複數個自由端係遠離該第二半導體晶粒之該第一表面以及該複數個底座，並包含複數個該端表面，該複數條焊線係定義在該複數個底座以及該複數個端表面之間延伸的複數個邊緣表面；以及該柔性材料層係進一步位在該複數條額外焊線之該複數個底座外部的該第二半導體晶粒之該第一表面上並延伸而出，且該柔性材料層係進一步沿著該複數條額外焊線之該複數個邊緣表面之複數個第一部分延伸，其中該複數條額外焊線之複數個第二部分係由該複數個端表面以及從該複數個端表面延伸出的該複數個邊緣表面之複數個部分所定義，該複數個部分係未被在該第三表面上的該柔性材料層所覆蓋且延伸遠離該第三表面上的該柔性材料層。
  14. 一種微電子封裝件，包含：一微電子元件，包含一第一半導體晶粒，係具有相背對的一第一表面以及一第二表面、以及在該第一表面上的一群組(Plurality)的複數個導電元件；複數條焊線，具有複數個底座，各自接合在該第一表面上的該複數個導電元件，以及具有複數個端表面，該複數個端表面係遠離一基板以及該複數個底座，每一該複數條焊線係從該底座延伸至該端表面；以及一柔性材料層(Compliant Material Layer)，係覆蓋該基板之該第一表面的第一部分上並從而延伸，並填充於該複數條焊線之該複數個第一部分之間的複數個空間，使得該複數條焊線之該複數個第一部分係藉由該柔性材料層而彼此相分離，該柔性材料層具有背對該基板之該第一表面的一第三表面，其中該複數條焊線之複數個第二部分係遠離該第三表面而延伸，該複數個第二部分係包含該複數個複數條焊線之該複數個自由端；其中該基板係具有一第四表面以及在該第四表面上暴露的一群組之複數個端子；其中該微電子元件係安裝於該基板上，且該第三表面係面向該第四表面，該複數條焊線之至少一些之該複數個第二部分係各自與該複數個端子接合。
  15. 如申請專利範圍第14項所述之微電子封裝件，其中該複數條焊線之該複數個第二部分係藉由複數個導電金屬塊，電性地以及機械性地與該複數個端子相接合。
  16. 如申請專利範圍第14項所述之微電子封裝件，更包含一成型介電層(Molded Dielectric Layer)，係形成在該基板之該第四表面之至少一部分上，並從而延伸，藉此沿著該微電子元件之至少一部分延伸。
  17. 如申請專利範圍第16項微電子封裝件，其中該成型介電層之該楊氏模數係大於該柔性材料層之該楊氏模數。
  18. 如申請專利範圍第14項所述之微電子封裝件，其中該柔性材料層具有低於2.5GPa的楊氏模數。
  19. 如申請專利範圍第14項所述之微電子封裝件，其中該複數條焊線係進一步定義在該複數個底座以及該複數個端表面之間延伸的複數個邊緣表面，而其中該柔性材料層係沿著該複數條焊線之至少鄰近該底座之邊緣表面之複數個部分，且在該複數條焊線之該複數個第一部分內延伸。
  20. 如申請專利範圍第19項所述之微電子封裝件，其中從該端表面延伸出的該複數條焊線之該複數個邊緣表面之複數個部分在該第三表面上係不被該柔性材料層之全部周長覆蓋。
  21. 一種製造微電子結構的方法，包含：在一半導體晶粒上形成複數條焊線，該半導體晶粒具有相背對的一第一表面以及一第二表面、以及在該第一表面的一群組之複數個導電元件，所形成之該複數條焊線係具有複數個底座，以分別接合到該複數個導電元件，且該複數條焊線具有遠離基板以及該複數個底座的複數個端表面，該複數條焊線之複數個邊緣表面係在該複數個底座以及該複數個端表面之間延伸；以及形成一柔性材料層覆蓋於該複數條焊線之該複數個底座外部的該半導體晶粒之該第一表面上並從而延伸出，所形成之該柔性材料層係進一步沿著該複數條焊線之複數個第一部分之該複數個邊緣表面之複數個部分延伸，以填充該複數條焊線之該複數個第一部分之間的複數個空間，藉此將該複數條焊線之該複數個第一部分相分離，其中該柔性材料層係進一步形成具有背對該基板之該第一表面的一第三表面，且該複數條焊線之複數個第二部分係延伸遠離該第三表面，該複數個第二部分係包含該複數條焊線之該複數個自由端。
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