KR100948569B1 - 반도체 집적회로장치 - Google Patents
반도체 집적회로장치 Download PDFInfo
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- KR100948569B1 KR100948569B1 KR1020080016740A KR20080016740A KR100948569B1 KR 100948569 B1 KR100948569 B1 KR 100948569B1 KR 1020080016740 A KR1020080016740 A KR 1020080016740A KR 20080016740 A KR20080016740 A KR 20080016740A KR 100948569 B1 KR100948569 B1 KR 100948569B1
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- 239000004065 semiconductor Substances 0.000 title abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims description 56
- 239000002184 metal Substances 0.000 claims description 56
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229910021332 silicide Inorganic materials 0.000 claims description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 2
- 238000000926 separation method Methods 0.000 claims 1
- 238000005452 bending Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 127
- 229910052581 Si3N4 Inorganic materials 0.000 description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 18
- 238000010586 diagram Methods 0.000 description 15
- 238000005530 etching Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 238000001312 dry etching Methods 0.000 description 6
- 101150110971 CIN7 gene Proteins 0.000 description 5
- 101100286980 Daucus carota INV2 gene Proteins 0.000 description 5
- 101150110298 INV1 gene Proteins 0.000 description 5
- 101100397044 Xenopus laevis invs-a gene Proteins 0.000 description 5
- 101100397045 Xenopus laevis invs-b gene Proteins 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
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- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
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- 238000000206 photolithography Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/783—Field effect transistors with field effect produced by an insulated gate comprising a gate to body connection, i.e. bulk dynamic threshold voltage MOSFET
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
- Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors
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Abstract
Description
Claims (10)
- 제1 및 제 2 비트선과,제1 워드선과,제 1 N-채널 MOS 트랜지스터 및 제1 P-채널 MOS 트랜지스터를 포함하는 제1 인버터와, 제2 N-채널 MOS 트랜지스터 및 제2 P-채널 M0S 트랜지스터를 포함하고 그 입력 단자가 상기 제 1 인버터의 출력 단자에 접속되고 그 출력 단자가 상기 제 1 인버터의 입력 단자에 접속된 제2 인버터와, 소스·드레인 경로를 상기 제 1 인버터의 출력 단자와 상기 제 1비트선과의 사이에 가지는 제3 N-채널 MOS 트랜지스터와, 소스·드레인 경로를 상기 제 2 인버터의 출력 단자와 상기 제 2 비트선과의 사이에 가지는 제4 N-채널 MOS 트랜지스터를 갖는 메모리셀과,상기 제1 및 제3 N-채널 M0S 트랜지스터는 제1 P-타입 웰 영역에 형성되고,상기 제2 및 제4 N-채널 M0S 트랜지스터는 제2 P-타입 웰 영역에 형성되고,상기 제1 및 제2 P-채널 MOS 트랜지스터는 상기 제1 P-타입 웰 영역과 제2 P-타입 웰 영역의 사이에 위치한 N-타입 웰 영역에 형성되고,상기 제1 P-타입 웰 영역은 제1 확산층을 포함하고,상기 N-타입 웰 영역은 제2 및 제3 확산층을 포함하고,상기 제1 확산층의 각각의 장변을 따라 확장되는 분리층에 의해 경계 지워지는 상기 제1 확산층의 외형은 상기 제1 P-타입 웰 영역을 통하는 제1 방향으로 연장되는 라인에 대해 실질적으로 선대칭이고,상기 제1 P-타입 웰 영역과 상기 N-타입 웰 영역의 경계는 상기 제1 방향으로 연장되고,상기 제1 인버터의 입력단자는 상기 제1 N-채널 MOS 트랜지스터와 상기 제1 P-채널 MOS 트랜지스터에 공통으로 속하는 제1 게이트 전극이고,상기 제2 인버터의 입력단자는 상기 제2 N-채널 MOS 트랜지스터와 상기 제2 P-채널 MOS 트랜지스터에 공통으로 속하는 제2 게이트 전극이고,상기 제1 및 제2 게이트 전극은 제1 및 제2 접속 영역에 있는 실리사이드를 경유하여 각각 상기 제1 및 제2 확산층에 접속되어 있고,상기 제1 및 제2 접속 영역은 모두 상기 N-타입 웰 영역에 형성되어 있는 것을 특징으로 하는 반도체집적회로장치.
- 청구항 1에 있어서,상기 제1 P-타입 웰 영역에 있는 상기 제1 확산층의 외형은 직사격형들의 조합의 형태인 것을 특징으로 하는 반도체집적회로장치.
- 청구항 1에 있어서,상기 제1 비트선은 제1 전원공급선과 제1 배선의 사이에 위치하고,상기 제2 비트선은 상기 제1 전원공급선과 제2 배선의 사이에 위치하고,상기 제1 배선은 상기 제1 N-채널 MOS 트랜지스터의 소스와 결합되고, 상기 제2 배선은 상기 제2 N-채널 MOS 트랜지스터의 소스와 결합되는 것을 특징으로 하 는 반도체집적회로장치.
- 청구항 3에 있어서,상기 제1 비트선, 상기 제1 전원공급선 및 상기 제1, 제2 배선은 동일한 금속층 레벨을 갖는 금속층들인 것을 특징으로 하는 반도체집적회로장치.
- 청구항 1에 있어서,상기 제1 N-채널 MOS 트랜지스터의 상기 게이트 폭은 상기 제3 N-채널 MOS 트랜지스터의 상기 게이트 폭보다 큰 것을 특징으로 하는 반도체집적회로장치.
- 청구항 1에 있어서,상기 제1 워드선은 기판과 상기 제1 및 제2 비트선의 사이의 금속층에 놓여 있는 것을 특징으로 하는 반도체집적회로장치.
- 청구항 1에 있어서,상기 제3 N-채널 MOS 트랜지스터의 게이트로서 사용하기 위한 제1 다결정질 실리콘 리드 층과 상기 제1 P-채널 MOS 트랜지스터의 게이트와 상기 제1 N-채널 MOS 트랜지스터의 게이트로서 사용하기 위한 제2 다결정질 실리콘 리드 층 서로 평행하게 배치되고,상기 제4 N-채널 MOS 트랜지스터의 게이트로서 사용하기 위한 제3 다결정질 실리콘 리드 층과 상기 제2 N-채널 MOS 트랜지스터의 게이트와 상기 제2 P-채널 MOS 트랜지스터의 게이트로서 사용하기 위한 제4 다결정질 실리콘 리드 층 서로 평행하게 배치되고,상기 제1 및 제3 다결정질 실리콘 리드층은 상기 제1 워드선을 구성하는 금속 리드층의 제2 층에 콘텍트를 통하여 접속되는 것을 특징으로 하는 반도체집적회로장치.
- 제1 인버터 및 제2 인버터와,상기 제1 인버터의 출력이 제2 인버터의 입력에 결합되고 상기 제2 인버터의 출력이 상기 제1 인버터의 입력에 결합되고,상기 제1 인버터의 출력과 상기 제2 인버터의 입력 사이의 접속노드에 접속되는 제1 스위치와,상기 제1 인버터의 입력과 상기 제2 인버터의 출력 사이의 접속노드에 접속되는 제2 스위치와,N-타입 웰 영역과 상기 N-타입 웰 영역의 반대측에 설치되는 제1 및 제2 P-타입 웰 영역을 갖고,상기 N-타입 웰 영역과 상기 제1 및 제2 P-타입 웰 영역의 각각에 형성된 확산층은, 상기 N-타입 웰 영역 및 상기 제1 및 제2 P-타입 웰 영역의 경계 선의 연장 방향의 긴 측면들을 가진 기본적으로 단일 사각형으로 구성된 형태, 상기 N-타입 웰 영역 및 상기 제1 및 제2 P-타입 웰 영역의 경계선의 연장 방향의 다수의 사 각형의 조합형태로부터 되고 상기 사각형들은 상기 연장 방향에 긴 측면들을 가진 형태 중 어느 하나를 갖고 평면 형상으로 배열되고,상기 제1 인버터의 입력단자는 상기 N-타입 웰 영역에 형성되고 상기 제2 인버터의 출력단자로 되는 상기 확산층에 접속되고,상기 제1 인버터의 상기 입력단자는 상기 N-타입 웰 영역에 형성되어 있는 제1 접속 영역에 있는 실리사이드를 통하여 상기 제 2 인버터의 상기 출력단자로 되는 상기 확산층에 접속되고,상기 제2 인버터의 입력단자는 상기 N-타입 웰 영역에 형성되고 상기 제1 인버터의 출력단자로 되는 상기 확산층에 접속되고,상기 제2 인버터의 상기 입력단자는 상기 N-타입 웰 영역에 형성되어 있는 제2 접속 영역에 있는 실리사이드를 통하여 상기 제1 인버터의 상기 출력단자로 되는 상기 확산층에 접속되는 것을 특징으로 하는 반도체집적회로장치.
- 청구항 8에 있어서,상기 N-타입 웰 영역 및 상기 P-타입 웰 영역에 형성된 상기 확산층은,제1 길이의 짧은 측면을 따라 상기 제1 및 제2 P-타입 웰 영역 및 상기 N-타입 웰 영역의 경계선들의 연장방향으로 긴 측면들을 가진 제 1 사각형과, 제2 길이의 짧은 측면을 따라 상기 제1 및 제2 P-타입 웰 영역 및 상기 N-타입 웰 영역의 경계선들의 연장방향으로 긴 측면들을 가진 제 2 사각형들의 조합으로 된 조합 형성된 평면 형태를 가지고,상기 조합은 상기 경계선들의 연장 방향에 있는 것을 특징으로 하는 반도체집적회로장치.
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KR1020000025125A KR100796215B1 (ko) | 1999-05-12 | 2000-05-10 | 반도체 집적회로장치 |
KR1020070062452A KR20070077162A (ko) | 1999-05-12 | 2007-06-25 | 반도체 집적회로장치 |
KR1020070107160A KR100928694B1 (ko) | 1999-05-12 | 2007-10-24 | 반도체 집적회로장치 |
KR1020080016740A KR100948569B1 (ko) | 1999-05-12 | 2008-02-25 | 반도체 집적회로장치 |
KR1020080094648A KR20080093008A (ko) | 1999-05-12 | 2008-09-26 | 반도체 집적회로장치 |
KR1020090101702A KR100977760B1 (ko) | 1999-05-12 | 2009-10-26 | 반도체 집적회로장치 |
KR1020100034209A KR101079215B1 (ko) | 1999-05-12 | 2010-04-14 | 반도체 집적회로장치 |
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