CN108352361B - 用于干扰屏蔽的引线接合线 - Google Patents

用于干扰屏蔽的引线接合线 Download PDF

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CN108352361B
CN108352361B CN201680058110.0A CN201680058110A CN108352361B CN 108352361 B CN108352361 B CN 108352361B CN 201680058110 A CN201680058110 A CN 201680058110A CN 108352361 B CN108352361 B CN 108352361B
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microelectronic device
substrate
wire bond
wire
ground plane
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CN108352361A (zh
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阿比欧拉·奥佐拉
孙卓文
惠尔·佐尼
阿修克·S·普拉布
威尔玛·苏比杜
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British Sails
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Abstract

大致有关于具有免于干扰的保护的微电子封装的设备是被揭示。在本发明的设备中，基板是具有上表面以及与该上表面相对的下表面，并且具有接地面。第一微电子装置是耦接至该基板的该上表面。引线接合线是耦接至该接地面以用于传导该干扰至其，并且从该基板的该上表面延伸离开。该些引线接合线的第一部分是被设置以提供用于该第一微电子装置的相关该干扰的屏蔽区域。该些引线接合线的第二部分并未被设置以提供该屏蔽区域。第二微电子装置是耦接至该基板，并且位在该屏蔽区域之外。导电表面是在该些引线接合线的该第一部分之上，以用于覆盖该屏蔽区域。

Description

用于干扰屏蔽的引线接合线
技术领域
以下的说明是大致有关用于垂直的互连及/或干扰屏蔽的引线接合线。
背景技术
微电子组件一般包含一或多个IC，例如是一或多个经封装的晶粒("晶片")或是一或多个晶粒。此种IC中的一或多个可被安装在电路平台之上，例如像是晶圆层级封装("WLP")的晶圆、印刷板("PB")、印刷线路板("PWB")、印刷电路板("PCB")、印刷线路组件("PWA")、印刷电路组件("PCA")、封装基板、中介体、或是晶片载体。此外，IC可被安装在另一IC之上。中介体可以是被动式IC或是主动式IC，其中后者是包含一或多个例如是电晶体的主动装置，而前者并不包含任何主动装置，但是可包含一或多个例如是电容器、电感器、及/或电阻器的被动装置。再者，中介体可被形成像是PWB，亦即不具有任何的电路元件，例如是不具有任何被动或主动装置。此外，中介体可包含至少穿过基板的贯孔(via)。
IC例如可包含导电的元件，例如是路径、线路、轨迹、贯孔、接点、像是接触垫及焊垫的垫、插塞、节点、或是端子，其可被使用于与一电路平台电互连。这些配置可以使得被用来提供IC的功能的电连接变得容易。IC可以藉由接合来耦接至一电路平台，例如是接合此种电路平台的线路或端子至IC的焊垫或是接脚或柱的露出的末端或类似者；或是IC可以藉由焊接来耦接至电路平台。此外，重分布层("RDL")可以是IC的部分，以例如使得覆晶的配置、晶粒堆叠、或是焊垫的更便利或可接达的位置变得容易。
某些被动或主动微电子装置可以与电磁干扰("EMI")及/或射频干扰("RFI")加以屏蔽开。然而，习知的屏蔽可能是制造上复杂的、对于某些行动应用而言是过重的、且/或对于某些低轮廓的应用而言是过大的。再者，某些屏蔽可能并不适合用于大致被称为三维的(”3D”)IC或是”3D IC"的一堆叠的晶粒或是堆叠的封装。
于是，提供对于习知的干扰屏蔽的改良的干扰屏蔽将会是所期望而且是有用的。
发明内容
一种设备是大致有关于具有免于干扰的保护的微电子封装。在此种设备中，基板是具有上表面以及与该上表面相对的下表面，并且具有接地面。第一微电子装置是耦接至该基板的该上表面。引线接合线是耦接至该接地面以用于传导该干扰至该接地面，并且从该基板的该上表面延伸离开。该些引线接合线的第一部分是被设置以提供用于该第一微电子装置的相关该干扰的屏蔽区域。该些引线接合线的第二部分并未被设置以提供该屏蔽区域。第二微电子装置是耦接至该基板，并且位在该屏蔽区域之外。导电表面是在该些引线接合线的该第一部分之上，以用于覆盖该屏蔽区域。
一种设备是大致有关于另具有免于干扰的保护的微电子封装。在此种设备中，基板是具有上表面以及与该上表面相对的下表面，并且具有接地面。微电子装置是耦接至该基板的该上表面。引线接合线是被接合到该基板的该上表面，并且从该基板的该上表面延伸离开。该些引线接合线的第一部分是具有第一高度，并且接近该第一微电子装置而且在该第一微电子装置的周围来加以设置，以用于提供用于该第一微电子装置的相关该干扰的屏蔽区域。该些引线接合线的该第一部分是耦接至该接地面以用于传导该干扰至该接地面。该些引线接合线的第二部分是具有小于该第一高度的第二高度，并且接近该第一微电子装置而且在该第一微电子装置的周围来加以设置。该些引线接合线的该第二部分是包含用于电耦接该微电子装置与该基板的信号线。导电表面是在该些引线接合线之上，以用于覆盖该屏蔽区域。该些引线接合线的该第一部分的上末端是机械式地耦接至该导电表面。
一种设备是大致有关于又具有免于干扰的保护的微电子封装。在此种设备中，基板是具有上表面以及与该上表面相对的下表面，并且具有接地面。第一微电子装置是耦接至该基板的该上表面。引线接合线的下末端是耦接至该接地面以用于传导该干扰至其。该些引线接合线的第一部分是被设置以提供用于该第一微电子装置的相关该干扰的屏蔽区域。该些引线接合线的第二部分并未被设置以提供该屏蔽区域。第二微电子装置是耦接至该基板，并且位在该屏蔽区域之外。导电表面是使得该些引线接合线的该第一部分耦接至其。该导电表面是覆盖该屏蔽区域并且界定该屏蔽区域，其中该些引线接合线的该第一部分是从该导电表面延伸离开。
附图说明
所附的图式是展示根据范例的设备或方法的一或多个特点的范例实施例。然而，所附的图式不应该被视为限制申请专利范围的范畴，而只是用于解说及理解而已。
图1A是描绘不具有电磁干扰("EMI")屏蔽的范例的习知系统级封装("SiP")的侧视方块图。
图1B是描绘另一不具有EMI屏蔽的范例的习知的SiP的侧视方块图。
图2是描绘具有习知的EMI屏蔽的范例的部分的角落的俯视立体图。
图3A及3B是描绘个别的具有EMI屏蔽的范例的SiP的俯视方块图。
图4是描绘具有EMI屏蔽的范例的SiP的侧视横截面方块图。
图5是描绘范例性的SiP的侧视横截面方块图，其是具有导电罩盖并且具有在该导电罩盖之下的EMI屏蔽区域中的信号引线接合线。
图6是描绘具有利用上方的基板的EMI屏蔽的范例的SiP的侧视横截面方块图。
图7是描绘在法拉第笼(Faraday cage)的上方的导电表面的加入之前的SiP的范例的部分的俯视方块图。
图8是描绘在法拉第笼的上方的导电表面的加入之前的另一SiP的范例的部分的俯视方块图。
图9A是描绘具有EMI屏蔽的堆叠式封装("PoP")装置的范例的部分的侧视横截面方块图。
图9B是描绘另一具有EMI屏蔽的PoP装置的范例的部分的侧视横截面方块图。
图10是描绘另一具有EMI屏蔽的SiP的范例的部分的侧视横截面方块图。
图11A是描绘不具有引线接合线EMI屏蔽的SiP的范例的部分的侧视横截面方块图。
图11B是描绘另一不具有引线接合线EMI屏蔽的SiP的范例的部分的侧视横截面方块图。
图12A至12D是描绘个别的不具有引线接合线EMI屏蔽的SiP的范例的部分之个别的侧视横截面方块图。
图13A至13D是描绘个别的不具有引线接合线EMI屏蔽而具有垂直整合的微电子封装的SiP的范例的部分的个别的侧视横截面方块图。
具体实施方式
在以下的说明中，许多特定的细节是被阐述，以提供在此所述的特定例子的更彻底的说明。然而，对于熟习此项技术者应该明显的是，一或多个其它例子或是这些例子的变化可以在无所有以下给出的特定细节下加以实施。在其它实例中，众所周知的特点并未详细地叙述，以防模糊在此的例子的说明。为了便于说明，相同的元件符号是在不同的图中被使用以参照到相同的项目；然而，在替代的例子中，该些项目可以是不同的。
范例的设备及/或方法是在此加以描述。应了解的是，该字词"范例的"是在此被使用以表示"当作为一个例子、实例、或是例证"。任何在此叙述为"范例"的例子或特点并不一定被解释为相对其它例子或特点为较佳或是有利的。
干扰可能是电磁干扰("EMI")及/或射频干扰("RFI")。干扰屏蔽的以下的说明可被使用于这些类型的干扰的任一种或是两者。然而，为了举例且非限制性的清楚的目的起见，大致只有针对EMI的屏蔽是在以下用额外的细节来加以描述。
图1A是描绘不具有EMI屏蔽的范例的习知系统级封装("SiP")10的侧视方块图。在SiP 10中，可以有耦接至封装基板19的一或多个主动微电子装置11、被动微电子装置12、及/或IC晶粒13。在此例子中，可以是一被动式或主动式的晶粒的IC晶粒13可能会遭受到EMI。IC晶粒13可以利用引线接合15而被引线接合至封装基板19，该些引线接合15是用于载有输入/输出及其它信号、电源电压以及接地参考。
封装基板19可以是由称为积层或积层基板的薄层所形成的。积层可以是有机或无机的。用于"刚性"封装基板的材料例子是包含例如是FR4或FR5的环氧树脂基的积层、例如是双马来酰亚胺-三嗪("BT")树脂基的积层、陶瓷基板(例如，低温共烧陶瓷(LTCC))、玻璃基板、或是其它形式的刚性封装基板。再者，封装基板19在此可以是PCB或是其它电路板。为了清楚的目的起见，其它有关习知的SiP 10的已知的细节并未被叙述。
图1B是描绘另一不具有EMI屏蔽的范例的习知的SiP 10的侧视方块图。除了例如是微凸块的覆晶的("FC")互连17被使用，而不是引线接合15之外，图1B的SiP 10是与图1A的SiP 10相同的。即使微凸块互连17是说明性地被描绘，但是其它类型的晶粒表面安装的互连亦可被使用。再者，尽管未说明性地描绘在图1B中，但是微凸块互连17可以在引线接合15之外另外被使用。
图2是描绘一习知的EMI屏蔽20的一范例的部分的角落的俯视立体图。在习知的EMI屏蔽20中，一顶端导电板23可被设置在一底部导电板24之上，其中此种底部导电板24具有一大于此种顶端导电板23的表面积。
导电板23及24分别可以耦接至一具有引线接合21及22的列的封装基板19。因此，顶端板23的两个侧边可以与对应的列的引线接合21来加以引线接合，并且底部板24的两个侧边同样地可以与对应的列的引线接合22来加以引线接合。非导电的间隙壁(未显示)可被用来隔离引线接合21与底部导电板24。一待被EMI屏蔽的微电子装置(未显示)可被夹设在顶端及底部导电板23及24之间。此类型的具有引线接合的EMI屏蔽对于许多应用而言可能是过于庞大的。再者，在相关提供侧边EMI屏蔽的引线接合的相对的侧边上可能会有间隙。
干扰屏蔽
图3A及3B是描绘个别的具有EMI屏蔽的范例的SiP 100的俯视方块图。SiP 100的每一个都可包含一封装基板19，其具有耦接至其之一上表面132的一或多个主动微电子装置11、一或多个被动微电子装置12、以及引线接合线131，其中此种引线接合线131的上末端可以耦接至一上表面132。上表面132可以是一导电表面。引线接合线131可包含等于或小于约0.0508毫米(2密耳)的导线直径。
引线接合线131的一部分可被设置以界定一屏蔽区域133。以此种方式，引线接合线131的一BVA配置136的列与行可被用来包围或者是围绕一屏蔽区域133。此种引线接合线131的至少一子集合的围绕一屏蔽区域133的上末端可被用来支撑导电表面130，因而此种导电表面130可以是在此种屏蔽区域133之上，以用于其覆盖。
导电表面130可以是一导电的刚性或挠性的表面。在一实施方式中，导电表面130可以是挠性的，例如是在一挠性的片的一表面上的一挠性的导电的涂层。在另一实施方式中，一刚性板可以提供一导电表面。一刚性板可以是由一种导电材料所做成的。然而，一导电的涂层可被喷涂或是擦涂在一刚性板或是挠性的片上。在图3B的例子中，如同在以下以额外的细节叙述的，导电表面130可以具有孔洞137，以用于容许引线接合线131中的界定一屏蔽区域133的至少某些个的上方的部分能够延伸穿过上表面130。
图4是描绘一具有EMI屏蔽的范例的SiP 100的侧视横截面方块图。SiP 100可包含一封装基板19，其具有耦接至其之一上表面132的一或多个主动微电子装置11、一或多个被动微电子装置12、以及引线接合线131，其中此种引线接合线131的上末端可以耦接至一导电表面130。即使是描述SiP 100，但是其它类型的具有免于EMI的保护的微电子封装亦可被使用。
封装基板19具有上表面132以及与该上表面相对的下表面149。封装基板19可以具有位在表面132及149之间的接地面140以及互连接至此种接地面以用于导电的贯孔142。
引线接合线131可以利用贯孔142来耦接至接地面140。某些引线接合线131可以利用用于导电的球体接合141来机械式地耦接至上表面132；然而，在其它实施方式中，其它类型的接合亦可被使用。再者，并非所有的引线接合线131都需要耦接至接地面140。某些引线接合线131可被使用于在SiP 100之内载有供应电压或信号。某些引线接合线131可被使用于耦接至在SiP 100之内的其它装置。然而，以下的说明的大部分大致上是有关于和法拉第笼153相关的引线接合线131。以此种方式，引线接合线131可以耦接至一或多个接地面，以用于传导干扰至所述接地面。
主动或被动的微电子装置145可以耦接至封装基板19的上表面132。微电子装置145可包含主动集成电路晶粒及/或被动构件。被动构件可以是电容器、电感器、或是电阻器、或是其的任意组合。
微电子装置145可以利用如先前所述的球体或凸块互连及/或引线接合线来耦接至封装基板19。再者，微电子装置145可以利用粘着剂或是底胶填充层(未显示)来耦接至上表面132。
微电子装置145可被设置在例如是利用密封剂或是模制材料的介电保护材料143中，以用于至少覆盖微电子装置145的上表面以及侧壁。引线接合线131可被设置在微电子装置145的侧壁的周围。
导电表面130可以是位在介电保护材料143的顶端或上表面146之上、或是耦接至介电保护材料143的顶端或上表面146。然而，在另一实施方式中，如同在以下以额外的细节叙述的，介电保护材料143的顶表面可以是位在高于引线接合线131的尖端148的高度处。导电表面130可被设置在和法拉第笼153相关的引线接合线131之上。此种引线接合线131的上末端或尖端148可以机械式地耦接至导电表面130。此耦接可以是利用热压接合或是其它形式的机械式耦接。
法拉第笼153可以是接地面140的一部分例如利用贯孔142来互连接至支撑导电表面130的引线接合线131的组合。在另一实施方式中，在导电表面130与引线接合线131的某些个尖端148之间可以有一间隙144。以此种方式，导电表面130的底部，例如是导电板的底部例如可以附接至、或是安置在介电保护材料143的顶表面之上，因而介电保护材料143的高度可以是大于引线接合线131的高度。
因此，导电表面130可被设置在引线接合线131的一部分之上，其中引线接合线131的上末端或尖端148是和导电表面130间隔开。然而，一种具有间隙144的配置可能会提供较不有效的法拉第笼153，因而为了例如且非限制性的清楚的目的起见，应假设是没有间隙的。
耦接至接地面140而从封装基板19的上表面132向上突出或延伸离开的引线接合线131可加以排列。以此种方式，即使引线接合线131的一种Bond ViaArrayTM或是BVATM配置136的单一列与行在一实施方式中可以存在，但是一种BVATM配置136的多个列及/或多个行的引线接合线131可以沿着屏蔽区域133的一或多个侧边而存在。
为了重述要点，引线接合线131中的某些例如是在界定屏蔽区域133的BVA配置136中的引线接合线131可被设置，以提供此种避免EMI或相关EMI的屏蔽区域133给微电子装置145。引线接合线131的其它位在屏蔽区域133之外的部分可能并未被使用于EMI屏蔽。再者，一或多个其它主动或被动微电子装置11及/或12可以耦接至基板19，并且是位在屏蔽区域133之外，因而不是此种屏蔽区域的部分、或是用于此种屏蔽区域的位置。
图5是描绘一范例的SiP 100的侧视横截面方块图，其具有一导电罩盖150，并且在导电罩盖150之下的EMI屏蔽区域中具有信号引线接合线131s。图5的SiP 100是与图4的SiP100相同的，但是具有以下的差异。
在此例子中，引线接合线131的一部分具有一高度，其大于引线接合线131的另一部分的高度。两组的引线接合线131都可以接近微电子装置145而且在微电子装置145的周围来加以设置。然而，引线接合线131的较高的部分可以是用于提供相关EMI的屏蔽区域133给微电子装置145。然而，引线接合线131的其它较矮的部分("引线接合线131s")可以是耦接微电子装置145至封装基板19的导体的信号线。此种较矮的引线接合线131s可以是在法拉第笼153之内。较高的引线接合线131的高度可被限制为低轮廓的封装应用。
导电罩盖150可以耦接至封装基板19的上表面132。导电罩盖150可以覆盖SiP 100的耦接至上表面132的构件，其包含微电子装置145、微电子装置11、12以及引线接合线131。并非BVA配置136的部分之引线接合线131可以将导电罩盖150以及接地面140互连。此耦接可被使用以降低内部的杂讯。然而，法拉第笼153可以是位在覆盖150之下，以用于内部的EMI屏蔽。选配的是，导电表面130可被省略，而有利于利用导电罩盖作为法拉第笼153的一上方的导电表面，而不论在尖端148与导电罩盖150的底面之间具有或是不具有间隙144。
某些在BVA配置136之内的引线接合线131可以是信号线，亦即引线接合线131s。引线接合线131s可以不耦接至接地面140，而是可以耦接至封装基板19的线路(未显示)。引线接合线131s的尖端可以在介电保护材料143的使用之前，先被接合或是焊接至微电子装置145。在另一实施方式中，相关微电子装置145的介电保护材料143可被省略。
引线接合线131s可被接合到被动微电子装置12或是主动微电子装置11中的一或多个的上表面。这些引线接合线131s可以是用于在SiP 100之内的互连。
图6是描绘一范例的SiP 100的侧视横截面方块图，其是具有利用一上方的基板169的EMI屏蔽。图6的SiP 100是与图5的SiP 100相同的，但是并不具有导电罩盖150，而且具有以下的差异。
除了贯孔162之外，上方的基板169可包含接地面160。引线接合线131的尖端或是上末端148可以沿着上方的基板169的底表面，利用互连161(例如是利用微球体或微凸块)来互连接至贯孔162，例如以用于耦接至接地面160。互连161可被设置在介电保护材料143的上表面168上。接地面160可以提供法拉第笼153的上方的导电表面130。
另一不论是主动或被动的微电子装置165可以耦接至上方的基板169的顶表面。微电子装置165可以利用引线接合线15来耦接至基板169的贯孔或线路。然而，微球体或是微凸块可以在另一实施方式中被使用。微电子装置165可以耦接在法拉第笼153之外。
图7是描绘在法拉第笼153的上方的导电表面130的加入之前的SiP 100的范例的部分的俯视方块图。焊垫170可以接近微电子装置145而且在微电子装置145的周围来加以设置，以用于将引线接合线131分别耦接至焊垫170，以用于提供法拉第笼153的屏蔽区域133。屏蔽区域133可被界定在BVA配置136之内。
焊垫170可以在介电保护材料143的侧边周围和彼此间隔开。在介电保护材料143中的微电子装置145可以是位在屏蔽区域133的中央部分中。焊垫170的垫至垫的间距171可以是等于或小于约250微米。焊垫170的间距171可以针对于和例如是EMI及/或RFI的干扰相关的频率来加以选择，以将微电子装置145与EMI及/或RFI屏蔽开。再者，微电子装置145可能是干扰的辐射体，并且因而此种屏蔽可以是用以保护SiP 100的其它构件免于由微电子装置145所产生的干扰。
即使单一列与行的焊垫170是说明性地被描绘，但是在另一实施方式中可以有超过一或两个列及/或行。再者，焊垫170的列及/或行可以相关彼此来交错的，以提供较稠密的屏蔽。引线接合线131可以有效地被用来提供一低通滤波器的法拉第笼，以用于降低相关微电子装置145的操作的EMI。以此种方式，尽管并非必要的，但焊垫170的设置以及因此的引线接合线131的设置可以是一致的。引线接合线131可以针对于被调适以屏蔽往微电子装置145、或是来自微电子装置145的特定范围的频率密度来加以置放及/或调整。
图8是描绘在一法拉第笼153的上方的导电表面130的加入之前的另一SiP100的范例的部分的俯视方块图。在此例子中，引线接合线131的BVA配置136的两个列以及两个行是被用来界定一屏蔽区域133。在此例子中，在列与行之间的间隔是交错的，以提供较稠密的引线接合线131的样式。
在此例子中，BVA配置136的引线接合线131中的某些个是用于载有信号，亦即引线接合线131s。以此种方式，互连180可被形成以用于从微电子装置145延伸到介电保护材料143之外，以用于与信号引线接合线131s的互连。
图9A是描绘具有EMI屏蔽的堆叠式封装的("PoP")装置190的范例的部分的侧视横截面方块图。PoP装置190可包含上方的SiP 100U，其堆叠在下方的SiP 100L的顶端上。PoP装置190例如可包含一或多个在屏蔽区域之外的其它微电子装置以及其它的细节，例如是先前参考图3A至8所述。于是，为了清楚且非限制性的目的起见，先前针对于SiP 100所叙述的细节并未在以下加以叙述。
下方的SiP 100L的下方的封装基板19L可包含下方的接地面140L，其使得下方的引线接合线131L从下方的封装基板19L的上表面向上地延伸。此种下方的引线接合线131L及接地面140L可以例如是利用如先前所述的贯孔及球体接合来互连接至彼此，以用于形成法拉第笼153的下方的部分。下方的引线接合线131L的尖端148可以沿着上方的封装基板19U的下方侧，利用互连191而被接合或耦接至针对其的垫及贯孔。
选配的是，上方的封装基板19U可包含上方的接地面140U，以用于形成法拉第笼153来作为两个法拉第笼的堆叠，亦即上方的法拉第笼192U以及下方的法拉第笼192L。法拉第笼192U及192L的每一个都可包含分别耦接至封装基板19U及19L的上表面之个别的封装的微电子装置145U及145L。
上方的基板19U的上方的接地面140U可以是位在下方的微电子装置145L之上，因而下方的引线接合线131L的尖端或上末端148可以沿着上方的封装基板19U的底表面，利用互连191来互连接至垫或接点以用于电耦接至上方的接地面140U。上方的引线接合线131U以及选配的接地面140U可以例如利用如先前所述的贯孔以及球体接合来互连接至彼此，以用于形成法拉第笼153的上方部分。上方的引线接合线131U的尖端148可被接合或是耦接至导电表面130，以用于完成此种上方的法拉第笼192U。
在另一实施方式中，上方的基板封装19U的贯孔可以在不连接至上方的接地面140U之下，互连下方的引线接合线131L以及上方的引线接合线131U，以形成用于两个微电子装置145U、145L的"两个楼层的"或是两层的法拉第笼153。即使只有两层是说明性地被描绘，但是超过两层亦可被使用在其它的实施方式中。
图9B是描绘另一具有EMI屏蔽的PoP装置190的范例的部分的侧视横截面方块图。PoP装置190例如可包含一或多个在屏蔽区域之外的其它的微电子装置以及其它细节，例如是先前参考图3A至9A所述者。于是，为了清楚且非限制性的目的起见，先前针对于SiP 100所叙述的细节并未在以下加以叙述。
除了以下的差异之外，图9B的PoP装置190可以是与图9A的PoP装置190相同的。图9B的PoP装置190可包含信号引线接合线131s。信号引线接合线131s可以是位在法拉第笼153之内，其是包含在法拉第笼192U之内。
在此配置中的信号引线接合线131s可以从下方的微电子装置145L的上表面向上地延伸。从下方的微电子装置145L的上表面延伸之引线接合线131s的尖端或上末端148可以例如是利用互连191而互连接至上方的封装基板19U的下面侧。贯孔及/或线路(未显示)可以利用信号引线接合线131s来电耦接上方及下方的微电子装置145。再者，下方的基板封装19L可包含用于与下方的微电子装置145互连的贯孔及/或线路(未显示)。
图10是描绘另一具有EMI屏蔽的SiP 100的范例的部分的侧视横截面方块图。SiP100例如可包含一或多个在屏蔽区域之外的其它的微电子装置以及其它细节，例如是先前参考图3A至9B所述者。于是，为了清楚且非限制性的目的起见，先前针对于SiP 100所叙述的细节并未在以下加以叙述。
在此例子中，引线接合线131以及例如是IC晶粒的微电子装置145是被介电保护材料143所保护。微电子装置145可以在沉积或是注入介电保护材料143之前，利用微凸块互连17来互连至封装基板19的上表面。同样地，在沉积或是注入介电保护材料143之前，引线接合线131可以被球体接合到封装基板19的上表面。
选配的是，信号引线接合线131s可以在沉积或是注入介电保护材料143之前，被球体接合到微电子装置145的上表面201。信号引线接合线131s因此可以是在法拉第笼153的屏蔽区域133之内。
引线接合线131的尖端或上末端148以及选配的信号引线接合线131s可以延伸在介电保护材料143的上表面202之上。焊料球体或是其它的互连共晶体204可加以沉积到尖端148之上，以用于例如是在此的别处所描述的后续的互连。
不具有干扰屏蔽的垂直的整合
图11A是描绘不具有引线接合线EMI屏蔽的SiP 100的范例的部分的侧视横截面方块图。图11B是描绘可包含或者可以不包含EMI屏蔽的SiP 100的范例的部分的侧视横截面方块图。同时参考图11A及11B，分别说明性地描绘在那些图中的SiP 100是进一步加以叙述。SiP 100的每一个都可以包含一或多个其它微电子装置以及其它细节，例如是先前所叙述。于是，为了清楚且非限制性的目的起见，先前针对于SiP 100所叙述的细节并未在以下加以叙述。
SiP 100的每一个是包含垂直整合的微电子封装200。微电子封装200的每一个是包含基板19，其是具有上表面132以及与该上表面相对的下表面149。封装基板19可以具有位在表面132及149之间的接地面140、以及互连接至此种接地面以用于导电的贯孔142，然而此并不是一项要件。
微电子装置145可以耦接至基板19的上表面132，其中微电子装置是主动或是被动微电子装置。以此种方式，在SiP 100中，可以有被动或是主动微电子装置中的任一种或是两者的一或多个耦接至上表面132。该些主动或被动装置可被实施在半导体晶片上、或是可被实施为离散的构件，例如是独立的电容器、电阻器、电感器、天线、感测器、等等。若被实施在一种半导体材料中、或是在一种半导体材料上，则该构件可以用面向上或是面向下的配置来加以连接，并且亦可以具有一或多个耦接该构件的相对的侧边之穿过半导体的贯孔(TSV)。根据此实施方式，此种主动或是被动微电子装置的上表面在过去对于垂直的整合而言可能已经变成是未使用的，现在则包含接合被附接至此种微电子装置的此种上表面的引线接合线，以用于连接至其它的被动或是主动构件。
更具体而言，引线接合线131可以耦接至基板19的上表面132并且从该上表面132延伸离开，并且引线接合线231可以耦接至微电子装置145的一上表面201并且从该上表面201延伸离开。引线接合线131及231分别可以利用用于导电的球体接合141来机械式地耦接至上表面132及201。然而，在其它实施方式中，其它类型的接合亦可被使用。引线接合线231是在长度上比引线接合线131短的。
参考图11A，引线接合线131可以具有整体完成后的长度261，并且引线接合线231可以具有整体完成后的长度262。然而，引线接合线131及231的完成后的高度可以是大致相同的，以用于使得上末端148延伸在模制层143的上表面202之上。
上末端148可以为了大致是共面的而为毗连的。焊料球体或是其它的互连共晶体204可以在上表面202上，而分别加以沉积在上末端148之上，以用于与在主动或被动微电子装置11或12的正面的底面上的垫(未显示)形成互连。
根据一实施方式，微电子装置145可以耦接至封装基板19的上表面132。微电子装置145可包含导电线路，并且可以只包含被动构件。若被实施为被动构件，则微电子装置145可以代表电容器、电感器、或是电阻器、或是其的任意组合。若被实施为主动构件，则微电子装置145可以代表例如是具有电晶体的晶粒，但是额外或替代地可以在该主动构件上、或是在该主动构件中包含其它的主动或被动装置。
如同先前所述的，微电子装置145可以利用球体或凸块互连及/或引线接合线来耦接至封装基板19。再者，微电子装置145可以利用粘着剂或是底胶填充层(未显示)来耦接至上表面132。
在所展示的实施方式中，微电子装置145以及微电子装置11或12是使得朝向是面向下的，亦即朝向基板19的上表面132之面朝下的朝向。然而，在另一实施方式中，微电子装置11或12可以额外或是替代地在从基板19的上表面132面向上的正面的侧面上具有电路。
微电子装置11或12可以被耦接在模制层143的最上面的表面202之上。在一实施方式中，微电子装置11或12可以利用共晶体204或是其它机械式互连来耦接至引线接合线131及231的上末端148。微电子装置11或12可以是位在微电子装置145之上，并且可以完全地重叠微电子装置145、至少部分地重叠此种微电子装置145、或是可以完全不重叠微电子装置145。
模制层143可以具有最上面的表面202以及与该最上面的表面相对的最下面的表面252。模制层143可被设置以用于围绕引线接合线131及231两者的长度261及262的部分。上末端148例如可以像是藉由用于注入模制的模制辅助膜的使用而不被模制层143所覆盖。在另一实施方式中，模制层143可以暂时完全覆盖长度261及262，接着是回蚀以露出上末端148。
在垂直整合的微电子封装200的一实施方式中，微电子装置145可被设置在模制层143中。以此种方式，在一实施方式中，微电子装置145可以完全位在模制层143的最上面的表面202与最下面的表面252之间。引线接合线131可被设置在微电子装置145的侧壁203的周围，尽管在此范例实施方式中并非是用于干扰的屏蔽。
引线接合线131可以耦接至接地面140，以用于从封装基板19的上表面132向上地突出或延伸，并且可加以排列。以此种方式，尽管引线接合线131及/或231的BVATM配置的单一列与行在一实施方式中可以存在，但是多个列及/或多个行的此种引线接合线亦可以是在BVATM配置中。
在垂直整合的微电子封装200的一实施方式中，被实施为被动微电子装置的微电子装置12可被使用。然而，在垂直整合的微电子封装200的另一实施方式中，微电子装置11可被实施为主动微电子装置。
参考图11B，内部的引线接合线131i可以具有整体完成后的长度263，并且引线接合线231可以具有整体完成后的长度264。如同先前参考图11A所述的，外部的引线接合线131o可以具有整体完成后的高度261。引线接合线131i及231在形成之后的完成后的高度可以是大致相同的，以用于使得上末端148大致与彼此为高低相同的。
引线接合线131i及231的上末端148可以是为了大致是共面的而为毗连的。焊料球体或是其它的互连共晶体274分别可以将主动或被动微电子装置271的下表面耦接至引线接合线131i及231的上末端148，以用于与在主动或被动微电子装置271的正面的底面上的垫(未显示)形成互连。在微电子装置271处于适当的地方下，模制材料可被注入以形成模制材料层143，并且因此微电子装置271的下表面可以接触到模制层143的模制材料。为了模制，模制辅助膜可被用来容许外部的引线接合线131o的尖端148、以及微电子装置271的垫或是其它互连(未显示)，能够延伸在模制层143的上表面202之上。在另一实施方式中，模制层143可以暂时完全地覆盖长度261，接着是回蚀以露出其的上末端148。
微电子装置271可以耦接至微电子装置145而且位在微电子装置145之上，并且可以至少部分地重叠微电子装置145。以此种方式，微电子装置271可以横向地延伸在微电子装置271的周边之外，以用于内部的引线接合线131i在基板19的上表面132与微电子装置271的面对此种上表面132的下表面之间的互连。引线接合线131i以及引线接合线131o可被设置在微电子装置145的侧壁203的周围，尽管在此范例实施方式中并非用于干扰的屏蔽。
同样地，被动微电子装置145可以耦接至封装基板19的上表面132。微电子装置145可包含导电线路，并且可以只包含被动构件。被动构件可以是电容器、电感器、或是电阻器、或是其的任意组合。如先前所述，微电子装置145可以利用球体或是凸块互连及/或引线接合线来耦接至封装基板19。再者，微电子装置145可以利用粘着剂或是底胶填充层(未显示)来耦接至上表面132。若该微电子装置是离散的被动构件，则该导线231可被形成在例如是焊料垫的焊料部分上、或是在铜、镍、金、或合金垫上。
模制层143可以具有最上面的表面202以及与该最上面的表面相对的最下面的表面252。模制层143可被设置以用于围绕引线接合线131o的长度261的部分，并且用于围绕引线接合线131i及231两者的长度263及264。
在垂直整合的微电子封装200的实施方式中，微电子装置145可被设置在模制层143中，并且完全位在模制层143的最上面的表面202与最下面的表面252之间。微电子装置271可被设置在模制层143中，并且至少部分地位在模制层143的最上面的表面202与最下面的表面252之间。微电子装置11或12可以被耦接在模制层143的最上面的表面202之上。
对于被动微电子装置271而言，微电子装置271可包含导电线路，并且可以只包含被动构件。微电子装置271可包含RDL。被动构件可以是电容器、电感器、或是电阻器、或是其之任意组合。在此实施方式中，微电子装置145及271、以及微电子装置11或12是具有面向下的朝向，亦即朝向基板19的上表面132之面朝下的朝向。然而，在另一实施方式中，微电子装置11或12及/或微电子装置271可以具有从基板19的上表面132面向上的正面的侧面。
在垂直整合的微电子封装200的一实施方式中，被动微电子装置的微电子装置12可被使用。然而，在垂直整合的微电子封装200的另一实施方式中，主动微电子装置的微电子装置11可被使用。微电子装置11或12可以耦接在模制层143的最上面的表面202之上，以用于与微电子装置271的互连。在一实施方式中，微电子装置11或12可以利用用于导电的共晶体204或是其它的机械式互连来耦接至微电子装置271的上表面。
微电子装置11或12可以是位在微电子装置271之上，并且至少部分地重叠此种微电子装置271。以此种方式，微电子装置11或12可以耦接在模制层143的最上面的表面202之上，以用于与外部的引线接合线131o的上末端148的互连、以及与微电子装置271的上表面的互连。
引线接合线131i及131o可以耦接至接地面140，以用于从封装基板19的上表面132向上地突出或延伸，并且可加以排列。以此种方式，即使引线接合线131i、131o及/或231的BVATM配置的单一列与行在一实施方式中可以存在，但是多个列及/或多个行的此种引线接合线可以是在BVATM配置中。
图12A是描绘另一不具有引线接合线EMI屏蔽的SiP 100的一范例的部分的侧视横截面方块图。除了以下的细节之外，图12A的SiP 100可以是与在图11A中的相同。在垂直整合的微电子封装200的此实施方式中，微电子装置12是悬臂伸出，以用于横向地延伸超过引线接合线131并且在其之上。以此种方式，引线接合线131的上末端148可以利用共晶体204来互连至微电子装置11或12的下表面。
图12B是描绘另一不具有引线接合线EMI屏蔽的SiP 100的范例的部分的侧视横截面方块图。除了以下的细节之外，图12B的SiP 100可以是与在图11B中的相同。在垂直整合的微电子封装200的此实施方式中，微电子装置12并未悬臂伸出以用于横向地延伸超过引线接合线131o并且在其之上。以此种方式，微电子装置11或12以及微电子装置271对于其分别的下表面以及上表面可以具有大致相等的表面积。
图12C是描绘另一不具有引线接合线EMI屏蔽的SiP 100的范例的部分的侧视横截面方块图。除了以下的细节之外，图12C的SiP 100可以是与在图12A中的相同。在垂直整合的微电子封装200的此实施方式中，微电子装置12是悬臂伸出以用于在微电子装置145的右侧以及左侧上横向地延伸超过引线接合线131并且在其之上。以此种方式，引线接合线131的上末端148可以利用共晶体204来互连至微电子装置11或12的下表面。于是，应该体认到的是，被设置在微电子装置的周围并且互连接至微电子装置11或12的引线接合线131可被使用于扇出。
图12D是描绘另一不具有引线接合线EMI屏蔽的SiP 100的一范例的部分的侧视横截面方块图。除了以下的细节之外，图12D的SiP 100可以是与在图12B中的相同。在垂直整合的微电子封装200的此实施方式中，微电子装置12是并未悬臂伸出以用于横向地延伸超过引线接合线131o并且在其之上。以此种方式，微电子装置11或12以及微电子装置271对于其分别的下表面以及上表面可以具有大致相等的表面积。以此种方式，引线接合线131i的上末端148可以利用共晶体274来互连至微电子装置271的下表面。于是，应该体认到的是，被设置在微电子装置145的周围并且互连接至微电子装置271的引线接合线131i可被使用于扇出。
图13A是描绘不具有EMI屏蔽而具有垂直整合的微电子封装200的范例的SiP 100的侧视横截面方块图。在此实施方式中，垂直整合的微电子封装200可以是耦接至基板19的独立的封装，即如同在图12D中的SiP 100。由于SiP 100的构件先前已经例如是参考图4来加以叙述，因而此种说明并未予以重复。
在此实施方式中，共晶体274是被形成在模制层143的上表面202上。共晶体274是将引线接合线131i及231的上末端148互连至微电子装置271的下表面，该些引线接合线除了其之下方及上末端之外，可被封入在模制层143中。在此例子中，微电子装置271的下表面并未接触模制层143的上表面202。
再者，在此范例实施方式中，除了此种信号引线接合线131s的下表面之外，信号引线接合线131s可被封入在模制层143的模制材料中。信号引线接合线131s可以是短于内部的引线接合线131i，并且可以是如先前所述的用于与微电子装置145的互连。以此种方式，微电子装置271可以耦接至例如是引线接合线131i之被耦接到上表面132的引线接合线131的较高的部分的上末端148。微电子装置271可以进一步耦接至引线接合线231的上末端148。例如是先前所叙述的，引线接合线131的另一耦接至上表面132的部分(例如是信号引线接合线131s)可以使得其之上末端148耦接至微电子装置145的上表面。
选配的是，引线接合线331可以耦接至直接被耦接到基板19的上表面132的主动微电子装置11及/或被动微电子装置12的一或多个上表面。
有关图13A的SiP 100的其它细节先前已经加以叙述，并且因此为了清楚且非限制性的目的起见而未予以重复。
图13B是描绘不具有EMI屏蔽而具有垂直整合的微电子封装200的范例的SiP 100的侧视横截面方块图。在此实施方式中，如同在图13A中的SiP 100，垂直整合的微电子封装200可以是耦接至基板19之独立的封装。由于SiP 100的构件先前已经例如参考图4来加以叙述，因而此种说明并不予以重复。
除了以下的差异之外，图13B的SiP 100是类似于图13A的SiP 100。在图13B的SiP100中，垂直整合的微电子封装200是省略微电子装置271。因此，例如是先前叙述的，微电子装置11及/或12可以利用共晶体204来直接耦接至模制层143的上表面202。
图13C是描绘不具有EMI屏蔽而具有垂直整合的微电子封装200的范例的SiP 100的侧视横截面方块图。在此实施方式中，如同在图13A中的SiP 100，垂直整合的微电子封装200可以是耦接至基板19的独立的封装。由于SiP 100的构件先前已经例如参考图4来加以叙述，因而此种说明并不予以重复。
除了以下的差异之外，图13C的SiP 100是类似于图13A的SiP 100。在图13C的SiP100中，垂直整合的微电子封装200是具有某些如先前所述的被封入在模制层143的模制材料中的引线接合线131i，并且具有某些并未被封入在模制层143的模制材料中的引线接合线131i。
图13D是描绘不具有EMI屏蔽而具有垂直整合的微电子封装200的范例的SiP 100的侧视横截面方块图。在此实施方式中，如同在图13B中的SiP 100，垂直整合的微电子封装200可以是耦接至基板19的独立的封装。由于SiP 100的构件先前已经例如参考图4来加以叙述，因而此种说明并不予以重复。
除了以下的差异之外，图13D的SiP 100是类似于图13B的SiP 100。在图13D的SiP100中，垂直整合的微电子封装200并不具有被封入在模制层143的模制材料中的引线接合线131。
这些是用于SiP 100的垂直整合的微电子封装200的各种实施方式中的一些实施方式。然而，这些或其它的实施方式亦可以根据在此的说明来加以提供。
以此种方式，尽管前述内容是描述根据本发明的一或多个特点的范例实施例，但是根据本发明的该一或多个特点的其它及进一步的实施例可以在不脱离本发明的范畴下而被设计出，该范畴是藉由以下的申请专利范围以及其等同物来加以决定。申请专利范围所列的步骤并不意指该些步骤的任何顺序。商标则是其个别的拥有者的财产权。

Claims (20)

1.一种用于具有免于干扰的保护的微电子封装的设备，其是包括：
基板，其是具有上表面以及与该上表面相对的下表面，并且具有一接地面；
第一微电子装置，其是耦接至该基板的该上表面；
引线接合线，其是耦接至该接地面以用于传导该干扰至该接地面，并且从该基板的该上表面延伸离开；
所述引线接合线的第一部分是被设置以提供用于该第一微电子装置的相关该干扰的屏蔽区域；
所述引线接合线的第二部分并未被设置以提供该屏蔽区域；
第二微电子装置，其是耦接至该基板，并且位在该屏蔽区域之外；以及
导电表面，其是在所述引线接合线的该第一部分之上，以用于覆盖该屏蔽区域。
2.根据权利要求1的设备，其中该导电表面是被设置在所述引线接合线的该第一部分之上，其中所述引线接合线的上末端是机械式地耦接至该导电表面。
3.根据权利要求2的设备，其中该第一微电子装置是包含集成电路晶粒。
4.根据权利要求2的设备，其中该第一微电子装置是包含被动构件。
5.根据权利要求4的设备，其中该被动构件是从由电容器、电感器、以及电阻器所构成的群组中被选出。
6.根据权利要求1的设备，其中该接地面、该导电表面、以及所述引线接合线的该第一部分的互连组合是提供法拉第笼。
7.根据权利要求1的设备，其进一步包括耦接至该基板的该上表面的导电罩盖，该导电罩盖是覆盖该第一微电子装置、该第二微电子装置、该导电表面、以及所述引线接合线。
8.根据权利要求1的设备，其进一步包括：
接近该第一微电子装置而且在该第一微电子装置的周围而被设置在该基板的该上表面上的焊垫，以用于将所述引线接合线的该第一部分耦接至所述焊垫以用于该屏蔽区域；以及
所述焊垫是具有等于或小于250微米的垫至垫的间距。
9.根据权利要求1的设备，其中该基板以及该接地面分别是第一基板以及第一接地面，该设备进一步包括：
第二基板，其是具有第二接地面；
所述引线接合线的该第一部分的上末端是耦接至该第二基板的底表面，以用于耦接至该第二接地面；以及
第三微电子装置，其是耦接至该第二基板的顶表面。
10.一种用于具有免于干扰的保护的微电子封装的设备，其是包括：
基板，其是具有上表面以及与该上表面相对的下表面，并且具有接地面；
微电子装置，其是耦接至该基板的该上表面；
引线接合线，其是被接合到该基板的该上表面，并且从该基板的该上表面延伸离开；
所述引线接合线的第一部分是具有第一高度，并且接近而且在该微电子装置的周围而被设置以用于提供相关该干扰的屏蔽区域给该微电子装置，所述引线接合线的该第一部分是耦接至该接地面以用于传导该干扰至该接地面；
所述引线接合线的第二部分是具有小于该第一高度的第二高度，并且接近而且在该微电子装置的周围而被设置，所述引线接合线的该第二部分是包含用于电耦接该微电子装置与该基板的信号线；
导电表面，其是在所述引线接合线之上以用于覆盖该屏蔽区域；以及
所述引线接合线的该第一部分的上末端是机械式地耦接至该导电表面。
11.根据权利要求10的设备，其中该微电子装置是第一微电子装置，该设备进一步包括第二微电子装置，其是耦接至该基板并且位在该屏蔽区域之外。
12.根据权利要求10的设备，其进一步包括：
接近而且在该微电子装置的周围而被设置在该基板的该上表面上的焊垫，以用于耦接所述引线接合线至所述焊垫；以及
所述焊垫是具有等于或小于250微米的垫至垫的间距。
13.根据权利要求10的设备，其中该基板、该接地面以及该微电子装置分别是第一基板、第一接地面以及第一微电子装置，该设备进一步包括：
第二基板，其是位在该第一微电子装置之上并且具有第二接地面以作为该导电表面，该第二基板是位在所述引线接合线的上末端之上；以及
第二微电子装置，其是耦接至该第二基板的顶表面。
14.根据权利要求10的设备，其中该接地面、该导电表面、以及所述引线接合线的该第一部分的互连组合是提供法拉第笼。
15.一种用于具有免于干扰的保护的微电子封装的设备，其是包括：
基板，其是具有上表面以及与该上表面相对的下表面，并且具有接地面；
第一微电子装置，其是耦接至该基板的该上表面；
引线接合线的下末端，其是耦接至该接地面以用于传导该干扰至该接地面；
所述引线接合线的第一部分是被设置以提供用于该第一微电子装置的相关该干扰的屏蔽区域；
所述引线接合线的第二部分并未被设置以提供该屏蔽区域；
第二微电子装置，其是耦接至该基板并且位在该屏蔽区域之外；以及
导电表面，其是具有所述引线接合线的该第一部分耦接至该导电表面，该导电表面是覆盖该屏蔽区域并且界定该屏蔽区域，其中所述引线接合线的该第一部分是从该导电表面延伸离开。
16.根据权利要求15的设备，其进一步包括：
接近该第一微电子装置而且在该第一微电子装置的周围而被设置在该基板的该上表面上的焊垫，以用于耦接所述引线接合线的所述下末端至所述焊垫，以用于提供相关该干扰的该屏蔽区域给该微电子装置；以及
所述焊垫是具有等于或小于250微米的垫至垫的间距。
17.根据权利要求15的设备，其中该接地面、该导电表面、以及所述引线接合线的该第一部分的互连组合是提供法拉第笼。
18.根据权利要求15的设备，其中该基板以及该接地面分别是第一基板以及第一接地面，该设备进一步包括：
第二基板，其是具有第二接地面；
所述引线接合线的该第一部分的球体接合，其是耦接至该第二基板的底表面，以用于耦接至该第二接地面以作为该导电表面；以及
第三微电子装置，其是耦接至该第二基板的顶表面。
19.根据权利要求15的设备，其中该第一微电子装置是包含集成电路晶粒。
20.根据权利要求15的设备，其中该第一微电子装置是包含被动构件。
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