WO2022147429A1 - Structures with through-substrate vias and methods for forming the same - Google Patents

Structures with through-substrate vias and methods for forming the same Download PDF

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Publication number
WO2022147429A1
WO2022147429A1 PCT/US2021/073122 US2021073122W WO2022147429A1 WO 2022147429 A1 WO2022147429 A1 WO 2022147429A1 US 2021073122 W US2021073122 W US 2021073122W WO 2022147429 A1 WO2022147429 A1 WO 2022147429A1
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WIPO (PCT)
Prior art keywords
conductive via
via portion
dielectric layer
barrier layer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2021/073122
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English (en)
French (fr)
Inventor
Gaius Gillman Fountain, Jr.
Cyprian Emeka Uzoh
George Carlton Hudson
John Posthill
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Adeia Semiconductor Bonding Technologies Inc
Original Assignee
Invensas Bonding Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Invensas Bonding Technologies Inc filed Critical Invensas Bonding Technologies Inc
Priority to JP2023539267A priority Critical patent/JP2024501016A/ja
Priority to CN202180092102.9A priority patent/CN116830256A/zh
Priority to EP21916596.6A priority patent/EP4268273A4/en
Priority to KR1020237025992A priority patent/KR20230125309A/ko
Publication of WO2022147429A1 publication Critical patent/WO2022147429A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
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    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
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    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
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    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
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    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
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    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
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    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
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    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
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    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H10W20/4424—Copper alloys
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    • H10W72/01904—Manufacture or treatment of bond pads using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
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    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9226—Bond pads being integral with underlying chip-level interconnections with via interconnections
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    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
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    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Definitions

  • the field relates to structures with through-substrate vias and methods for forming the same.
  • a semiconductor element such as integrated device dies or chips, may be mounted or stacked on other elements.
  • a semiconductor element can be mounted to a carrier, such as a package substrate, an interposer, a reconstituted wafer or element, or other semiconductor element.
  • a semiconductor element can be stacked on top of another semiconductor element, e.g., a first integrated device die can be stacked on a second integrated device die.
  • a through-substrate via can extend vertically through a thickness of the semiconductor element to transfer electrical signals through the semiconductor element, e.g., from a first surface of the semiconductor element to a second opposing surface of the semiconductor element.
  • FIG. 1A-1F show conventional processing steps for forming TSVs in an element.
  • Figure 2 shows an etch depth map of a processed wafer.
  • Figures 3A and 3B are example wafer maps of etched wafers.
  • Figures 4A-4I illustrate a method for forming a microelectronic structure, according to various embodiments.
  • Figures 5A-I illustrate a method for forming a microelectronic structure, according to various embodiments.
  • Figures 6A-6H illustrate a method for forming a microelectronic structure, according to various embodiments.
  • FIGS 1A-F illustrate various conventional processing steps for forming TSVs in a microelectronic structure.
  • the formation of TSVs can be performed using via-middle or front side via-last processing methods. Both of these methods are high volume manufacturing processes for different dies, including e.g. 40 um thick dies. Both of these processes involve etching through the TSVs into the bulk silicon after integrated circuit fabrication.
  • Technical challenges of these processes increase with a reduction in the die thickness. These challenges can include TSV etch uniformity, die thickness uniformity, and the overall quality of the backside dielectric layer that is formed.
  • the microelectronic structure comprises a portion of a semiconductor wafer 102.
  • the illustrated via structures comprise via-middle structures in which active circuitry 106, e.g., transistors or other active circuit elements, can be formed on or in the active surface of a bulk semiconductor portion 102, one or more insulating layers 112 and 113 can be formed over the active circuitry 106, and an opening 104 for the TSV can be formed through the one or more insulating layers 112 and 113 and a portion of the bulk semiconductor portion 102.
  • a metallization layer 110 for instance a back-end-of line (BEOL) or redistribution layer (RDL), can be provided over or within one or more insulating layers.
  • BEOL back-end-of line
  • RDL redistribution layer
  • a via structure 108 can be provided.
  • the via structure 108 can extend into the opening and over insulating layers 112 and 113.
  • a conductive pad 114 can be provided over one or more of the insulating layers and electrically connected to the metallization layer 110.
  • Conductive overburden from electroplating the via structure 108 in Figure IB can be removed (e.g., polished away) in Figure 1C.
  • a conductive pad 117 can be provided over the one or more insulating layers 112 and 113 and electrically connected to the via structure 108.
  • the conductive pad 117 can also be configured to electrically connect to another element.
  • the conductive pad 117 can be part of a BEOL or RDL.
  • a frontside of the microelectronic structure 114 can be attached to a carrier 120 by way of an adhesive 118.
  • the carrier 120 can comprise a temporary handle wafer that is used to support the microelectronic structure 114 during processing.
  • the adhesive 118 can comprise an organic adhesive and can be sensitive to high temperatures. Accordingly, the use of the adhesive 118 to attach the carrier 120 to the microelectronic structure 114 may limit the temperatures that can be applied during processing. In other embodiments, however, the carrier 120 can be directly bonded to the frontside of the microelectronic structure 114 without an adhesive 118.
  • a dielectric layer 122 may be deposited on the back side surface of the semiconductor 124.
  • a backside metallization layer 116 for instance a back-end-of line (BEOL) or redistribution layer (RDL), can be provided over the dielectric layer 122 and can be configured to electrically connect to the via structure 108.
  • BEOL back-end-of line
  • RDL redistribution layer
  • the conventional via formation process has several problems that lead to non-uniform via lengths.
  • the etch process used to form the openings for the vias is non-uniform across the substrate, e.g., wafer, particularly for the high aspect ratio openings used for vias, which leads to via openings having different depths.
  • This nonuniformity in produced vias causes yield loss during the TSV reveal process.
  • dielectric deposition which is part of the TSV reveal process, may be limited by the temporary bond material used to adhere the die to a carrier. The adhesive limits the backside dielectric deposition temperature and can cause various processing complications.
  • temporary bond layer thickness non-uniformity can add to the thinned silicon wafer thickness uniformity.
  • the etch process that is used to form the via openings can have a non-uniformity of approximately 7 microns.
  • the etch depth may be higher 202, while some areas of the wafer with have low etch depths 206, other areas of the wafer will have etch depths 204 between the low 206 and high 202 etch depths.
  • the varying depth of the via openings leads to different via structure lengths once the conductive material, for instance copper, is filled into the openings.
  • the different via lengths can lead to a significant loss in yield.
  • This loss of thickness for example, when combined with wafer thickness variations caused by the temporary processes can further decrease the TSV yield.
  • dies that have TSVs that are too short 304 to be effective and dies that have TSVs that are too long 302 to be effective may not be used.
  • some dies within the wafer may have TSVs that are too long 302 and break off during grinding or polishing.
  • Other vias are too short 304 and are buried in the semiconductor portion of the device.
  • non-uniform TSVs may result from incomplete or non- uniform plating procedures.
  • the via openings may be etched uniformly, but the plating process through the high aspect ratio openings may not uniformly fill the via openings.
  • This process variation reduces the number of dies that are effective 306. Accordingly, non-uniform TSV lengths may result from a variety of different processing methods.
  • Figure 3B illustrates the thickness variation on an 8” wafer that can be measured after TSV planarization.
  • the thickness of the wafer can vary by 4 microns. Some regions of the wafer can have a thickness of up to 58.09 microns, while other regions of the wafer can have a thickness of 56.09 microns, while other regions of the wafer can have lower thicknesses around 54.67 microns. Wafer thickness variation can also cause some TSVs to be rendered ineffective and lead to lower levels of process control.
  • the lengths of the TSVs may vary considerably across the wafer after grinding the backside of the semiconductor portion to reveal the TSVs. Accordingly, as the backside of the bulk semiconductor portion is ground or otherwise thinned, the exposed vias may protrude from the backside of the thinned semiconductor portion by varying lengths and some vias, as explained above, may remain unexposed and buried in the semiconductor portion.
  • one or more backside dielectric layers can be provided over the backside of the semiconductor portion and over the TSVs. While it may be possible to employ solder bumping despite some degree of TSV height variability, the variability leads to a lack of levelness and makes stacking difficult. Some stacking technologies, such as direct hybrid bonding, are especially sensitive to topographical variations.
  • a barrier layer e.g., a dielectric barrier layer, such as silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon, or any other suitable dielectric barrier material layer, can be deposited over the backside of the semiconductor portion, over a sidewall of the exposed TSVs, and over the exposed end surfaces of the exposed TSVs.
  • a second dielectric layer such as silicon oxide or any other suitable dielectric, can be deposited over the dielectric barrier layer, including over the upper surface of the barrier layer, over the portion of the barrier layer that extends along the sidewall of the exposed TSVs, and over the portion of the barrier layer that is disposed along the end surface of the exposed TSVs.
  • the vias and portion(s) of the dielectric layer(s) can be polished, or otherwise removed, to planarize the vias and reduce non-uniformities.
  • thinner layer(s) of the first dielectric barrier layer and/or the second dielectric barrier layer may be deposited over the thinned semiconductor portion and the vias.
  • the dielectric layer(s) may be only 1 or 2 microns thick, e.g., significantly thinner than the length of the protruding portions of the vias.
  • the vias and dielectric layer(s) are polished, some of the vias may break off, such that the ends of the vias are embedded in the semiconductor portion and recessed relative to the backside of the semiconductor portion. Broken TSVs can reduce device yield.
  • the chosen metal within the TSVs can lead to significant changes in TSV performance.
  • copper can be an effective deposition metal.
  • Copper when used in TSVs, is an alloy metal that may be used and may change expansion and polishing characteristics of the TSV. Copper at the bottom of the etch via may be generally confined and may not anneal at the same rates or the same temperatures as free copper.
  • TSV metallization may include metallic or organic impurities that are unsuitable for reliable direct bonding by, for example, Direct Bond Interconnect® processes.
  • shrinkage of TSVs during storage or thermal processing has been shown to cause topographical issues, e.g. the formation of rims or trenches, in the isolation oxide which may surround the TSV.
  • TSV can have a typical depth variation of 2 to 4 um over a 300 mm wafer out of a total of a 55 um depth. This variation in depth may create challenges for achieving uniform surface bonding. Moreover, non uniform TSVs can cause breakage during processing leading to lower yields. Silicon wafers may be planarized using chemical mechanical processing (CMP) planarization. Some TSVs may be broken off during CMP planarization. This breaking may be in part caused by excessive TSV reveal which often is caused by the depth variation in TSVs.
  • CMP chemical mechanical processing
  • backside TSV processing has not been used for direct bonding in high volume manufacturing.
  • Conventional procedures for planarizing TSVs on the back side of wafers may also rely on patterning copper pads and adding solder bumps to the wafers.
  • Conventional backside processing also does not protect against breaking off of TSVs and may not achieve planarity suitable for direct bonding.
  • These processes may not be suitable for high volume manufacturing because of the length of polishing time, the number of polish cycles - which may range from 4 to 6 cycles and take up to 2 hours of machine time, the amount of material that is deposited (5 um), the amount of material removed (2-4 um depending on the oxide deposited), and the total annealing time used between polishes (3-5 one hour annealing cycles).
  • Various embodiments disclosed herein can improve device yield by ensuring that TSV length is uniform throughout the thinned wafer.
  • Some embodiments may use a copper wet etch to lower the copper TSV surface up to a few microns below the silicon surface.
  • surrounding silicon bulk will help to restrain and stabilize the copper within the TSVs.
  • barrier layers are deposited before the deposition of copper seed layers.
  • electroplating techniques are used to fill the vias.
  • some TSVs may be deeper than other TSVs and electroplating processes may be used to accommodate broken TSV additional depths.
  • the annealing processes stabilize the copper plug material so as to provide it with similar chemical and structural properties as device-side copper used for bonding. In some embodiments, the annealing processes stabilizes the copper plug material to have the same impurity and texturing characteristics of the device side bonding copper. In some embodiments, plated copper can be annealed as a direct bonding interface. This annealing may stabilize the copper plug material, making the plug material chemically and physically resemble the device side direct bonding interface copper pad.
  • CMP used on the copper layers can comprise a standard direct bond interface CMP slurry and process.
  • the CMP for TSVs can be the same as the device side CMP in terms of slurry usage and machine time.
  • the CMP parameters may be the same or similar to the device side CMP parameters. In some embodiments, this CMP uniformity can be achieved with or without the use of additional photolithography steps. In some embodiments, the only photolithography steps that are used during the CMP process may be blanket backside processing.
  • FIGS 4A-4I illustrate a method for forming a microelectronic structure, according to one embodiment.
  • TSV structures 410 can be provided at least partially through a thickness of substrate that includes a bulk semiconductor portion 404.
  • the bulk semiconductor portion 404 can comprise silicon, germanium, silicon carbide or any other suitable semiconductor material.
  • One or multiple lining layers 412 can be provided in the openings from a front surface 406 of a substrate.
  • the one or more lining layers 412 can comprise a dielectric liner 415 in some embodiments.
  • the dielectric liner 415 of the one or more lining layers 412 can comprise silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon, and any other suitable dielectric material.
  • the one or more lining layers 412 can additionally or alternatively include a first lining barrier layer 413.
  • Figure 4A schematically illustrates the layer 412 as a single layer, it should be appreciated that the layer 412 can comprise multiple layers or sub-layers, including, e.g., a dielectric liner 415 and a lining barrier layer 413.
  • a first conductive via 402 can be provided in the openings over the lining layer(s) 412.
  • the first conductive via 402 can comprise copper, although other suitable metals may be used.
  • the first conductive via portion 402 can be provided from the front surface of the substrate 406.
  • the first lining barrier layer 413 can comprise a conductive barrier for reducing diffusion of the conductive via material.
  • the first lining barrier layer 413 may be a different material from the conductive material of the first 402 and second 424 conductive via portions.
  • the first lining barrier layer 413 may be configured to reduce diffusion of the conductive material of the first 402 and/or second 424 conductive via portions into the surrounding dielectric and/or semiconductor materials.
  • the first conductive via portion 402 can be electroplated within the opening over a seed layer.
  • the front surface or side of the wafer e.g., the first surface 406 may comprise an active side of the semiconductor portion with active integrated circuitry, such as transistors, formed in or on the active side.
  • the front or first surface 406 of the wafer can be mounted to a carrier 414.
  • the carrier 414 may serve as a temporary handle wafer in some embodiments.
  • the microelectronic structure can be attached to the carrier 414 with an adhesive.
  • the microelectronic structure can be directly bonded to the carrier 414 without an intervening adhesive, using the direct bonding techniques described in more detail below.
  • the TSVs 410 can have variable heights across the substrate due to variable etching through a significant depth through bulk semiconductor.
  • the backside of the semiconductor portion, the second side, 408, also a back surface of the substrate at this stage, can be thinned, by dry etching or otherwise removed, to reveal the TSVs. 410.
  • the TSVs 410 can protrude beyond the backside of the semiconductor portion 408.
  • the lengths of the TSVs 410 may be non-uniform across the wafer, such that the TSVs 410 protrude by varying lengths above the semiconductor portion 416.
  • the etch process may leave the via structures 410 intact, such that the one or more lining layer(s) 412, including dielectric liner 415 and first lining barrier layer 413, remain disposed over and along a sidewall 411 of the first conductive via portion.
  • one or more dielectric layers 418 can be provided, e.g., deposited, over the upper surface 408 of the bulk semiconductor portion 416, along sidewalls 411 of the via structures 410, and over end surfaces of the via structures 410 to define a back surface of the substrate 408.
  • Figure 4C schematically illustrates the layer 418 as a single layer, it should be appreciated that the layer 418 can comprise multiple layers or sublayers.
  • dielectric layer(s) 418 can be a first dielectric barrier layer 419 provided on the bulk semiconductor portion 416 and on the via structure 410.
  • the dielectric layer(s) 418 can further comprise a second dielectric layer 421 over the first dielectric barrier layer 419.
  • the first dielectric barrier layer 419 can comprise a material to reduce copper migration, such as, e.g., silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, diamond-like carbon (DLC), or any other suitable dielectric barrier layer material.
  • the second dielectric layer 421 can comprise a lower k dielectric material, and can be an inorganic dielectric, such as silicon oxide.
  • the TSVs 410 can protrude beyond the semiconductor portion 408 by a distance in a range of about 0 to 10 microns, 1 to 7 microns, or 5 to 6 microns. Further as explained herein, the TSVs 410 can break off, as seen in TSV 420, and be recessed within the semiconductor portion 416 and/or the dielectric layer(s) 418 by a distance in a range of 0 to 10 microns, 1 to 7 microns, or 2-6 microns. The thickness of the dielectric layer(s) 418 can be in a range of about 2 to 7 microns, in a range of about 3 to 7 microns, or in a range of 4 to 6 microns, or about 5 microns in one embodiment.
  • the via structures 410 and dielectric layer(s) 418 can be planarized, for example, using a chemical-mechanical polishing (CMP) process applied to the back surface of the substrate 408.
  • CMP chemical-mechanical polishing
  • the planarization process may break off one or more of the TSVs 410, for instance the middle TSV 420.
  • the middle TSV 420 is shown as having broken off such that the TSV 420 is embedded within and recessed below the surface of the dielectric layer(s) 418 and/or semiconductor portion 416.
  • broken TSVs like the middle TSV 420, can reduce device yield for the wafer.
  • the first conductive via portion 402 can be selectively etched so as to be recessed below the back surface of the substrate 408, e.g., below the dielectric layer(s) 418 and/or the semiconductor portion 408. Because the middle TSV 420 broke off, the depth of the etch for the middle via structure 420 is deeper than the etch for the other via structures 410. In various embodiments, a selective copper wet etch can be performed to etch only a portion of the first conductive via portion 402.
  • all of the TSVs 410 across the substrate 416 are recessed to some degree, at least below the upper surface of the added dielectric layer(s) 418.
  • recessing of the TSVs 410 can be accomplished during the CMP described above with respect to Figure 4D.
  • not all TSVs 410 are recessed, and only some TSVs 410 are recessed, whether or not a separate recessing process is employed.
  • a conventional CMP process is employed in which some TSVs 410 are substantially recessed below the surface 408, e.g., due to breaking off.
  • a second barrier layer 422 can be provided over the exposed end surface of the first conductive via portions 402 and along the lining barrier layer 412.
  • a seed layer (not illustrated) can be provided over the second barrier layer 422, and a second conductive via portion 424 can be provided, by for instance, electroplating, over the second barrier layer 422 from the back surface of the substrate 416.
  • the microelectronic structure can be annealed, which can beneficially promote grain growth to improve direct bonding.
  • the deposition process for instance, electroplating, and an anneal process can both be selected to prepare for direct hybrid bonding, as opposed to the plating process that was used to fill the TSV 410 vias in the first place, which is selected to improve filling of high aspect ratio, deep vias.
  • alloying additives can be provided to the conductive material of the TSV 410.
  • the alloying additives can be provided to control thermal expansion and/or improve corrosion resistance of the conductor.
  • the conductor is copper, silver, gold, or any other suitable conductive material.
  • the alloying additive material(s) can include metallic elements, for example, beryllium, indium, gallium, nickel, and manganese, typically representing less that 5 atomic % and more particularly less than 2 atomic % of the TSV 410.
  • the alloying additive may be provided as part of the seed layer or the second barrier layer 422 and diffuse therefrom.
  • Such alloying elements can be present in different amounts to affect the TSV 410 hardness, corrosion resistance and/or to pin grain formation during subsequent anneal. Because larger grains are desirable in the second conductive portion to aid interdiffusion in a direct metal-to-metal bonding process, the first conductive portion 402 may contain a smaller percentage of the alloying elements as compared to the second conductive portion 424.
  • the second conductive via portion 424 can have at least 5% less, at least 10% less, at least 15% less, or at least 20% less of the alloying element(s) as compared to the first conductive via portion.
  • one or more organic additives can be provided to the plating bath during formation of the TSV 410 to improve filling.
  • different additives and/or different proportions of additives e.g., fewer additives, may be provided when plating the second conductive via portion 424 as compared to the type or amount of additives used when plating the first conductive via portion 402 that fills the opening.
  • additives may be used when plating both the first 402 and second 424 conductive via portions, but the amount of additives used for the first conductive via portion 402 may be substantially different than the amount used for the second conductive via portion 424.
  • additives may be used when plating the first conductive via portion 402 than when plating the second conductive via portion 424.
  • additives such as organic additives, may be provided during electroplating of the first conductive via portion 402 to, e.g., improve filling, but different proportions or different types of organic additives may be provided during electroplating of the second conductive via portion 424.
  • the plating bath for the first conductive via portion 402 can include a higher percentage of organic additives as compared to the plating bath for forming the second conductive via portion 424.
  • the first conductive via portion 402 may have a higher percentage of impurities, such as sulfur, oxygen, nitrogen, and/or carbon, as compared to the second conductive via portion 424.
  • the first conductive via portion 402 can be formed in a plating bath have a higher concentration of leveler, e.g., Janus Green, which introduces more impurities, such as nitrogen, carbon, and/or oxygen, as compared to the second conductive via portion 424.
  • the impurities from additives may be measured in part per million (ppm).
  • impurities from the plating additives may be incorporated in the first 402 and/or second 424 conductive via portions.
  • the amount of impurities present in the first conductive via portion 402 may be more than the amount of impurities present in the second conductive via portion 424.
  • only trace amounts of the impurities may be present in the second conductive via portion 424.
  • the impurities present in the second conductive via portion 424 can have a different composition and/or concentrations compared to the first conductive via portion 402.
  • compositions may be selected to influence the grain size, orientation or thermal stability of the interconnect that can be formed by the second conductive portion.
  • Impurities can include other material elements present within the conductive vias with concentrations less than 2 atm. %, e.g., less than 100 ppm or less than 50 ppm.
  • the impurities in the second conductive via portion 424 can be less than the impurities in the first conductive via portion 402.
  • the second conductive via portion 424 can have at least 5% less, at least 10% less, or at least 20% less non-copper elements (e.g., such as metallic alloying elements, or impurities from plating bath additives) than the first conductive via portion 402.
  • portions of the second conductive via portion 424 and the second barrier layer 422 that overlie the dielectric layer 418 can be removed, for example, using a CMP process applied to the back surface of the substrate.
  • the polishing process can expose and planarize the dielectric layer(s) 418, and can serve as a preparatory step for direct bonding, i.e., a very high degree of polishing accomplishes planarity sufficient for direct bonding.
  • the middle broken TSV 420 has been repaired, the metal recess is provided at a suitable depth , and the polished dielectric layer(s) 418 and second conductive via portions 424 can be used in a direct bonding process.
  • the plating and annealing process can form grains, e.g., copper, gold, or silver grains, or metal texture, e.g., copper, oriented along a 111 crystal plane primarily perpendicular to the bond surface, which can enhance metal diffusion and bonding during a direct bonding process.
  • the metal texture can be oriented so as to have a geometric component that is generally perpendicular to the bond surface.
  • the second conductive via portion 424 can have a first proportion of 111 planes oriented within 30° of vertical, e.g., within 30° of a vertical axis extending along a longitudinal dimension of the via structure, within 20° of vertical, or within 10° of vertical.
  • the second conductive via portion 424 can have a second proportion of 111 planes oriented within 30° of vertical, e.g., within 30° of a vertical axis extending along a longitudinal dimension of the via structure, within 20° of vertical, or within 10° of vertical. In some embodiments, the second proportion can be greater than the first portion.
  • each TSV 410 may include both first 402 and second 424 conductive via portions.
  • each of the TSVs 410 may be recessed below the dielectric layer(s) 418 upper surface, for example, by less than 40 nm, less than 30 nm, less than 20 nm, less than 15 nm or less that 10 nm, but more than or equal to about 5 nm, e.g., more than or equal to about 2 nm.
  • a first stacked die 434 can be directly bonded to a base wafer 432 without an adhesive.
  • the front active surface can be bonded to the base wafer.
  • contact pads 426 of the first die can be directly bonded to contact pads 426 of the wafer without an adhesive
  • nonconductive regions can be directly bonded to corresponding nonconductive regions of the wafer without an adhesive 430.
  • Additional devices can be stacked and directly bonded to the backside of the microelectronic structure.
  • contact pads 426 of a second element or die 436 can be directly bonded to the exposed TSV structures 410 of the first element 434 without an adhesive.
  • Nonconductive regions of the second element or die 436 can be directly bonded to the dielectric layer(s) 418 without an adhesive.
  • Additional elements can be directly bonded to the second element or die to form any number of elements in the stacked and directly bonded structure.
  • processed wafers with the methods described herein may be assembled or stacked and directly bonded to each other without an intervening adhesive layer.
  • Figure 41 illustrates the via structure 410 formed using various disclosed embodiments.
  • the microelectronic structure can include a bulk semiconductor portion 404 having a first/front surface 406 and a second/back surface opposite the first surface 408.
  • the second surface 408 can comprise an active surface having active circuitry formed in or on the second surface.
  • the first surface 406 may comprise an active surface having active circuitry formed in or on the second surface.
  • the first surface 406 may comprise an inactive surface devoid of active circuitry.
  • the via structure 410 can be disposed in an opening extending at least partially through, e.g., completely through, the bulk semiconductor portion 404 along a direction non-parallel to the first surface.
  • the via structure can include a first conductive via portion 402, a second conductive via portion 424, and a second barrier layer 422.
  • the second barrier layer 422 includes a first portion 440 disposed between the first conductive via portion 402 and the second conductive via portion 424.
  • the second barrier layer 422 can also include a second portion 442 disposed along the sidewall 411 of the second conductive portion 402.
  • the second conductive via portion 424 can extend from the second barrier layer 440 to at least the surface of the substrate 408.
  • the second conductive via portion 424 can have a different composition from the first conductive via portion 402.
  • Both the first 402 and second 424 conductive via portions can be formed of copper, for example, but have different types and/or concentrations of alloying elements and impurities, e.g., originating from the types of levelers, suppressors, accelerators, plating current densities, used in the electroplating process, and/or different grain sizes and/or orientations.
  • the first 402 and/or second 424 conductive via portion can have different proportions of non-copper elements, such as metallic alloying elements, or impurities from plating bath additives.
  • the first via portion 402 can have more non-copper elements than the second 424 via portion.
  • the first via portion 402 can have alloying elements, such as Be, Mn, Ni, incorporated via diffusion from the barrier layer 412 or via the seed layer.
  • the second via portion 424 may not have such non-copper elements, or only trace levels of such impurities.
  • the second via portion 424 may have such non-copper elements but a smaller amount as compared to the first via portion.
  • the alloying material(s) incorporated via the barrier layer(s) 412 and/or the seed layer during plating can be provided in some arrangements to pin grains of the first via portion 402.
  • one or more organic additives can be provided during plating of the first via portion 402 to improve filling, and the additive may not be used in the second 424 conductive via portion.
  • the organic or other additives may be provided for both the first 402 and second 424 via portions, but the first via portion 402 may have higher concentrations of impurities left by the additives after plating.
  • impurities such as sulfur, oxygen, carbon, or nitrogen may be present in the TSVs 410 in higher concentrations in the first via portion 402 as compared to the second via portion 424.
  • the non-copper elements, including alloying elements and impurities from additives, composition in the first conductive via portion 402 is higher than those in the second conductive via portion 424.
  • the second conductive via portion 424 can have at least 5% less, at least 10% less, at least 15% less, or at least 20% less of the noncopper elements, as compared to the first conductive via portion 402.
  • the composition and grain structure of the first conductive portion 402 can be the result of processing selected to optimize filling of deep, high aspect ratio vias, wherein the composition and grain structure of the second conductive portion 424 can be selected to optimize subsequent direct hybrid bonding.
  • a dielectric layer 418 can be disposed on the bulk semiconductor portion 404, with the second 424 conductive via portion extending through the dielectric layer 418 such that an end of the second conductive via portion 424 is flush with an upper surface of the dielectric layer 418, or is slightly recessed relative to the upper surface of the dielectric layer 418, e.g., by less than about 40 nm, by less than about 30 nm, by less than about 20 nm, by less than about 10 nm, or by less than about 5 nm.
  • the dielectric layer 418 can include a planarized dielectric bonding layer configured for direct bonding to another element.
  • the dielectric layer 418 can further comprise a dielectric barrier layer on the bulk semiconductor portion 404, the planarized dielectric bonding layer disposed on the dielectric barrier layer.
  • a first lining barrier layer 412 can extend along a sidewall 411 of the first 402 and second 424 conductive portions.
  • the second barrier layer 440 can include a second portion 442 extending along the first barrier layer 412 between the first barrier layer 412 and the second conductive via portion 424.
  • the overall barrier thickness is greater between the second conductive portion 424 and the bulk substrate 404, as compared to that between the first conductive portion 402 and the bulk substrate 404, and may include two identifiable barrier layers, which may or may not have different compositions.
  • Figures 5A-5I illustrate a method for forming a microelectronic structure, according to another embodiment.
  • the embodiment of Figures 5A-5I may be the same as or generally similar to like components of Figures 4A-4I.
  • the steps of Figures 5A-5E may be the same as those set forth above in connection with Figures 4A-4E.
  • Figure 5F there may not be a barrier layer provided over the first conductive via portion 410. Rather, the second conductive via portion 424 may be plated directly onto the first conductive via portion 410, or onto an intervening seed layer only, and the bulk semiconductor portion 416 without an intervening barrier layer.
  • the structure of Figure 5F may be annealed, which can promote copper grain growth that is conducive to direct bonding.
  • the buried conductive material of the first conductive via portion 402 may be more constrained than the upper portions of conductive material of the second conductive via portion 424.
  • the first 402 and second 424 conductive via portions can form different metal textures and/or have different concentrations of non-copper elements, such as alloying elements and/or impurities from plating additives.
  • a first metal texture of the first conductive via portion 402 can be different from a second metal texture of the second conductive via portion 424.
  • the crystal structure of the second conductive via portion 424 can have grains oriented vertically along a 111 crystal plane non-parallel to, e.g., generally perpendicular to, the bond interface to enhance metal diffusion, e.g., copper diffusion, during direct bonding.
  • the grains can have geometric components that are generally perpendicular to the bond interface.
  • the first 402 and second 424 conductive via portions can comprise different metals or different alloys.
  • the first conductive via portion 402 can comprise a copper alloy
  • the second conductive via portion 424 can comprise substantially pure copper.
  • Figures 5G and 5H may be generally similar to the steps set forth in Figures 4G and 4H.
  • Figure 51 illustrates the microelectronic structure without the intervening barrier layer of Figure 41.
  • the second conductive via portion 424 can be formed after and separately from the first conductive via portion 402.
  • Figures 6A-6H illustrate another embodiment that enables the formation of conductive vias 606 having generally uniform lengths, while avoiding degradation of the vias 606, e.g., copper vias or other suitable conductive metal, and/or contamination of the semiconductor portion 604, e.g., silicon or other suitable semiconductor.
  • the components of Figures 6A-6H may be generally similar to the components of Figures 4A-5I.
  • a semiconductor element 604 e.g., a semiconductor wafer
  • the front side of the bulk semiconductor 610 is shown facing upwardly, and the opposite back side of the bulk semiconductor 612 is shown facing downwardly.
  • the front side 610 can comprise an active side of the semiconductor element, such that active circuitry can be formed at or near the front side 610.
  • a dielectric liner and/or a barrier layer 608 can line the openings in which the vias 606 are disposed.
  • One or more frontside dielectric layer(s) 602 can be provided over the front side of the semiconductor portion 610.
  • Figure 6A schematically illustrates the layer 602 as a single layer, it should be appreciated that the layer 602 can comprise multiple layers or sub-layers.
  • the frontside dielectric layer(s) 602 can comprise any suitable type of dielectric material(s), including, e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, diamond-like carbon (DLC), and any other suitable dielectric material.
  • dielectric material(s) including, e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, diamond-like carbon (DLC), and any other suitable dielectric material.
  • the depth of the openings in which the conductive via 606 material is deposited, e.g., electroplated, may vary which can lead to the formation of vias having non-uniform lengths.
  • the lack of uniformity can make it challenging to reveal the vias from the back side of the semiconductor element 612.
  • the etch variation of the via openings 606 can be on the order of 2-3 microns or more, such that there may be a 50% or more variation in TSV heights.
  • the semiconductor portion 604 is dry etched to expose the vias 606, which may protrude above the semiconductor material 604 at different heights.
  • etching a semiconductor material 604 such as silicon with an etchant such as SFe may cause severe erosion of the copper via material, particularly if the dielectric liner and/or the lining barrier layer 608 are etched before the via 606 is adequately revealed.
  • processing of the conductive vias 606, e.g.* by CMP, grinding, and other processing methods may cause some of the conductive material of the via, e.g., copper material, to contaminate the semiconductor portion 604, e.g., silicon.
  • the back side of the semiconductor portion 612 can be grinded and polished, e.g., with CMP, to reveal the vias 606.
  • the grinding and polishing processes can uniformly reveal the conductive vias 606, which can accommodate for the non-uniform lengths of the vias 606 before grinding and polishing.
  • the back side of the semiconductor element 612 can be grinded and polished until all of the vias 606 are revealed at the planarized, grinded and polished back side of the semiconductor element 614.
  • the grinding and polishing processes can be used to reveal vias 606 having a generally uniform length.
  • the conductive via 606 can be etched from the backside 614 to form an etched recess in the conductive material, which can comprise copper.
  • the conductive material can be etched at a depth in a range of 0.25 microns to 3 microns, in a range of 0.5 microns to 3 microns, e.g., about 1 micron in an embodiment.
  • a first backside dielectric layer 616 can be provided, e.g., deposited, over the grinded and polished back side of the semiconductor portion 618 and into the etched recesses formed in the vias 620.
  • the first backside dielectric layer 616 can extend within the recesses over the copper vias and abutting the dielectric liner and/or barrier layers disposed in the openings 620.
  • the first backside dielectric layer 616 can comprise a plurality of layers.
  • the first backside dielectric layer 616 can comprise a first dielectric layer 617, e.g., a low temperature silicon nitride dielectric layer, disposed on the back side of the semiconductor portion and on the vias 606 and a second dielectric layer 619, e.g., a low temperature silicon oxide dielectric layer, over the first dielectric layer 617.
  • the first 617 and/or second 619 dielectric layers can be formed using a low-temperature chemical vapor deposition (CVD) process.
  • the first backside dielectric layer 616 can comprise only a single dielectric layer, or more than two dielectric layers.
  • the back side of the semiconductor element 614 can be polished (e.g., with CMP) to remove first portions of the first backside dielectric layer 616 that overlie the semiconductor portion 604 so as to expose the semiconductor portion 604.
  • Second portions of the first backside dielectric layer 620 may remain disposed in the recess over the conductive vias 606 as shown in Figure 6E.
  • the remaining second portion of the first backside dielectric layer 620 may serve to protect the conductive via material during a subsequent dry etch of the semiconductor portion 604, shown in Figure 6F.
  • the dry etch of Figure 6F can accordingly uniformly reveal the vias 606, and the second portion of the first backside dielectric layer 620 can serve to protect the copper of the vias during the dry etch, e.g., using SFe.
  • the step of Figure 6F can use an etchant, e.g., SFe, that is highly selective to silicon over the first backside dielectric layer 620, which can include silicon oxide at the exposed surface.
  • the vias 606, first portion of the first backside dielectric layer 620, and dielectric liner/barrier layers 608 can protrude relative to an etched surface at the back side of the semiconductor portion 604.
  • the vias can protrude by an amount in a range of 3 microns to 4 microns.
  • a second backside dielectric layer(s) 624 can be provided, e.g., deposited over the etched surface 622 of the semiconductor portion 604, along sidewalls of the exposed lining layers of the vias 606, over end portions of the lining layers 608, and over the second portions of the first backside dielectric layer 620.
  • the second backside dielectric layer 624 can comprise a plurality of layers.
  • the second backside dielectric layer can comprise a first dielectric layer 625, e.g., a low temperature silicon nitride dielectric layer, disposed on the etched surface of the semiconductor portion 622 and on the second portion of the first backside dielectric layer 620 and a second dielectric layer 627, e.g., a low temperature silicon oxide dielectric layer, over the first dielectric layer 625.
  • the second backside dielectric layer 624 can comprise only a single dielectric layer, or more than two dielectric layers.
  • a thickness of the second backside dielectric layer 624 can be any suitable thickness, e.g., in a range of 4 microns to 5 microns in various embodiments.
  • a thickness of one or both of the first 625 and second 627 backside dielectric layer(s) can be selected so as to provide adequate support or stress compensation, particularly for thinned dies.
  • the back side of the semiconductor element can be polished (e.g., with CMP) to expose the vias 606.
  • the polishing can remove portions of the second backside dielectric layer 624 that are disposed over the first backside dielectric layer 616, the remaining second portion of the first backside dielectric layer 620, and can thin the portion of the second backside layer that overlie the semiconductor portion.
  • the second backside dielectric layer 624 can be disposed over the etched surface 622 of the semiconductor portion 604 and can about the via lining layer(s) 608, e.g., the lining dielectric layer and/or lining barrier layer.
  • the polishing can also serve to recess the conductive material within the via 606 relative to the second backside dielectric 624 layer so as to prepare the back side of the semiconductor element for direct bonding.
  • the polishing can recess the conductive material by an amount in a range of 1 nm to 20 nm, or in a range of 1 nm to 10 nm.
  • the semiconductor element can be directly bonded and/or stacked to another element.
  • the frontside dielectric layer(s) 602 can also be removed to expose the vias 606 at the front side, and one or more additional elements can be stacked on and directly bonded to the front side of the semiconductor element.
  • Various embodiments disclosed herein relate to directly bonded structures in which two elements can be directly bonded to one another without an intervening adhesive.
  • Two or more semiconductor elements such as integrated device dies, wafers, and other semiconductor elements, may be stacked on or bonded to one another to form a bonded structure.
  • Conductive contact pads of one element may be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements can be stacked in the bonded structure.
  • the elements are directly bonded to one another without an adhesive.
  • a non-conductive or dielectric material of a first element can be directly bonded to a corresponding non-conductive or dielectric field region of a second element without an adhesive.
  • the non-conductive material can be referred to as a nonconductive bonding region or bonding layer of the first element.
  • the non-conductive material of the first element can be directly bonded to the corresponding non-conductive material of the second element using dielectric-to-dielectric bonding techniques.
  • dielectric-to-dielectric bonds may be formed without an adhesive using the direct bonding techniques disclosed at least in U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
  • hybrid direct bonds can be formed without an intervening adhesive.
  • dielectric bonding surfaces can be polished to a high degree of smoothness.
  • the bonding surfaces can be cleaned and exposed to a plasma and/or etchants to activate the surfaces.
  • the surfaces can be terminated with a species after activation or during activation, e.g., during the plasma and/or etch processes.
  • the activation process can be performed to break chemical bonds at the bonding surface, and the termination process can provide additional chemical species at the bonding surface that improves the bonding energy during direct bonding.
  • the activation and termination are provided in the same step, e.g., a plasma or wet etchant to activate and terminate the surfaces.
  • the bonding surface can be terminated in a separate treatment to provide the additional species for direct bonding.
  • the terminating species can comprise nitrogen.
  • the bonding surfaces can be exposed to fluorine. For example, there may be one or multiple fluorine peaks near layer and/or bonding interfaces.
  • the bonding interface between two dielectric materials can comprise a very smooth interface with higher nitrogen content and/or fluorine peaks at the bonding interface. Additional examples of activation and/or termination treatments may be found throughout U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
  • conductive contact pads of the first element can also be directly bonded to corresponding conductive contact pads of the second element.
  • a hybrid bonding technique can be used to provide conductor-to-conductor direct bonds along a bond interface that includes covalently direct bonded dielectric-to-dielectric surfaces, prepared as described above.
  • the conductor-to-conductor, e.g., contact pad to contact pad, direct bonds and the dielectric-to-dielectric hybrid bonds can be formed using the direct bonding techniques disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.
  • dielectric bonding surfaces can be prepared and directly bonded to one another without an intervening adhesive as explained above.
  • Conductive contact pads which may be surrounded by nonconductive dielectric field regions, may also directly bond to one another without an intervening adhesive.
  • the respective contact pads can be recessed below exterior (e.g., upper) surfaces of the dielectric regions or nonconductive bonding regions, for example, recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of 4 nm to 10 nm.
  • the nonconductive bonding regions can be directly bonded to one another without an adhesive at room temperature in some embodiments and, subsequently, the bonded structure can be annealed. Upon annealing, the contact pads can expand and contact one another to form a metal-to-metal direct bond.
  • the use of hybrid bonding techniques such as Direct Bond Interconnect, or DBI®, available commercially from Xperi of San Jose, CA, can enable high density of pads connected across the direct bond interface, e.g., small or fine pitches for regular arrays.
  • the pitch of the bonding pads, or conductive traces embedded in the bonding surface of one of the bonded elements may be less 40 microns or less than 10 microns or even less than 2 microns.
  • the ratio of the pitch of the bonding pads to one of the dimensions of the bonding pad is less than 5, or less than 3 and sometimes desirably less than 2.
  • the width of the conductive traces embedded in the bonding surface of one of the bonded elements may range between 0.3 to 3 microns.
  • the contact pads and/or traces can comprise copper, although other metals may be suitable.
  • a first element can be directly bonded to a second element without an intervening adhesive.
  • the first element can comprise a singulated element, such as a singulated integrated device die.
  • the first element can comprise a carrier or substrate (e.g., a wafer) that includes a plurality, e.g., tens, hundreds, or more, of device regions that, when singulated, form a plurality of integrated device dies.
  • the second element can comprise a singulated element, such as a singulated integrated device die.
  • the second element can comprise a carrier or substrate (e.g., a wafer).
  • the first and second elements can be directly bonded to one another without an adhesive, which is different from a deposition process.
  • a width of the first element in the bonded structure can be similar to a width of the second element.
  • a width of the first element in the bonded structure can be different from a width of the second element.
  • the width or area of the larger element in the bonded structure may be at least 10% larger than the width or area of the smaller element.
  • the first and second elements can accordingly comprise non-deposited elements.
  • directly bonded structures unlike deposited layers, can include a defect region along the bond interface in which nanovoids are present.
  • the nanovoids may be formed due to activation of the bonding surfaces, e.g., exposure to a plasma.
  • the bond interface can include concentration of materials from the activation and/or last chemical treatment processes.
  • a nitrogen peak can be formed at the bond interface.
  • an oxygen peak can be formed at the bond interface.
  • the bond interface can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride.
  • the direct bond can comprise a covalent bond, which is stronger than van Der Waals bonds.
  • the bonding layers can also comprise polished surfaces that are planarized to a high degree of smoothness.
  • metal-to-metal bonds are formed between contact pads.
  • the contact pads comprise copper or a copper alloy.
  • the metal-to-metal bonds between the contact pads can be joined such that copper grains grow into each other across the bond interface.
  • the copper can have grains oriented along the 111 crystal plane for improved copper diffusion across the bond interface.
  • the bond interface can extend substantially entirely to at least a portion of the bonded contact pads, such that there is substantially no gap between the nonconductive bonding regions at or near the bonded contact pads.
  • a barrier layer may be provided under the contact pads, e.g., which may include copper. In other embodiments, however, there may be no barrier layer under the contact pads, for example, as described in US 2019/0096741, which is incorporated by reference herein in its entirety and for all purposes.
  • a microelectronic structure can include a bulk semiconductor portion having a first surface and a second surface opposite the first surface; and a via structure disposed in an opening extending at least partially through the bulk semiconductor portion along a direction nonparallel to the first surface, the via structure comprising a first conductive via portion, a second conductive via portion, a first barrier layer extending along a sidewall of the first conductive via portion, and a second barrier layer the second barrier layer including a first portion disposed between the first conductive via portion and the second conductive via portion, the second conductive via portion extending from the second barrier layer to at least the first surface.
  • the microelectronic structure includes a dielectric layer on the bulk semiconductor portion, the second conductive via portion extending through the dielectric layer such that an end of the second conductive via portion is flush with or recessed from an upper surface of the dielectric layer.
  • the dielectric layer comprises a planarized dielectric bonding layer configured for direct bonding to another element.
  • the dielectric layer further comprises a dielectric barrier layer on the bulk semiconductor portion, the planarized dielectric bonding layer disposed on the dielectric barrier layer.
  • the second barrier layer includes a second portion extending along the first barrier layer between the first barrier layer and the second conductive via portion.
  • a first metal texture of the first conductive via portion is different from a second metal texture of the second conductive via portion.
  • the second metal texture has grains oriented along a 111 crystal plane non-parallel to a bond interface.
  • the first and second conductive via portions comprises copper, the copper of the first conductive via portion having an impurity material therein.
  • the first conductive via portion has a higher impurity concentration than the second conductive via portion.
  • the first conductive via portion further comprises one or more alloying elements including one or more of beryllium (Be), indium (In), gallium (Ga), manganese (Mn), and nickel (Ni).
  • the impurity material comprises one or more of sulfur, oxygen, carbon, or nitrogen.
  • the first and second conductive via portions comprise different metals or different alloys.
  • the second surface comprises an active surface including active integrated circuitry formed in or on the second surface.
  • the microelectronic structure is directly bonded to another element without an intervening adhesive.
  • an end surface of the second conductive via portion is directly bonded to a contact pad of the another element without an intervening adhesive.
  • nonconductive bonding regions of the microelectronic element and the another element are directly bonded without an intervening adhesive.
  • the microelectronic structure can include a second via structure having a first conductive via portion, a second conductive via portion, a first barrier layer extending along a sidewall of the first conductive via portion, and a second barrier layer, the second barrier layer including a first portion disposed between the first conductive via portion and the second conductive via portion, wherein the second conductive via portion of the via structure extends along a length different from a length of the second conductive via portion of the second via structure.
  • a microelectronic structure in another embodiment, can include a bulk semiconductor portion having a first surface and a second surface opposite the first surface; and a via structure disposed in an opening extending at least partially through the bulk semiconductor portion through the first surface along a direction non-parallel to the first surface, the via structure comprising a first conductive via portion and a second conductive via portion disposed directly onto and contacting the first conductive via portion without an intervening barrier layer, the second conductive via portion disposed between the first surface and the first conductive via portion, the first conductive via portion having a different material composition from the second conductive via portion.
  • the microelectronic structure includes a barrier layer extending along a sidewall of the first and second conductive portions.
  • the microelectronic structure includes a dielectric layer on the bulk semiconductor portion, the second conductive via portion extending through the dielectric layer such that an end of the second conductive via portion is flush with or recessed below an upper surface of the dielectric layer.
  • the dielectric layer comprises a planarized dielectric bonding layer configured for direct bonding to another element.
  • the dielectric layer further comprises a dielectric barrier layer on the bulk semiconductor portion, the planarized dielectric bonding layer disposed on the dielectric barrier layer.
  • a first metal texture of the first conductive via portion is different from a second metal texture of the second conductive via portion.
  • the second metal texture has grains oriented along a 111 crystal plane.
  • the first and second conductive via portions comprises copper, the copper of the first conductive via portion having an impurity material therein.
  • the first conductive via portion comprises one or more alloying elements including one or more of beryllium (Be), indium (In), gallium (Ga), manganese (Mn), and nickel (Ni).
  • the impurity material comprises one or more of sulfur, oxygen, carbon, or nitrogen.
  • the first and second conductive via portions comprise different metals or different alloys.
  • the microelectronic device is directly bonded to another element without an intervening adhesive.
  • an end surface of the second conductive via portion is directly bonded to a contact pad of the another element without an intervening adhesive.
  • nonconductive bonding regions of the microelectronic element and the another element are directly bonded without an intervening adhesive.
  • a microelectronic structure in another embodiment, can include a bulk semiconductor portion having a first surface and a second surface opposite the first surface; and a via structure disposed in an opening extending at least partially through the bulk semiconductor portion through the first surface along a direction non-parallel to the first surface, the via structure comprising a first conductive via portion and a second conductive via portion disposed directly onto and contacting the first conductive via portion without an intervening barrier layer, the second conductive via portion disposed between the first surface and the first conductive via portion, the first conductive via portion being formed before, and separately from, the second conductive via portion.
  • the microelectronic structure includes a barrier layer extending along a sidewall of the first and second conductive portions.
  • a first metal texture of the first conductive via portion is different from a second metal texture of the second conductive via portion.
  • the second metal texture has grains oriented along a 111 crystal plane.
  • the first metal texture has a first proportion of 111 planes oriented within 30° of vertical, wherein the second metal texture has a second proportion of 111 planes oriented within 30° of vertical, the second proportion greater than the first portion.
  • the first and second conductive via portions comprises copper, the copper of the first conductive via portion having an impurity material therein.
  • the first conductive portion has a higher percentage of alloying elements as compared to the second conductive via portion.
  • the microelectronic device is directly bonded to another element without an intervening adhesive.
  • an end surface of the second conductive via portion is directly bonded to a contact pad of the another element without an intervening adhesive.
  • nonconductive bonding regions of the microelectronic element and the another element are directly bonded without an intervening adhesive.
  • a method of forming a microelectronic structure can include forming an opening at least partially through a substrate having a front surface and a back surface opposite the front surface, the opening extending through the front surface along a direction non-parallel to the second surface; providing a first conductive via portion in the opening from the front surface; revealing the first conductive via portion by removing material from the back surface; and after the revealing, providing a filling structure in the opening over the first conductive via portion from the back surface.
  • providing the filling structure comprises providing a second conductive via portion in the opening over the first conductive via portion from the back surface.
  • the method includes after revealing, recessing the first conductive via portion from the back surface. In some embodiments, the method includes after providing the first conductive via portion but before providing the second conductive via portion, providing a second barrier layer over the first conductive via portion. In some embodiments, the method includes providing a first barrier layer along a sidewall of the first conductive via portion. In some embodiments, the method includes providing the first barrier layer before providing the first conductive via portion. In some embodiments, providing the second barrier layer comprises providing the second barrier layer along the first barrier layer between the first barrier layer and the second conductive via portion.
  • the method includes providing a dielectric layer on the bulk semiconductor portion, the dielectric layer at least partially defining the back surface of the substrate, the second conductive via portion extending through the dielectric layer such that an end of the second conductive via portion is flush with or recessed from the back surface of the substrate.
  • the method includes preparing the dielectric layer for direct bonding to another element.
  • the method includes providing a dielectric barrier layer on the bulk semiconductor portion, the dielectric bonding layer disposed on the dielectric barrier layer.
  • the method includes directly bonding the dielectric layer to another element without an intervening adhesive.
  • the method includes directly bonding an end surface of the second conductive via portion to a contact pad of another element without an intervening adhesive.
  • providing the filling structure comprises providing a dielectric layer in a recess over the first conductive via portion.
  • the method can include removing a portion of the substrate from the back surface such that the first conductive via portion protrudes from the back surface of the substrate, and removing the dielectric layer to expose the conductive via.
  • removing the portion of the substrate comprises etching the back surface of the substrate.
  • the method can include providing a second backside dielectric layer over at least the etched back surface of the substrate and a portion of the dielectric layer disposed in the recess.
  • the method can include removing at least portions of the second backside dielectric layer that overlie the portion of the dielectric layer disposed in the recess. In some embodiments, the method can include planarizing the second backside dielectric layer and recessing the first conductive via portion relative to the second backside dielectric layer.
  • a method of forming a microelectronic structure can include forming an opening partially through a substrate having a front surface and a back surface opposite the first surface, the opening extending through the front surface along a direction non-parallel to the front surface; filling the opening with a first conductive via portion; revealing the first conductive via portion by removing material from the back surface; and refilling a portion of the opening with a filling structure after revealing the first conductive portion.
  • refilling the portion of the opening with the filling structure comprises providing a second conductive via portion in the opening over the first conductive via portion from the back surface.
  • the method includes recessing the first conductive portion after revealing to define the portion of the opening.
  • the method includes depositing a second barrier layer on the first conductive via portion after recessing and before refilling.
  • the method includes depositing a first barrier layer to line the opening prior to filling.
  • depositing the second barrier layer comprises depositing the second barrier layer on the first barrier layer in the portion of the opening.
  • refilling the portion of the opening with the filling structure comprises providing a dielectric layer in a recess over the first conductive via portion.
  • the method can include removing a portion of the substrate from the back surface such that the first conductive via portion protrudes from the back surface of the substrate, and removing the dielectric layer to expose the conductive via.
  • removing the portion of the substrate comprises etching the back surface of the substrate.
  • the method can include providing a second backside dielectric layer over at least the etched back surface of the substrate and a portion of the dielectric layer disposed in the recess.
  • the method can include planarizing the second backside dielectric layer and recessing the first conductive via portion relative to the second backside dielectric layer.
  • the bonded structure can include a first element having a first bonding surface and a second element having a second bonding surface, the first element having a third surface opposite the first bonding surface; and a via structure disposed in an opening extending at least partially through the first element from the first bonding surface along a direction non-parallel to the first bonding surface, the via structure comprising a first conductive via portion and a second conductive via portion contacting one another, the second conductive via portion at least partially embedded within a bonding material at the bonding surface of the first element, the bonding material and the second conductive via portion directly bonded to the bonding surface of the second element without an intervening adhesive.
  • nonconductive bonding regions of the first and second elements are directly bonded without an intervening adhesive.
  • a method of forming a microelectronic structure is disclosed.
  • the method an include: providing a substrate having an opening and a conductive via disposed in the opening, the conductive via extending partially through the substrate from a first side of the substrate towards the second side; removing a portion of the substrate from the second side to expose the conductive via; removing a portion of the conductive via from the second side of the substrate to form a recess; providing a dielectric layer in the recess over the conductive via; further removing a portion of the substrate from the second side such that the conductive via protrudes from the second side of the substrate; and removing the dielectric layer to expose the conductive via.
  • removing the portion of the substrate comprises at least one of grinding and polishing the second side. In some embodiments, at least one of grinding and polishing comprises planarizing the substrate and the conductive via. In some embodiments, removing the portion of the conductive via comprises etching the conductive via. In some embodiments, providing the dielectric layer comprises providing a first backside dielectric layer over the back side of the substrate and in the recess. In some embodiments, providing the first backside dielectric layer comprises providing a plurality of dielectric layers. In some embodiments, providing the plurality of dielectric layers comprises providing a first silicon nitride layer over the back side of the substrate and over the conductive via and providing a second silicon oxide layer over the first silicon nitride layer.
  • the method can include, before further removing the portion of the substrate, removing a portion of the first backside dielectric layer that is disposed over the back side of the substrate. In some embodiments, further removing the portion of the substrate comprises etching the back side of the substrate. In some embodiments, the method can include providing a second backside dielectric layer over at least the etched back side of the substrate and a portion of the first backside dielectric layer disposed in the recess. In some embodiments, the method can include removing at least portions of the second backside dielectric layer that overlie the portion of the first backside dielectric layer disposed in the recess. In some embodiments, the method can include planarizing the second backside dielectric layer and recessing the conductive via relative to the second backside dielectric layer.
  • the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.”
  • the word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements.
  • the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements.
  • first element when used in this application, shall refer to this application as a whole and not to any particular portions of this application.
  • first element when a first element is described as being “on” or “over” a second element, the first element may be directly on or over the second element, such that the first and second elements directly contact, or the first element may be indirectly on or over the second element such that one or more elements intervene between the first and second elements.
  • words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively.

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US12564086B2 (en) 2016-10-27 2026-02-24 Adeia Semiconductor Technologies Llc Structures for low temperature bonding using nanoparticles
US12154880B2 (en) 2018-12-18 2024-11-26 Adeia Semiconductor Bonding Technologies Inc. Method and structures for low temperature device bonding
US20220208702A1 (en) * 2020-12-30 2022-06-30 Invensas Bonding Technologies, Inc. Structure with conductive feature and method of forming same
US12211809B2 (en) * 2020-12-30 2025-01-28 Adeia Semiconductor Bonding Technologies Inc. Structure with conductive feature and method of forming same
US12622307B2 (en) 2022-12-21 2026-05-05 Adeia Semiconductor Bonding Technologies Inc. Controlled grain growth for bonding and bonded structure with controlled grain growth
US12506114B2 (en) 2022-12-29 2025-12-23 Adeia Semiconductor Bonding Technologies Inc. Directly bonded metal structures having aluminum features and methods of preparing same
US12545010B2 (en) 2022-12-29 2026-02-10 Adeia Semiconductor Bonding Technologies Inc. Directly bonded metal structures having oxide layers therein

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US20260047416A1 (en) 2026-02-12
JP2024501016A (ja) 2024-01-10
US20220246497A1 (en) 2022-08-04
US20260040922A1 (en) 2026-02-05
KR20230125309A (ko) 2023-08-29
US12456662B2 (en) 2025-10-28
EP4268273A4 (en) 2024-10-23

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