JP2024501016A - 基板貫通ビアを有する構造体及びそれを形成する方法 - Google Patents

基板貫通ビアを有する構造体及びそれを形成する方法 Download PDF

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JP2024501016A
JP2024501016A JP2023539267A JP2023539267A JP2024501016A JP 2024501016 A JP2024501016 A JP 2024501016A JP 2023539267 A JP2023539267 A JP 2023539267A JP 2023539267 A JP2023539267 A JP 2023539267A JP 2024501016 A JP2024501016 A JP 2024501016A
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conductive via
via portion
dielectric layer
backside
conductive
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JP2024501016A5 (https=
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ガイウス ギルマン ジュニア ファウンテン
シプリアン エメカ ウゾー
ジョージ カールトン ハドソン
ジョン ポストヒル
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アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド
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    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
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    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
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    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
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    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
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    • H10W20/0249—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture
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    • H10W20/211—Through-semiconductor vias, e.g. TSVs
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    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
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    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
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    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
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    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
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    • H10W72/019—Manufacture or treatment of bond pads
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    • H10W72/921—Structures or relative sizes of bond pads
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    • H10W72/9226—Bond pads being integral with underlying chip-level interconnections with via interconnections
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JP2023539267A 2020-12-28 2021-12-27 基板貫通ビアを有する構造体及びそれを形成する方法 Pending JP2024501016A (ja)

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US202063131263P 2020-12-28 2020-12-28
US63/131,263 2020-12-28
US202163216389P 2021-06-29 2021-06-29
US63/216,389 2021-06-29
PCT/US2021/073122 WO2022147429A1 (en) 2020-12-28 2021-12-27 Structures with through-substrate vias and methods for forming the same

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JP2024501016A true JP2024501016A (ja) 2024-01-10
JP2024501016A5 JP2024501016A5 (https=) 2024-12-27

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US (3) US12456662B2 (https=)
EP (1) EP4268273A4 (https=)
JP (1) JP2024501016A (https=)
KR (1) KR20230125309A (https=)
WO (1) WO2022147429A1 (https=)

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US20260040922A1 (en) 2026-02-05
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US12456662B2 (en) 2025-10-28
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