JP5857615B2 - 電子装置およびその製造方法 - Google Patents
電子装置およびその製造方法 Download PDFInfo
- Publication number
- JP5857615B2 JP5857615B2 JP2011228333A JP2011228333A JP5857615B2 JP 5857615 B2 JP5857615 B2 JP 5857615B2 JP 2011228333 A JP2011228333 A JP 2011228333A JP 2011228333 A JP2011228333 A JP 2011228333A JP 5857615 B2 JP5857615 B2 JP 5857615B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- wiring
- layer
- resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Description
以下、第1の実施形態を、図4A〜図4Hの断面図を参照しながら説明する。
次に第2の実施形態を、図5A〜図5Gの断面図を参照しながら説明する。
図8は、第3の実施形態による多層配線基板80の例を示す断面図である。ただし図8中、先の実施形態で説明した部分には対応する参照符号を付し、説明を省略する。
およびそれらを主成分とする化合物(例 CoWP合金,CoWB合金,NiWP合金,TiN,TaN,WN)などを使うことが可能である。
先の各実施形態は、主に回路基板や配線基板などに関連して説明したが、先にも述べたように各実施形態はLSIなどの半導体集積回路装置に対しても適用が可能である。
2,3,4,5,6,7 層間絶縁膜
3A,4A,6A ランド
3B,4B,6B 金属膜
3C,5A Cuビアプラグ
10A〜10D 配線パタ―ン
10a〜10d,13,43,63,83 バリアメタル膜
11 拡散バリア膜
12,22,42,62,82 絶縁膜
12A〜12E,42A,42B,62A,62B 配線溝
14,44,64 Cuシード層
15,15A,15B,45A,45B.65A,65B,85A Cu層
15WA,15WC,15WE Cu配線パタ―ン
15PB,15PD Cuビアプラグ
45a,65a Cu層周辺部
45b,65b Cu層主部
46A,66,86A 研磨ストッパ
80 多層配線基板
81,87 キャップ膜
101 シリコン基板
101A 素子領域
101I 素子分離領域
101P ウェル
101a〜101d 拡散領域
102 ゲート絶縁膜
103 ゲート電極
103W1,103W2 側壁絶縁膜
104 絶縁膜
105,108 層間絶縁膜
105A,108A Cu太幅パタ―ン
105B,108B Cu微細パタ―ン
105P,108P Cuビアプラグ
105b,108b バリアメタル膜
107,110 SiCキャップ膜
A,B 領域
CH チャネル領域
Claims (7)
- 第1の絶縁膜と、
前記第1の絶縁膜の表面に形成された配線溝と、
Cuよりなり前記配線溝を充填する配線パタ―ンと、
前記配線パタ―ンの表面に形成され、CoまたはWよりなりCuよりも大きな弾性率を有し20〜200nmの膜厚の金属膜と、
前記第1の絶縁膜上に形成された第2の絶縁膜と、
Cuよりなり、前記第2の絶縁膜中に形成され、前記金属膜とコンタクトするビアプラグと、
を備え、
前記ビアプラグに蓄積される応力が90MPa未満であることを特徴とする電子装置。 - 前記配線パタ―ンは、前記第1の絶縁膜の表面と一致する表面を有し、前記金属膜の周囲に前記配線パタ―ンの表面が露出することを特徴とする請求項1記載の電子装置。
- 前記金属膜は、前記第1の絶縁膜の表面と一致する表面を有することを特徴とする請求項1記載の電子装置。
- 第1の絶縁膜中に配線溝を形成する工程と、
前記第1の絶縁膜上に前記配線溝を充填してCu層を形成する工程と、
前記Cu層上に、CoまたはWよりなりCuよりも大きな弾性率を有し20〜200nmの膜厚の金属膜を堆積する工程と、
前記金属膜をストッパに、前記Cu層を化学機械研磨する工程と、
前記第1の絶縁膜上に第2の絶縁膜を、前記金属膜を覆うように形成する工程と、
前記第2の絶縁膜中に、前記金属膜にコンタクトしてCuビアプラグを形成する工程と、
を含み、
前記Cuビアプラグに蓄積される応力が90MPa未満であることを特徴とする電子装置の製造方法。 - 前記Cu層を形成する工程は、前記配線溝中においてCu層の表面が前記第1の絶縁膜の表面に略一致するように実行されることを特徴とする請求項4記載の電子装置の製造方法。
- 第1の絶縁膜上にレジスト開口部を有するレジスト膜を形成する工程と、
前記レジスト膜をマスクに、前記レジスト開口部中にCu配線パタ―ンをメッキ法により形成する工程と、
前記レジスト膜上に前記Cu配線パタ―ンを覆って、Cuよりも大きな弾性率を有する金属膜を形成する工程と、
前記レジスト膜を、前記レジスト膜上の前記金属膜共々リフトオフして除去する工程と、
前記第1の絶縁膜上に第2の絶縁膜を、前記Cu配線パタ―ンおよび前記金属膜を覆って形成する工程と、
前記第2の絶縁膜中に前記金属膜にコンタクトしてCuビアプラグを形成する工程と、
を含むことを特徴とする電子装置の製造方法。 - 前記メッキ法によりCu配線パタ―ンを形成する工程は、前記第1の絶縁膜上に形成されたCu膜をシード層として実行され、前記リフトオフ工程の後、前記シード層を前記第1の絶縁膜の表面から、前記Cu配線パタ―ンおよび前記金属膜をマスクに除去する工程を含むことを特徴とする請求項6記載の電子装置の製造方法。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011228333A JP5857615B2 (ja) | 2011-10-17 | 2011-10-17 | 電子装置およびその製造方法 |
TW101133464A TWI555090B (zh) | 2011-10-17 | 2012-09-13 | 電子裝置及用於製造其之方法 |
US13/613,167 US20130093092A1 (en) | 2011-10-17 | 2012-09-13 | Electronic device and method for producing same |
DE102012217198A DE102012217198A1 (de) | 2011-10-17 | 2012-09-24 | Elektronische Vorrichtung und Verfahren zum Herstellen derselben |
CN201210370333.4A CN103050477B (zh) | 2011-10-17 | 2012-09-28 | 电子器件及其制造方法 |
KR1020120111547A KR101366520B1 (ko) | 2011-10-17 | 2012-10-08 | 전자 장치 및 그 제조 방법 |
US15/392,537 US20170110369A1 (en) | 2011-10-17 | 2016-12-28 | Electronic device and method for producing same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011228333A JP5857615B2 (ja) | 2011-10-17 | 2011-10-17 | 電子装置およびその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2013089736A JP2013089736A (ja) | 2013-05-13 |
JP5857615B2 true JP5857615B2 (ja) | 2016-02-10 |
Family
ID=47990876
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011228333A Expired - Fee Related JP5857615B2 (ja) | 2011-10-17 | 2011-10-17 | 電子装置およびその製造方法 |
Country Status (6)
Country | Link |
---|---|
US (2) | US20130093092A1 (ja) |
JP (1) | JP5857615B2 (ja) |
KR (1) | KR101366520B1 (ja) |
CN (1) | CN103050477B (ja) |
DE (1) | DE102012217198A1 (ja) |
TW (1) | TWI555090B (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014069662A1 (ja) * | 2012-11-05 | 2014-05-08 | 大日本印刷株式会社 | 配線構造体 |
US9153479B2 (en) | 2013-03-11 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of preventing a pattern collapse |
US9793212B2 (en) | 2015-04-16 | 2017-10-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structures and methods of forming same |
KR102493463B1 (ko) * | 2016-01-18 | 2023-01-30 | 삼성전자 주식회사 | 인쇄회로기판, 이를 가지는 반도체 패키지, 및 인쇄회로기판의 제조 방법 |
US9721889B1 (en) | 2016-07-26 | 2017-08-01 | Globalfoundries Inc. | Middle of the line (MOL) metal contacts |
US9875958B1 (en) * | 2016-11-09 | 2018-01-23 | International Business Machines Corporation | Trace/via hybrid structure and method of manufacture |
US10276428B2 (en) * | 2017-08-28 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of fabricating semiconductor package |
US11158573B2 (en) * | 2018-10-22 | 2021-10-26 | Invensas Bonding Technologies, Inc. | Interconnect structures |
JP7244394B2 (ja) * | 2019-09-18 | 2023-03-22 | 株式会社東芝 | デジタルアイソレータ |
US11444029B2 (en) * | 2020-02-24 | 2022-09-13 | International Business Machines Corporation | Back-end-of-line interconnect structures with varying aspect ratios |
US20220084948A1 (en) * | 2020-09-17 | 2022-03-17 | Nanya Technology Corporation | Semiconductor structure and manufacturing method thereof |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5362669A (en) * | 1993-06-24 | 1994-11-08 | Northern Telecom Limited | Method of making integrated circuits |
KR0155451B1 (ko) * | 1995-02-13 | 1998-12-15 | 김규용 | 전자부품삽입기의 프린트기판 받침장치 |
JP3647631B2 (ja) * | 1997-07-31 | 2005-05-18 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
JP2000003912A (ja) * | 1998-06-16 | 2000-01-07 | Hitachi Ltd | 半導体装置の製造方法および半導体装置 |
US6017803A (en) * | 1998-06-24 | 2000-01-25 | Chartered Semiconductor Manufacturing, Ltd. | Method to prevent dishing in chemical mechanical polishing |
JP2001060589A (ja) * | 1999-08-20 | 2001-03-06 | Matsushita Electronics Industry Corp | 半導体装置の製造方法 |
JP3319513B2 (ja) * | 1999-09-02 | 2002-09-03 | 日本電気株式会社 | 銅配線の形成方法 |
JP2001284351A (ja) | 2000-03-29 | 2001-10-12 | Hitachi Ltd | 半導体装置の製造方法 |
KR20020095715A (ko) * | 2001-06-15 | 2002-12-28 | 삼성전자 주식회사 | 이중금속막을 갖는 반도체 소자의 금속배선구조 및 그의형성방법 |
JP2003068848A (ja) * | 2001-08-29 | 2003-03-07 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP3540302B2 (ja) * | 2001-10-19 | 2004-07-07 | Necエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
KR100482180B1 (ko) * | 2002-12-16 | 2005-04-14 | 동부아남반도체 주식회사 | 반도체 소자 제조방법 |
JP2004273700A (ja) * | 2003-03-07 | 2004-09-30 | Renesas Technology Corp | 半導体装置及びその製造方法 |
EP1610376B1 (en) * | 2003-03-28 | 2014-10-15 | Fujitsu Semiconductor Limited | Semiconductor device |
US6927113B1 (en) * | 2003-05-23 | 2005-08-09 | Advanced Micro Devices | Semiconductor component and method of manufacture |
JP2005203476A (ja) * | 2004-01-14 | 2005-07-28 | Oki Electric Ind Co Ltd | 半導体装置の配線構造及びその製造方法 |
JP4178295B2 (ja) * | 2004-07-14 | 2008-11-12 | 富士通マイクロエレクトロニクス株式会社 | 銅からなる配線を有する半導体装置及びその製造方法 |
JP4351595B2 (ja) | 2004-07-23 | 2009-10-28 | 富士通株式会社 | 銅の配線層を形成する方法 |
JP2006156592A (ja) * | 2004-11-26 | 2006-06-15 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
TWI330863B (en) * | 2005-05-18 | 2010-09-21 | Megica Corp | Semiconductor chip with coil element over passivation layer |
US8193087B2 (en) * | 2006-05-18 | 2012-06-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process for improving copper line cap formation |
-
2011
- 2011-10-17 JP JP2011228333A patent/JP5857615B2/ja not_active Expired - Fee Related
-
2012
- 2012-09-13 TW TW101133464A patent/TWI555090B/zh not_active IP Right Cessation
- 2012-09-13 US US13/613,167 patent/US20130093092A1/en not_active Abandoned
- 2012-09-24 DE DE102012217198A patent/DE102012217198A1/de not_active Withdrawn
- 2012-09-28 CN CN201210370333.4A patent/CN103050477B/zh not_active Expired - Fee Related
- 2012-10-08 KR KR1020120111547A patent/KR101366520B1/ko not_active IP Right Cessation
-
2016
- 2016-12-28 US US15/392,537 patent/US20170110369A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20170110369A1 (en) | 2017-04-20 |
KR20130041730A (ko) | 2013-04-25 |
KR101366520B1 (ko) | 2014-02-27 |
TW201318066A (zh) | 2013-05-01 |
DE102012217198A1 (de) | 2013-04-18 |
US20130093092A1 (en) | 2013-04-18 |
JP2013089736A (ja) | 2013-05-13 |
CN103050477A (zh) | 2013-04-17 |
TWI555090B (zh) | 2016-10-21 |
CN103050477B (zh) | 2016-03-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5857615B2 (ja) | 電子装置およびその製造方法 | |
KR100387255B1 (ko) | 반도체 소자의 금속 배선 형성 방법 | |
US6878632B2 (en) | Semiconductor device having a conductive layer with a cobalt tungsten phosphorus coating and a manufacturing method thereof | |
US20040004288A1 (en) | Semiconductor device and manufacturing method of the same | |
JP2004343125A (ja) | 金属配線及び金属抵抗を含む半導体素子並びにその製造方法 | |
JP2009026989A (ja) | 半導体装置及び半導体装置の製造方法 | |
US7351652B2 (en) | Method of manufacturing semiconductor device | |
US6372616B1 (en) | Method of manufacturing an electrical interconnection of a semiconductor device using an erosion protecting plug in a contact hole of interlayer dielectric layer | |
JP5691253B2 (ja) | 配線構造の形成方法および配線構造 | |
US6780760B2 (en) | Methods for manufacturing semiconductor devices | |
KR20080047541A (ko) | 반도체 장치 상에 캐핑 레이어를 형성하는 방법 | |
KR100465761B1 (ko) | 탄탈륨 질화막을 포함하는 반도체 배선 구조 및 그 형성방법 | |
JP3628903B2 (ja) | 半導体装置の製造方法 | |
JP2001118923A (ja) | 半導体装置及び半導体装置の製造方法 | |
KR100545196B1 (ko) | 반도체 소자의 금속 배선 형성 방법 | |
JP2005142330A (ja) | 半導体装置の製造方法及び半導体装置 | |
KR100834283B1 (ko) | 금속 배선 형성 방법 | |
KR100579856B1 (ko) | 반도체 소자의 금속 배선 형성 방법 | |
KR100641994B1 (ko) | 반도체 장치 및 그의 형성방법 | |
KR100744239B1 (ko) | 반도체 소자의 금속 배선 형성 방법 | |
US20040132280A1 (en) | Method of forming metal wiring in a semiconductor device | |
KR20000033431A (ko) | 구리 배선 형성방법 | |
KR20030080552A (ko) | 플러그 형성 방법 및 이 플러그를 갖는 반도체 소자 | |
KR20050045394A (ko) | 반도체 소자의 금속배선 형성 방법 | |
KR20100078357A (ko) | 구리 금속 배선 형성 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20140603 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20150206 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20150210 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150305 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20151117 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20151130 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5857615 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |