WO2023122697A1

WO2023122697A1 - Controlled grain growth for bonding and bonded structure with controlled grain growth

Info

Publication number: WO2023122697A1
Application number: PCT/US2022/082186
Authority: WO
Inventors: Jeremy Alfred Theil; Cyprian Emeka Uzoh; Guilian Gao
Original assignee: Adeia Semiconductor Bonding Technologies Inc.
Priority date: 2021-12-23
Filing date: 2022-12-21
Publication date: 2023-06-29

Abstract

Disclosed is an element including a conductive feature at a contact surface of the element and a nonconductive region at the contact surface in which the conductive feature is at least partially embedded. The contact feature includes a conductive material and an amount of impurities at a grain boundary of the conductive material. The impurities have a non-alloying material that does not form an alloy with the conductive material at a bonding temperature.

Description

CONTROLLED GRAIN GROWTH FOR BONDING AND BONDED STRUCTURE

WITH CONTROEEED GRAIN GROWTH

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 63/293,300, filed December 23, 2021, titled “CONTROLLED GRAIN GROWTH FOR BONDING AND BONDED STRUCTURE WITH CONTROLLED GRAIN GROWTH,” the entire contents of which are hereby incorporated by reference herein in their entirety and for all purposes.

BACKGROUND

Field

[0002] The field relates to a conductive feature with controlled grain growth.

Description of the Related Art

[0003] Semiconductor elements, such as integrated device dies or chips, may be mounted or stacked on other elements. For example, a semiconductor element can be mounted to a carrier, such as a package substrate, an interposer, a reconstituted wafer or element, etc. As another example, a semiconductor element can be stacked on top of another semiconductor element, e.g., a first integrated device die can be stacked on a second integrated device die. Each of the semiconductor elements can have conductive pads for mechanically and electrically bonding the semiconductor elements to one another. There is a continuing need for improved methods for forming the conductive pads for reliable bonding.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The detailed description is set forth with reference to the accompanying figures. The use of the same reference numbers in different figures indicates similar or identical items.

[0005] For this discussion, the devices and systems illustrated in the figures are shown as having a multiplicity of components. Various implementations of devices and/or systems, as described herein, may include fewer components and remain within the scope of the disclosure. Alternatively, other implementations of devices and/or systems may include additional components, or various combinations of the described components, and remain within the scope of the disclosure.

[0006] These aspects and others will be apparent from the following description of preferred embodiments and the accompanying drawings, which are meant to illustrate and not to limit the invention, wherein:

[0007] Figure 1A is an image of metal (e.g., copper) grain structures that are representative of a conductive feature with relatively low or minimum impurity concentrations, shown after plating, with impurities schematically illustrated, according to one embodiment.

[0008] Figure IB is a representation of the grain structure shown in Figure 1A, but shown just before annealing, according to one embodiment.

[0009] Figure 1C is a representation of the grain structure shown in Figure 1A, but shown after annealing, according to one embodiment.

[0010] Figure 2A is an image of metal (e.g., copper) grain structures that are representative of a conductive feature having impurity concentrations selected to manage grain growth, shown after plating, with impurities schematically illustrated, according to one embodiment.

[0011] Figure 2B is a representation of the grain structure shown in Figure 2A, but shown just before annealing, according to one embodiment.

[0012] Figure 2C is a representation of the grain structure shown in Figure 2A, but shown after annealing, according to one embodiment.

[0013] Figure 3 A is an image of metal (e.g., copper) grain structures that are representative of a conductive feature with relatively high impurity concentrations, shown after plating, with impurities schematically illustrated, according to one embodiment.

[0014] Figure 3B is a representation of the grain structure shown in Figure 3A, but shown just before annealing, according to one embodiment.

[0015] Figure 3C is a representation of the grain structure shown in Figure 3A, but shown after annealing, according to one embodiment.

[0016] Figures 4A-4D present a series of schematic side sectional views that show a multi-step method by which an element can be formed, according to one embodiment.

[0017] Figures 4E is a schematic side sectional view of a first and second element prepared to be directly bonded, according to one embodiment. [0018] Figures 4F is a schematic side sectional view of the first and second elements from Figure 4E after being directly bonded, according to one embodiment.

DETAILED DESCRIPTION

[0019] The present disclosure describes methods of controlling metallic grain growth of conductive features (e.g., conductive pads, through-substrate vias (TSVs), etc.) in elements, such as microelectronic elements. Various embodiments disclosed herein can be advantageous for direct metal bonding, such as direct hybrid bonding. For example, as schematically demonstrated in Figures 4E and 4F, two or more semiconductor elements 102, 152 (such as integrated device dies, wafers, etc.) may be stacked on or bonded to one another to form a bonded structure 100. Conductive features 206 of one element 102 may be electrically connected to corresponding conductive features 156 of another element (e.g., a second element 156). Any suitable number of elements can be stacked in the bonded structure 100. The methods and conductive feature structures described herein can be useful in other contexts as well.

[0020] In some embodiments, the elements (e.g., the first element 102 and the second element 152) are directly bonded to one another without an adhesive. In various embodiments, a non-conductive (e.g., semiconductor or inorganic dielectric) region 130 of a first element 102 can be directly bonded to a corresponding non-conductive (e.g., semiconductor or inorganic dielectric) region 160 of a second element 152 without an adhesive. Although not shown, the nonconductive layers can be provided on a bulk device, such as a semiconductor substrate having devices formed therein. In various embodiments, a conductive feature 206 (e.g., a metal pad, a contact pad, a TSV, etc.) of the first element 102 can be directly bonded to a corresponding conductive feature 156 (e.g., a metal pad, a contact pad, a TSV, etc.) of the second element 152 without an adhesive. The non-conductive region 130 can be referred to as a nonconductive bonding region or bonding layer of the first element 102. In some embodiments, the non-conductive region 130 of the first element 102 can be directly bonded to the corresponding non-conductive region 160 of the second element 152 using bonding techniques without an adhesive using the direct bonding techniques disclosed at least in U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes. In other applications, in a bonded structure 100, a non-conductive region 130 of a first element 102 can be directly bonded to a conductive feature 156 of a second element 152, such that a conductive feature 206 of the first element 102 is intimately mated with a non-conductive region 160 of the second element 152.

[0021] In various embodiments, direct bonds can be formed without an intervening adhesive. For example, semiconductor or dielectric bonding surfaces (e.g., a nonconductive surface 136 of a first nonconductive region 130 of a first element 102 and a nonconductive surface 146 of a second nonconductive region 160 of a second element 152) can be polished to a high degree of smoothness. The bonding nonconductive surfaces can be cleaned and exposed to a plasma to activate the surfaces. In some embodiments, the bonding nonconductive surfaces can be terminated with a species after activation or during activation (e.g., during the plasma). Without being limited by theory, in some embodiments, the activation process can be performed to break chemical bonds at the bonding nonconductive surface, and the termination process can provide additional chemical species at the bonding nonconductive surface that improves the bonding energy during direct bonding. In some embodiments, the activation and termination are provided in the same step, e.g., a plasma or wet etchant to activate and terminate the nonconductive surfaces. In other embodiments, the bonding nonconductive surface can be terminated in a separate treatment to provide the additional species for direct bonding. In various embodiments, the terminating species can comprise nitrogen. Further, in some embodiments, the bonding nonconductive surfaces can be exposed to fluorine. For example, there may be one or multiple fluorine peaks near layer and/or bonding nonconductive interfaces. Thus, in the directly bonded structures, the bonding interface between two non-conductive regions 130, 160 can comprise a very smooth interface with higher nitrogen content and/or fluorine peaks at the bonding interface. Additional examples of activation and/or termination treatments may be found throughout U.S. Patent Nos. 9,564,414; 9,391,143; and 10,434,749, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes.

[0022] In various embodiments, conductive contact features 206 (e.g., contact pads, TSVs, etc.) of the first element 102 can also be directly bonded to corresponding conductive features 156 (e.g., contact pads, TSVs, etc.) of the second element 152. For example, a direct hybrid bonding technique can be used to provide conductor-to-conductor direct bonds along a bond interface that includes covalently direct bonded dielectric-to- dielectric surfaces (e.g., nonconductive surface 136 of a first nonconductive region 130 of a first element 102 and nonconductive surface 146 of a second nonconductive region 160 of a second element 152), prepared as described above. In various embodiments, the conductor- to-conductor (e.g., conductive feature 206 to conductive feature 156) direct bonds (e.g., bonds between a conductive surface 138 of a first conductive feature 206 of a first element 102 and a conductive surface 148 of a second conductive feature 156 of a second element 152) and the dielectric-to-dielectric hybrid bonds can be formed using the direct bonding techniques disclosed at least in U.S. Patent Nos. 9,716,033 and 9,852,988, the entire contents of each of which are incorporated by reference herein in their entirety and for all purposes. The bonded structures 100 described herein can also be useful for direct metal bonding without nonconductive region bonding, or for other bonding techniques.

[0023] In some embodiments, inorganic dielectric bonding surfaces (e.g., nonconductive surfaces 136, 146) can be prepared and directly bonded to one another without an intervening adhesive as explained above. Conductive contact pads, such as first and second conductive features 206, 156 (which may be surrounded by nonconductive dielectric field regions, such as first and second nonconductive regions 130, 160) may also directly bond to one another without an intervening adhesive. In some embodiments, the respective conductive surfaces 138, 148 of contact pads (e.g., first and second conductive features 206, 156) can be recessed below exterior (e.g., upper) nonconductive surfaces 136, 146 of the dielectric field or nonconductive regions 130, 160, for example, recessed by less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, for example, recessed in a range of 2 nm to 20 nm, or in a range of 4 nm to 10 nm. The nonconductive regions 130, 160 can be directly bonded to one another without an adhesive at room temperature in some embodiments and, subsequently, the bonded structure 100 can be annealed. Upon annealing, the conductive features 206, 156 (which can be, for example contact pads, TSVs, etc.) can expand with respect to the nonconductive regions 130, 160 and contact one another to form a metal-to-metal direct bond. Beneficially, the use of hybrid bonding techniques, such as Direct Bond Interconnect, or DBI®, available commercially from Adeia of San Jose, CA, can enable high density of pads (e.g., conductive features 206, 156) connected across the direct bond interface (e.g., small or fine pitches for regular arrays). In various embodiments, the conductive features 206, 156 can comprise copper, although other metals may be suitable.

[0024] Thus, in direct bonding processes, a first element 102 can be directly bonded to a second element 152 without an intervening adhesive. In some arrangements, the first element 102 can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the first element 102 can comprise a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element 152 can comprise a singulated element, such as a singulated integrated device die. In other arrangements, the second element 152 can comprise a carrier or substrate (e.g., a wafer).

[0025] As explained herein, the first and second elements 102, 152 can be directly bonded to one another without an adhesive, which is different from a deposition process. The first and second elements 102, 152 can accordingly comprise non-deposited elements. Further, directly bonded structures (e.g., bonded structure 100), unlike deposited layers, can include a defect region along the bond interface in which nanovoids are present. The nanovoids may be formed due to activation of the bonding surfaces (e.g., exposure to a plasma). As explained above, the bond interface can include concentration of materials from the activation and/or last chemical treatment processes. For example, in embodiments that utilize a nitrogen plasma for activation, a nitrogen peak can be formed at the bond interface. In embodiments that utilize an oxygen plasma for activation, an oxygen peak can be formed at the bond interface. In some embodiments, the bond interface can comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride, with levels of nitrogen present at the bonding interface that are indicative of nitrogen termination of at least one of the elements prior to direct bonding. In some embodiments, nitrogen and nitrogen related moieties may not be present at the bonding interface. As explained herein, the direct bond can comprise a covalent bond, which is stronger than van Der Waals bonds. The bonding layers can also comprise polished surfaces that are planarized to a high degree of smoothness.

[0026] In various embodiments, the metal-to-metal bonds between the contact pads (e.g., conductive features 206, 156) can be joined such that copper grains 116 grow into each other across the bond interface. In some embodiments, the copper can have grains 116 oriented vertically along the 111 crystal plane for improved copper diffusion across the bond interface. In some embodiments, the misorientation of 111 crystal planes in the conductive material may be in a range of ± 30° with respect to the vertical direction from the conductive surface of the conductive material (e.g., the conductive surfaces 138, 148 of the conductive features 206, 156 of the first and second elements 102, 152). In some embodiments, the crystal misorientation can be in a range of ± 20°, or in a range of ± 15°, with respect to the vertical direction. The bond interface can extend substantially entirely to at least a portion of the bonded contact pads (e.g., conductive features 206, 156), such that there is substantially no gap between the nonconductive bonding regions (e.g., the nonconductive regions 130, 160) at or near the bonded contact pads (e.g., the conductive features 206, 156). In some embodiments, a barrier layer may be provided under the conductive features 206, 156 (e.g., which may include copper or copper alloy). In other embodiments, however, there may be no barrier layer under the conductive features 206, 156, for example, as described in US 2019/0096741, which is incorporated by reference herein in its entirety and for all purposes.

[0027] Annealing temperatures (also referred to herein as “bonding temperature”) and annealing durations for forming the metal-to-metal direct bond (e.g., the direct bond between the conductive surface 138 of the first conductive feature 206 of the first element 102 and the conductive surface 148 of the second conductive feature 156 of the second element 152) can affect the consumption of thermal budget by the annealing. Bonding temperatures can, for example, be in a range of 100°C to 250°C, 100°C to 200°C, 150°C to 200°C, or 100°C to 150°C. It may be desirable to lower the annealing temperature and/or annealing duration to minimize consumption of the thermal (energy) budget. Surface diffusion of atoms along the 111 crystal plane (<111>) can be 3 to 4 orders of magnitude faster than along the 100 or 110 crystal planes. Also, a metal (e.g., Cu) with grains oriented along a 111 crystal plane can have a higher surface mobility as compared to conventional back end of line (BEOL) copper. Further, low-temperature direct metal-to-metal bonding (which can include bonding that occurs when a bonding temperature is at or below 250°C) is enabled by creep on the 111 crystal plane of Cu of the nano-texture surface. Therefore, it can be advantageous to have the 111 crystal plane on the bonding surface (e.g., contact surfaces 104, 154) in order to shorten the annealing time and/or reduce the annealing temperature for direct bonding (e.g., direct hybrid bonding). In some embodiments, the advantage to have the 111 crystal plane can be pronounced especially at lower temperatures because the metal surface diffusion (e.g., Cu surface diffusion) also slows down when the annealing temperature is reduced. Accordingly, in various embodiments disclosed herein, a crystal structure can have grains oriented vertically along the 111 crystal plane to enhance metal diffusion (e.g., copper diffusion) during direct bonding.

[0028] A metal layer can be formed with a process selected to plate a copper (Cu) layer having Cu in the 111 crystal orientation. The Cu layer may be deposited from a non- superfilling or super-filling electroplating bath, for example, with plating chemistry selected to optimize efficient filling of voids (e.g., vias, trenches) in the substrate, rather than to optimize the direct metal-to-metal bonding to occur during direct hybrid bonding. Subsequent metal treatment, described herein below, can facilitate subsequent bonding such that any desirable plating chemistry can be employed to optimize for other considerations, such as filling noted above. The micro structure (e.g., a grain size) of the deposited or coated metal layer (e.g., the conductive elements 206, 156) may be stabilized before the metal planarization process (e.g., chemical mechanical polishing, or CMP). The microstructure of the metal layer (e.g., the conductive elements 206, 156) can be stabilized for example by an annealing step, separate from the annealing step of the direct hybrid bonding that occurs later. In some embodiments, the plated metal can be partially stabilized before the CMP operation to form the bonding surface (e.g., contact surfaces 104, 154). In some other embodiments, the plated metal may be completely stabilized before the CMP operation.

[0029] As described above, the contact pads (e.g., conductive features 206, 156) can expand with respect to the nonconductive bonding regions (e.g., nonconductive regions 130 and 160) and contact one another to form a metal-to-metal direct bond (e.g., a bond between contact surfaces 104, 154). For example, the expansion of the contact pads (e.g., conductive features 206, 156) can be caused primarily by thermal expansion of a material (e.g., copper) of the contact pads relative to the nonconductive bonding regions (e.g., nonconductive regions 130 and 160). Grain growth of the contact pads (e.g., conductive features 206, 156) can at least partially cause the contact pads to expand. It can be beneficial for the grain growth to occur when the contact pads (e.g., conductive features 206, 156) are annealed to expand the contact pads when bonding the contact pads to one another, for example by bonding contact surfaces 104, 154. However, the grain growth of the contact pads (e.g., conductive features 206, 156) can occur prior to bonding or annealing. For example, in a material such as copper, diffusion between grains 116 of copper can cause grain growth at a room temperature. If grains 116 grow at room temperature, then a higher anneal temperature might be required to induce further grain growth than would have otherwise been required had the grains 116 not grown at room temperature. This is because grown grains can be in a more stable state. Grain growth and/or expansion of the contact pads (e.g., conductive features 206, 156) can be temperature driven. For a reliable bonding between the contact pads (e.g., conductive features 206, 156), it can be beneficial to minimize the grain growth prior to bonding or annealing to preserve potential energy of the material of the contact pads until the bonding or annealing in order for the material to sufficiently expand when bonding or annealing. Said differently, direct hybrid bonding can be performed by causing contact pads (e.g., conductive features 206, 156) to expand during an anneal, and this expansion can be driven in part by grain growth. One way to complete this anneal in a way that can reduce impacts on a thermal budget can be to reduce or minimize the grain growth (and corresponding release of potential energy) that would occur at room temperature. Such a reduction of grain growth at room temperature maintains the potential energy of the conductive material 108 until the anneal at a bonding temperature. In such a configuration, the potential energy released from grain growth can contribute to driving the direct bonding between the contact pads (e.g., conductive features 206, 156) during the anneal, instead of being released and lost in ambient conditions before the anneal.

[0030] The above phenomena can be described at least in part by the following equations.

[0031] wherein M is grain boundary mobility; ks is drag coefficient from pinning; ks is Boltzmann constant; A is grain boundary area; D is diffusion coefficient; f_r is drag force; T is temperature; t is time; AE is interaction energy required to overcome drag; and h-bar is grain boundary displacement.

[0032] Various embodiments disclosed herein relate to forming an element (e.g., element 102) with a conductive pad (e.g., conductive feature 206) that has a direct bonding surface (e.g., contact surface 104) having impurities 120 at a grain boundary 118 of a conductive material 108 (e.g., copper) of the conductive pad (e.g., conductive feature 206) to prevent or minimize grain growth of the conductive material 108 (e.g., copper) before bonding or annealing. The impurities 120 can be disposed at grain boundaries 118 within the conductive material 108 (e.g., copper) of the contact pads (e.g., conductive feature 206).

[0033] Figures 1A-1C illustrate the morphology evolution of the microstructure of a contact surface of a conductive feature 106 of an element (e.g., a semiconductor element), when there is a relatively low or minimum level of impurities 120 at grain boundaries 118 soon after plating. Figures 1A-1C illustrates how the microstructure of the contact surface can evolve as the conductive feature 106 is processed during a direct hybrid bonding procedure. Figure 1A illustrates the microstructure (e.g., grain 116 sizes and shapes) of the contact surface of the conductive feature 106 soon after plating. Figure IB illustrates the microstructure of the same contact surface of the conductive feature 106, but just before an annealing process after undergoing partial room temperature grain growth. And Figure 1C illustrates the microstructure of the same contact surface of the conductive feature 106 after an annealing process at a bonding temperature. The bonding temperature can, for example, be in a range of 100°C to 250°C, 100°C to 200°C, 150°C to 200°C, or 100°C to 150°C. Difference(s) in microstructure between Figures 1A and IB is understood to be at least partially the result of the conductive feature 106 being exposed to ambient conditions (e.g., at room temperature) between plating and the anneal. Difference(s) in micro structure between Figures IB and 1C is understood to be at least partially the result of the conductive feature 106 being annealed at a bonding temperature.

[0034] In Figures 1A-1C, the conductive feature 106 can comprise a conductive material 108 and a non-alloying material 110. The non-alloying material 110 does not form an alloy with the conductive material 108 at the bonding temperature. The conductive material 108 can comprise copper or gold or silver or their respective alloys. The conductive material 108 can form grains 116. Grain boundaries 118 can form at the interfaces between grains 116 of conductive material 108. The non-alloying material 110 can, for example, comprise a metallic compound, a metal oxide, a non-metallic compound, a non-metal oxide, a chemical compound, and/or a refractory material - as described further herein. The non-alloying material 110 can form impurities 120 within the conductive material 108 of the conductive feature 106. Each impurity 120 can diffuse or migrate throughout the conductive material 108 and can be within a grain 116 or along a grain boundary 118 or accumulate around the grain boundaries 118. When a sufficient amount of impurities 120 accumulate along grain boundaries 118, the impurities 120 can “pin” the grains 116 and suppress grain growth. An additional amount of energy can be introduced to induce pinned grains 116 to grow. This may include, for example, annealing and exposing the microstructure of the grains 116 with accumulated impurities 120 to higher temperatures for an adequate length of time. The higher temperatures increase the mobility of the atoms within the grain 116 and especially along the grain boundaries 118. The increased mobility of the grain boundaries 118 leads to grain growth and increase in the size of the grains 116. The word “pin” does not mean that the pinned grain boundaries 118 are completely immobile; rather, the impurity 120 may exert a force (e.g., a drag or pinning force) that can reduce the grain boundary’s 118 mobility, thereby slowing grain growth. In short, more impurities 120 along grain boundaries 118 increases pinning, which can decrease grain growth.

[0035] In Figures 1A-1C, the conductive feature 106 includes a minimum level of impurities 120, which means the grains 116 of conductive material 108 are minimally pinned. Figure 1A illustrates the very fine grains 116 of conductive material 108 that can result immediately after plating. Figure 1A also illustrates a minimal amount of impurities 120 within the conductive material 108. In part because of the minimal level of impurities 120, the grains 116 within the conductive feature 106 are not pinned and can grow even in ambient conditions (e.g., at room temperature) before annealing, as shown in Figure IB. This grain growth that can occur in ambient conditions can be referred to as a “natural anneal,” which is different from an anneal at a bonding temperature. Figure 1C illustrates that the grains 116 within the conductive feature 106 can continue to grow during an anneal at a bonding temperature. [0036] Figures 2A-2C show the morphology evolution of the microstructure of a contact surface 104 (shown in Figure 4D) of a conductive feature 206 within an element 102 (shown in Figure 4D), according to various embodiments, when there is a level of impurities 120 at grain boundaries 118 selected to manage grain growth, soon after plating. The amount of impurities 120 at the grain boundaries 118 shown in Figure 2 A is higher than that shown in Figure 1A. Figures 2A-2C show how the microstructure of the contact surface 104 (shown in Figure 4D) can evolve as the conductive feature 206 is processed, according to various embodiments. Figure 2A shows the microstructure (e.g., grain 116 sizes and shapes) of the contact surface 104 (shown in Figure 4D) of the conductive feature 206 soon after plating, according to various embodiments. Figure 2B shows the micro structure of the same contact surface 104 (shown in Figure 4D), but just before an anneal, according to various embodiments. And Figure 2C shows the micro structure of the same contact surface 104 (shown in Figure 4D) after an anneal at a bonding temperature, according to various embodiments. The bonding temperature can, for example, be in a range of 100°C to 350°C, 100°C to 250°C, 100°C to 200°C, 150°C to 200°C, or 100°C to 150°C. Difference(s) in microstructure between Figures 2A and 2B is understood to be at least partially the result of the conductive feature 206 being exposed to ambient conditions (e.g., at room temperature) between plating and the anneal. Difference(s) in micro structure between Figures 2B and 2C is understood to be at least partially the result of the conductive feature 206 being annealed at a bonding temperature.

[0037] In Figures 2A-2C, the conductive feature 206 can comprise a conductive material 108 and a non-alloying material 110, according to various embodiments. The nonalloying material 110 does not form an alloy with the conductive material 108 at the bonding temperature. The conductive material 108 can comprise copper or gold or silver or their alloys, according to various embodiments. The conductive material 108 can form grains 116. Grain boundaries 118 can form at the interfaces between grains 116 of conductive material 108. The non-alloying material 110 can, for example, comprise a metallic compound, a metal oxide, a non-metallic compound, a non-metal oxide, a chemical compound, and/or a refractory material, according to various embodiments - as described further herein. The non-alloying material 110 can form impurities 120 within the conductive material 108 of the conductive feature 206. Each impurity 120 may diffuse or migrate throughout the conductive material 108 and typically accumulate along a grain boundary 118. When a sufficient amount of impurities 120 accumulate along grain boundaries 118 or around the grains 116, the impurities 120 can “pin” the grains 116 and suppress the growth of the various grains 116. An additional amount of energy can be introduced to induce pinned grains 116 to grow. One example method for unpinning the grains 116 can include exposing the pinned micro structure to higher temperatures for adequate length of times. The higher temperature increases the mobility of the atoms within the grain 116 and especially along the grain boundaries 118. The increased mobility of the grain boundaries 118 can unpin the pinned grains, thus leading to grain growth and increase in the size of the grains 116. In short, more impurities 120 along grain boundaries 118 increases pinning, which can decrease grain growth.

[0038] In Figures 2A-2C, the conductive feature 206 includes a first level of impurities 120 selected to manage grain growth, which means the grains 116 of conductive material 108 can be selectively pinned, according to various embodiments. Figure 2A shows the very fine grains 116 of conductive material 108 that can result immediately after plating. Figure 2A also illustrates an amount of impurities 120 within the conductive material 108 selected to manage grain growth. The amount of the impurities can be selected to pin the grains 116 from growing before bonding and annealing (in, e.g., ambient conditions) as shown in Figure 2B, but allow grain growth during an anneal at a bonding temperature (e.g., between 100°C and 250°C), as shown in Figure 2C. In part because of the level of impurities 120 selected to manage grain growth, the grains 116 within the conductive feature 206 are pinned sufficiently to prevent or minimize grain growth in ambient conditions (e.g., at room temperature) before annealing, as shown in Figure 2B. The presence of an amount of impurities 120 selected to manage grain growth can prevent or minimize a “natural anneal.” Figure 2C illustrates that the grains 116 within the conductive feature 206 can grow during an anneal at a bonding temperature.

[0039] An amount of impurities 120 along grain boundaries 118 selected to manage grain growth can strike a balance: there can be enough impurities 120 along grain boundaries 118 to cause enough pinning to reduce or minimize grain growth in ambient conditions (e.g., at room temperature), but not so many impurities 120 along grain boundaries 118 as to prevent or minimize grain growth at a bonding temperature, which can, for example, be in a range of 100°C to 250°C, 100°C to 200°C, 150°C to 200°C, or 100°C to 150°C. As described herein, such an amount of impurities 120 selected to manage grain growth can facilitate direct hybrid bonding by maintaining the potential energy of the conductive material 108 in ambient conditions, then permitting the grain growth that can help form a reliable direct bond between two conductive features 206, 156 of two elements 102, 152 (shown in Figure 4F) at a bonding temperature (e.g., in a range of 100°C to 250°C, 100°C to 200°C, 150°C to 200°C, or 100°C to 150°C).

[0040] Figures 3A-3C show the morphology evolution of the microstructure of a contact surface 104 (shown in Figure 4D) of a conductive feature 306 within an element 102 (shown in Figure 4D), according to various other embodiments, when there is a high level of impurities 120 at grain boundaries 118 soon after plating. The amount of impurities 120 at the grain boundaries 118 shown in Figure 3A is higher than that shown in Figure 2A. Figures 3A- 3C show how the microstructure of the contact surface 104 (shown in Figure 4D) can evolve as the conductive feature 306 is processed, according to various embodiments. Figure 3A shows the microstructure (e.g., grain 116 sizes and shapes) of the contact surface 104 (shown in Figure 4D) of the conductive feature 306 soon after plating, according to various embodiments. Figure 3B shows the microstructure of the same contact surface 104 (shown in Figure 4D) of the conductive feature 306, but just before an anneal, according to various embodiments. And Figure 3C shows the micro structure of the same contact surface 104 (shown in Figure 4D) of the conductive feature 306 after an anneal at a bonding temperature, according to various embodiments. The bonding temperature can, for example, be in a range of 100°C to 400°C, 100°C to 250°C, 100°C to 200°C, 150°C to 200°C, or 100°C to 150°C. Difference(s) in microstructure between Figures 3 A and 3B is understood to be at least partially the result of the conductive feature 306 being exposed to ambient conditions (e.g., at room temperature) between plating and the anneal. Difference(s) in microstructure between Figures 3B and 3C is understood to be at least partially the result of the conductive feature 306 being annealed at a bonding temperature.

[0041] In Figures 3A-3C, the conductive feature 306 can comprise a conductive material 108 and a non-alloying material 110, according to various embodiments. The nonalloying material 110 does not form an alloy with the conductive material 108 at the bonding temperature. The conductive material 108 can comprise copper or gold or silver or their alloys, according to various embodiments. The conductive material 108 can form grains 116. Grain boundaries 118 can form at the interfaces between grains 116 of conductive material 108. The non-alloying material 110 can, for example, comprise a material not soluble in the conductive material 108 at the bonding temperature and may comprise a metallic material, a metallic compound, a metal oxide, a non-metallic compound, a non-metal oxide, a chemical compound, and/or a refractory material, according to various embodiments - as described further herein. The non-alloying material 110 can form impurities 120 within the conductive material 108 of the conductive feature 306. Each impurity 120 can diffuse or migrate throughout the conductive material 108 and can be within a grain 116 or along a grain boundary 118. When a sufficient amount of impurities 120 are along grain boundaries 118, the impurities 120 can “pin” the grains 116, which can reduce grain growth. In short, more impurities 120 along grain boundaries 118 increases pinning, which tends to decrease grain growth. In some embodiments, the non-alloying material 110 may comprise a material having limited solubility in the conductive material 108 at the bonding temperature. For example, the solubility of the non-alloying material 110 can be less than 20% in the conductive material 108 at the bonding temperature; and less than 5% or less than 1% or less than 0.05% at room temperature.

[0042] In Figures 3A-3C, the conductive feature 306 includes a second, high level of impurities 120, which means the grains 116 of conductive material 108 can be substantially fully pinned. Figure 3A shows the very fine grains 116 of conductive material 108 that can result immediately after plating. Figure 3A also illustrates a relatively high amount of impurities 120 within the conductive material 108. The amount of impurities 120 can be selected to be high enough to cause enough pinning to prevent or minimize grain growth within the conductive feature 306, both in ambient conditions before bonding and annealing (e.g., at room temperature) as shown in Figure 3B, and also during an anneal at a bonding temperature (e.g., in a range of 100°C to 400°C, 100°C to 250°C, 100°C to 200°C, 150°C to 200°C, or 100°C to 150°C), as shown in Figure 3C. The presence of a high level of impurities 120 in conductive feature 306 can reduce or minimize both a “natural anneal” and an anneal at a bonding temperature. In short, Figure 3B shows that the sizes of grains 116 can remain similar to those shown in Figure 3A at room temperature, and Figure 3C shows that the sizes of grains 116 can remain similar to those shown in Figures 3 A and 3B, even after an anneal at a bonding temperature. Therefore, when no grain growth is wanted, the high impurity content sufficiently high to prevent grain growth can be introduced. [0043] The impurities 120 used in Figures 1A-3C can comprise non-alloying impurities 120 that do not form alloys with the conductive material 108 (e.g., copper) of the conductive feature 206. The non-alloying impurities 120 can comprise a material that is insoluble with the conductive material 108 (e.g., copper) of the conductive feature 206 at the annealing temperatures of interest (e.g., at a bonding temperature). In some embodiments that utilize copper as the conductive material 108 for the conductive feature 206, the non-alloying impurities 120 can comprise a metallic compound. In some embodiments, the non-alloying impurities 120 can comprise a metal oxide. In some embodiments, the non-alloying impurities 120 can comprise a non-metallic compound. In some embodiments, the non-alloying impurities 120 can comprise a non-metal oxide. In some embodiments, the non-alloying impurities 120 can comprise other compounds, i.e., two or more bonded chemical elements, such as ceramic materials. In some embodiments, the non-alloying impurities 120 can comprise a refractory material. A non-exhaustive list of such materials includes aluminum nitride, tantalum particles and nanoparticles, tantalum nitride particles and nanoparticles, titanium nitride particles and nanoparticles, aluminum oxide, nickel oxide particles and nanoparticles, magnesium oxide particles and nanoparticles, manganese oxide particles and nanoparticles, glass, ceramic or glass-ceramic particles and nanoparticles, silicon carbide (SiC), silicon nitride (SiN), silicon carbide-nitride (SiCN), silicon oxide, tantalum (Ta), zirconium (Zr), molybdenum (Mo), and tungsten (W).

[0044] In some embodiments, the impurities 120 can be introduced by codeposition sputtering of the impurities 120 and the conductive material 108 into cavity 122 of Figure 4B to form the structures of Figure 4C. In some embodiments, a sputtering target comprising the impurities 120 and the conductive material 108 may be sputtered into cavity 122 to form the structure of Figure 4C. In some embodiments, the impurities 120 may be introduced as a particulate material into an electroplating bath and is co-deposited into the conductive material 108 during the plating step to form the conductive material 108 in Figure 4C. In some embodiments, the impurities 120 can comprise silicon oxide (or other non-metal oxide) particles or silicon carbide (or other non-metallic compounds). In some embodiments, the non-alloying material can be introduced into the conductive material 108 of the conductive feature 206 as very fine particles (e.g., particles with a linear lateral dimension of less than 200 nm, less than 100 nm, less than 50 nm, or less than 20 nm) of the non-alloying impurities 120 into the electroplating bath, and the impurities 120 may be co-deposited with the conductive material 108 on the substrate of interest, for example, by galvanostatic or potentiostatic methods, by pulse plating or by the various combinations thereof.

[0045] In the conductive feature 106 shown in Figures 1A-1C, there can be less than 20 parts per million (ppm) of impurities 120, such as 2 ppm or 3 ppm of impurities 120. For example, the conductive feature 106 of Figure 1A can include 2 ppm to 20 ppm, 5 ppm to 20 ppm, 2 ppm to 15 ppm, or 5 ppm to 15 ppm of impurities 120. In such a conductive feature 106, grains 116 of a conductive material 108 of the conductive feature 106 can grow at room temperature. The grown grains 116 shown in Figure IB - having lower potential energy relative to the fine grains 116 shown in Figure 1A - can be in a relatively stable state such that a relatively high bonding temperature may be needed for the intimate mating of multiple conductive features 106 of multiple elements being directly bonded to one another. In some applications, a relatively low direct bonding or annealing temperature (low thermal budgets) may be preferred because of some limitation or constraint imposed by one of the elements 102, 152 being bonded (shown in Figure 4F). One example of a limitation that lowers a bonded structure’s thermal budget is when a relatively higher annealing temperature (for example higher than 250°C) is used for bonding two elements with a relatively large difference in the coefficient of thermal expansion (CTE). Such a thermal expansion mismatch between the two elements may cause defects, stress-related cracks in the bonded structure, or device degradation. In some embodiments, the CTE difference between materials in the first and second elements 102, 152 can be greater than 2ppm/°C or 5ppm/°C and in other applications can be greater than 10ppm/°C. The use of conductive features 206 with impurity amounts selected to manage grain growth (as shown, e.g., in Figures 2A-2C) can facilitate the use of elements (e.g. first and second elements 102, 152) with CTE differences that can be greater than 2ppm/°C, 5ppm/°C, or 10ppm/°C, which, as described above, are elements that are typically susceptible to thermal-related damage. This can be because the use of such conductive features 206 can reduce the thermal impact of a bonding process by, for example, reducing the bonding temperature, a bonding time, or both, of the anneal. In some embodiments, a smaller die may be bonded to a larger die, hence a bonded surface area (not shown) of the first element 102 may be smaller than a bonded surface area (not shown) of the second element 152. [0046] In the conductive feature 206 of Figures 2A-2C, the first amount of impurities 120 can be a sufficient amount of impurities 120 that can delay grain growth of the conductive material 108 of the conductive feature 206 such that a stored potential energy of the conductive material 108 due, for example, to relatively small grains 116 with relatively high atomic vacancies is maintained until the annealing process for bonding the conductive feature 206 to another conductive feature (e.g., the conductive feature 156 of the second element 152, shown in Figure 4E). The delay of the grain growth can be due to an increase in drag coefficient (k_s in the equations above). In some embodiments, the first amount of impurities 120 can enable the conductive material 108 of the conductive feature 206 to prevent or minimize grain growth at room temperature.

[0047] In the conductive feature 306 of Figures 3A-3C, the second amount of impurities 120 can be a sufficient amount of impurities 120 that can delay grain growth of the conductive material 108 of the conductive feature 306 such that the stored potential energy of the conductive material 108 is maintained until the annealing process for bonding the conductive feature 306 to another conductive feature (e.g., the conductive feature 156 of the second element 152, shown in Figure 4E). The second amount (z.e., the amount of impurities 120 in Figures 3A-3C) of impurities 120 is greater than the first amount (z.e., the amount of impurities 120 in Figures 2A-2C). In some embodiments, the conductive material 108 with the second amount of impurities 120 can delay grain growth of the conductive material 108 for a longer time than can the conductive material 108 with the first amount of impurities 120. In some embodiments, the second amount of impurities 120 can enable the conductive material 108 of the conductive feature 306 to prevent or minimize grain growth at room temperature.

[0048] The conductive features (e.g., the first conductive feature 206 of the first element 102 and the second conductive feature 156 of the second element 152) disclosed herein can be replaced with any suitable conductive feature or structure. A conductive feature 206 can comprise a contact pad configured to directly bond to another conductive feature 156 on an opposing element. The conductive feature 206 can comprise a contact pad connected to underlying circuitry or traces, a through-substrate via (TSV) extending at least partially through a substrate, or any other conductive material configured to directly bond and contact an opposing conductive feature 156. [0049] Figures 4A-4F show schematic cross sectional side views illustrating various steps in a process of manufacturing a first element 102 then a bonded structure 100. In Figure 4A, a nonconductive region 130 can be provided. The nonconductive region 130 can comprise a nonconductive material (e.g., dielectric material 132), such as silicon oxide, silicon nitride, silicon oxynitride, or other similar materials. In Figure 4B, an opening 122 can be formed at a nonconductive surface 136 of the nonconductive region 130. The opening 122 may comprise any suitable shape and size for receiving a conductive material 108 (shown in Figure 4C), so as to form a conductive feature 206 (shown in Figure 4D), such as a contact pad or a via, such as a through-substrate via (TSV) or a through-substrate groove (TSG). The nonconductive surface 136 can comprise a contact surface that in some embodiments can bond to the nonconductive surface 148 of a second element 152, as shown in Figures 4E and 4F.

[0050] In Figure 4C, a barrier layer 126, a seed layer (not shown), and a conductive material 108 can be provided in the opening 122 and over the surface of the dielectric material 132. The barrier layer 126 can comprise a nitride, such as titanium nitride (TiN) or tantalum nitride (TaN). And the seed layer (not shown) can be a metallic (e.g. copper) seed that can be deposited over the barrier layer 126 and used as a seed for the electroplating process that fils the opening 122 with the conductive material 108. In Figure 4C, impurities 120 (not shown) can be provided in the conductive material 108 of the conductive feature 206. In some embodiments, the impurities 120 (not shown) can be provided as a seed layer (not shown), e.g., can be sputtered into the opening 122. In some other embodiments, the impurities 120 can be provided by way of a physical vapor deposition (PVD) process or sputtering. For example, the impurities 120 can be provided by way of co-deposition of impurities 120 at a certain concentration with the conductive material 108 using a doped conductive material target or cosputtering, or co-plating the impurities 120 with the conductive materials 108 from electroless or electrolytic plating bath or baths. More than one type of plating bath may be applied to fill the opening 122 in the dielectric material 132. After the seed layer coating step, a first bath that comprises a superfilling can be used to form a conductive material 108 (e.g., a void free or generally void free conductive material) in bulk of the opening 122. For example, with the first bath, the opening 122 can be filled less than 90% of the depth of the opening 122 (not shown). A second coating process may be applied to fill and overfill the opening 122 in the dielectric material 132. The second coating can include grain size modulated particles. In some embodiments, the impurities 120 (not shown) can comprise nanoparticles. In some embodiments, the impurities 120 can be provided by way of atomic layer deposition (ALD) method. An amount of the impurities 120 can be selected so as to maintain the stored potential energy of the conductive material 108 in ambient conditions (e.g., at room temperature) before an annealing process. The conductive feature 206 is configured such that grains 116 (not shown) of the conductive material 108 grow slower than the conductive material 108 without the impurities 120 (not shown) at room temperature.

[0051] In Figure 4D, an element 102 can be formed. In Figure 4D at least a portion of the conductive material 108 can be removed. The portion of the conductive material 108 can be removed by way of chemical mechanical polishing (CMP). In some embodiments, the CMP process can also remove a very small portion of the nonconductive surface 136 of the dielectric material 132 to form the contact surface 104. When the nonconductive surface 136 of the dielectric material 132 is polished, there can be dielectric rounding at a region of the contact surface 104 adjacent to the barrier layer 126 or conductive material 108 in the opening 122 (shown in Figure 4B) of the dielectric material 132. The presence of impurities 120 (not shown) can reduce the grain 116 size (not shown) of the conductive material 108 within the conductive feature 206 in the opening 122. Smaller grains tend to be mechanically harder than larger grains, thus the presence of the impurities in the conductive material 108 can reduce the polish rate for polishing the conductive material 108. The reduced polish rate of the small grain conductive material 108 can coincidentally minimize the dielectric rounding. Although not shown in Figures 4A-4D, it should be appreciated that the illustrated dielectric material 132 (e.g., a nonconductive region 130) and conductive feature 206 (which can comprise a conductive material 108 with embedded impurities 120 (not shown)) may be formed on a larger semiconductor device region (not shown) such as a silicon region or layer. Each element 102 can comprise a plurality of conductive features 206 formed in the contact surface 104.

[0052] Figure 4E shows the element 102 (a first element 102) and another element (a second element 152) before being bonded together to form a bonded structure 100 (shown in Figure 4F). In some embodiments, the second element 152 can have a similar structure as the first element 102. In some embodiments, each of the first and second elements 102, 152 can include a conductive feature 206, 156 at least partially embedded in a nonconductive region 130, 160, as described above. The conductive features 206, 156 can comprise a conductive material 108 (shown, e.g., in Figures 2A-2C) and impurities 120 (shown, e.g., in Figures 2A- 2C), as described above. The conductive material 108 includes grains 116 (shown, e.g., in Figures 2A-2C) and grain boundaries 118 (shown, e.g., in Figures 2A-2C), and impurities 120 (shown, e.g., in Figures 2A-2C) can be embedded in grains 116 or along grain boundaries 118 within the conductive features 206, 156. In some embodiments, each of the elements 102 and 152 can include a seed layer (not shown) and/or a barrier layer 126, 126a disposed between each element’s conductive feature 206, 156 and dielectric material 132, 132a.

[0053] The bonded structure 100 (shown in Figure 4F) can be formed by bonding the first element’s 102 contact surface 104 to the second element’s 156 contact surface 154. Each element’s 102, 152 contact surface 104, 154 can comprise a nonconductive portion (e.g., a nonconductive surface 136, 146, which can be the surface of the nonconductive region 130, 160) and a conductive portion (e.g., a conductive surface 138, 148, which can be the surface of the conductive feature 206, 156). The conductive surfaces 138, 148 can be recessed below the nonconductive surfaces 136, 146 by, for example, less than 30nm. These recesses are not shown in the figures.

[0054] Figure 4F shows a bonded structure 100 in which the first and second elements 102, 152 shown in Figure 4E are directly bonded to each other along the contact surfaces 104, 154. During the direct bonding process, the elements 102, 152 (shown in Figure 4F) can be brought together to form a direct bond between adjacent nonconductive regions 130, 160 and annealed to impart expansion to the conductive features 206, 156 to form electrical contacts between opposing conductive features 206, 156. Beneficially, the potential energy of the conductive material (e.g., copper) of the conductive features 206, 156 can be maintained prior to bonding by providing non-alloying impurities 120 (shown, e.g., in Figures 2A-2C) that migrate to the grain boundaries 118 of the conductive material. Maintaining the potential energy can beneficially lower the thermal budget of the direct bonding process by reducing the temperature at which the elements 102, 152 are annealed in order to form the metallic contacts between opposing conductive features 206, 156.

[0055] The nonconductive (e.g., dielectric) material 132 of the nonconductive region 130 of the first element 102 can be bonded to the nonconductive (e.g., dielectric) material 132a of the nonconductive region 160 of the second element 152. The dielectric material 132 of the first element 102 can be directly bonded to the dielectric material 132a of the second element 152 without an intervening adhesive. Once the nonconductive surface 136 of the first element 102 is directly bonded to the nonconductive surface 146 of the second element 152, in some embodiments, the first and second conductive features 206, 156 can still have some separation between them because each of the conductive surfaces 138, 148 can be recessed below the contact surfaces 104, 154. After the nonconductive regions 130, 160 of the first and second elements 102, 152 are bonded to one another, the bonded elements 102, 152 can be annealed to form the bonded structure 100. During the anneal, the conductive features 206, 156 can expand and directly bond to each other. The first and second conductive features 206, 156 - once being directly bonded to each other - can form a single component: bonded conductive features 162.

[0056] In some embodiments, the bonded elements 102, 152 can be annealed at a relatively low temperature. For example, the bonded elements can be annealed at a bonding temperature below 250°C, or at a temperature in a range of 100°C to 250°C, 100°C to 200°C, 150°C to 200°C, or 100°C to 150°C. The impurities 120 (shown, e.g., in Figures 2A-2C) can comprise a non-alloying material that does not form an alloy with the conductive material 108 at the bonding temperature, as described herein.

[0057] In some embodiments, the impurities 120 (shown, e.g., in Figures 2A-2C) can be provided to cover, for example, 5% to 75%, 5% to 40%, 5% to 30%, 15% to 75%, 15% to 40%, or 15% to 30% of grain boundaries 118 (shown, e.g., in Figures 2A-2C) of the conductive material 108 (shown, e.g., in Figures 2A-2C). In some embodiments, the conductive feature 206 can include, for example, 20 parts per million (ppm) to 5000 ppm, 20 ppm to 1000 ppm, 50 ppm to lOOOppm, 100 ppm to 5000ppm, 200 ppm to 2000 ppm, 50 ppm to 500 ppm, 100 ppm to 500 ppm, 200 ppm to 1000 ppm, or 200 ppm to 500 ppm of the nonalloying impurities 120. In some embodiments, the concentration or amount of the impurities 120 through a conductive feature 206 is not uniform. For example, in some embodiments, the concentration or amount of impurities 120 might be higher near the bonding surface (e.g., the contact surface 104, shown in Figure 4E) than in the bulk. A concentration or an amount of the impurities 120 can be measured by way of secondary ion mass spectrometry (SIMS), and/or transmission electron microscopy (TEM), such as a high resolution TEM (HRTEM). The impurities 120 can be present both at the grain boundary 118 and within the grain 116 (shown, e.g., in Figures 2A-2C) of the conductive material 108 of the conductive feature 206 both prior to and after the annealing process.

SUMMARY

[0058] In one embodiment, an element can include a conductive feature at a contact surface of the element including a conductive material and an amount of impurities at a grain boundary of the conductive material, the impurities having a non-alloying material that does not form an alloy with the conductive material at a bonding temperature; and a nonconductive region at the contact surface in which the conductive feature is at least partially embedded.

[0059] In some embodiments, the impurities can include a metallic compound. In some embodiments, the impurities can include a metal oxide. In some embodiments, the impurities can include a non-metallic compound. In some embodiments, the impurities can include a non-metal oxide. In some embodiments, the impurities can include a chemical compound. In some embodiments, the conductive material can include copper. In some embodiments, the impurities can include a refractory material. In some embodiments, the impurities can include tantalum. In some embodiments, the impurities can include zirconium. In some embodiments, the impurities can include molybdenum. In some embodiments, the conductive feature can be configured such that grains of the conductive material grow slower than the conductive material without the impurities at room temperature. In some embodiments, the impurities can be disposed to cover 5% to 75% of grain boundaries of the conductive material. In some embodiments, the impurities can be disposed to cover 5% to 40% of grain boundaries of the conductive material. In some embodiments, the conductive feature can include 20 parts per million (ppm) to 5000 ppm of the impurities. In some embodiments, the conductive feature can include 200 parts per million (ppm) to 1000 ppm of the impurities. In some embodiments, the amount of impurities can be configured such that potential energy of the conductive material is maintained in a room temperature. In some embodiments, the conductive features can include 20 parts per million (ppm) to 5000 ppm of the impurities near the contact surface. In some embodiments, the conductive feature can include 200 parts per million (ppm) to 1000 ppm of the impurities near the contact surface. In some embodiments, the conductive feature can include a contact pad. In some embodiments, the conductive feature can include a through-substrate via (TSV). In some embodiments, the bonding temperature can be in a range of 100°C to 250°C.

[0060] In another embodiment, a bonded structure can include a first element including a first conductive feature and a first nonconductive region at a first contact surface of the first element. The bonded structure can also include a second element including a second conductive feature directly bonded to the first conductive feature to define bonded conductive features, and a second nonconductive region directly bonded to the first nonconductive region. In some embodiments, the bonded conductive features can include a conductive material and a concentration of impurities, the impurities have a non-alloying material that does not form an alloy with the conductive material.

[0061] In some embodiments, the impurities can include a metallic compound. In some embodiments, the impurities can include a metal oxide. In some embodiments, the impurities can include a non-metallic compound. In some embodiments, the impurities can include a non-metal oxide. In some embodiments, the impurities can include a chemical compound. In some embodiments, the conductive material can include copper. In some embodiments, the impurities can include a refractory material. In some embodiments, the impurities can include tantalum. In some embodiments, the impurities can include zirconium. In some embodiments, the impurities can include molybdenum. In some embodiments, the conductive feature can be configured such that grains of the conductive material grow slower than the conductive material without the impurities at room temperature. In some embodiments, the conductive feature can include 20 parts per million (ppm) to 1000 ppm of the impurities. In some embodiments, the conductive feature can include 200 parts per million (ppm) to 1000 ppm of the impurities. In some embodiments, an amount of impurities can be configured such that potential energy of the conductive material is maintained in a room temperature.

[0062] In another embodiment, an element can be formed by: forming an opening in a dielectric material; providing a conductive material in the opening; providing non-alloying impurities at grain boundaries of the conductive material; and polishing a surface of the dielectric material and the conductive material.

[0063] In some embodiments, providing the non-alloying impurities can include providing a seed layer comprising the non-alloying impurities. In some embodiments, providing the non-alloying impurities can include co-depositing the non-alloying impurities with the conductive material. In some embodiments, providing the non-alloying impurities can include co-sputtering the non-alloying impurities with the conductive material. In some embodiments, the impurities can include a metallic compound. In some embodiments, the impurities can include a metal oxide. In some embodiments, the impurities can include a non- metallic compound. In some embodiments, the impurities can include a non-metal oxide. In some embodiments, the impurities can include a chemical compound. In some embodiments, the conductive material can include copper. In some embodiments, the impurities can include a refractory material. In some embodiments, the impurities can include tantalum. In some embodiments, the impurities can include zirconium. In some embodiments, the impurities can include molybdenum.

[0064] In another embodiment, a bonded structure can be formed by: providing a first element having a first conductive feature and a first nonconductive region at a first contact surface of the first element and a second element having a second conductive feature and a second nonconductive region at a second contact surface of the second element; directly bonding the first nonconductive region to the second nonconductive region without an intervening adhesive; and annealing to join the first conductive feature to the second conductive feature to form bonded conductive features. In some embodiments, the bonded conductive features can include a conductive material and a concentration of impurities, and the impurities can have a non-alloying material that does not form an alloy with the conductive material.

[0065] In some embodiments, the impurities can include a metallic compound. In some embodiments, the impurities can include a metal oxide. In some embodiments, the impurities can include a non-metallic compound. In some embodiments, the impurities can include a non-metal oxide. In some embodiments, the impurities can include a chemical compound. In some embodiments, the conductive material can include copper. In some embodiments, the impurities can include a refractory material. In some embodiments, the impurities can include tantalum. In some embodiments, the impurities can include zirconium. In some embodiments, the impurities can include molybdenum. In some embodiments, the conductive feature can be configured such that grains of the conductive material grow slower than the conductive material without the impurities at room temperature. In some embodiments, bonded conductive features can include 20 parts per million (ppm) to 1000 ppm of the impurities. In some embodiments, bonded conductive features can include 200 parts per million (ppm) to 1000 ppm of the impurities.

[0066] In another embodiment, a bonded structure can include a first element including a first conductive feature and a first nonconductive region at a first contact surface of the first element; and a second element including a second conductive feature directly bonded to the first conductive feature to define bonded conductive features, and a second nonconductive region directly bonded to the first nonconductive region. In some embodiments, a bonded surface area of the first element can be smaller than a bonded surface area of the second element, and a coefficient of thermal expansion (CTE) difference of a material of the first element and a material of the second element can be greater than 5ppm/°C.

[0067] In some embodiments, the first conductive feature can include impurities.

[0068] Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” “include,” “including” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Likewise, the word “connected”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Moreover, as used herein, when a first element is described as being “on” or “over” a second element, the first element may be directly on or over the second element, such that the first and second elements directly contact, or the first element may be indirectly on or over the second element such that one or more elements intervene between the first and second elements. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. [0069] Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise, or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and/or states. Thus, such conditional language is not generally intended to imply that features, elements and/or states are in any way required for one or more embodiments.

[0070] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while blocks are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and/or circuit topologies, and some blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.

Claims

WHAT IS CLAIMED IS:

1. An element comprising: a conductive feature at a contact surface of the element including a conductive material and an amount of impurities at a grain boundary of the conductive material, the impurities having a non-alloying material that does not form an alloy with the conductive material at a bonding temperature; and a nonconductive region at the contact surface in which the conductive feature is at least partially embedded.

2. The element of Claim 1, wherein the impurities comprise a metallic compound.

3. The element of Claim 2, wherein the impurities comprise a metal oxide.

4. The element of Claim 1 , wherein the impurities comprise a non-metallic compound.

5. The element of Claim 4, wherein the impurities comprise a non-metal oxide.

6. The element of Claim 1, wherein the impurities comprise a chemical compound.

7. The element of Claim 1, wherein the conductive material comprises copper.

8. The element of Claim 7, wherein the impurities comprise a refractory material.

9. The element of Claim 7, wherein the impurities comprise tantalum.

10. The element of Claim 7, wherein the impurities comprise zirconium.

11. The element of Claim 7, wherein the impurities comprise molybdenum.

12. The element of Claim 1, wherein the conductive feature is configured such that grains of the conductive material grow slower than the conductive material without the impurities at room temperature.

-28-

13. The element of Claim 1, wherein the impurities are disposed to cover 5% to 75% of grain boundaries of the conductive material.

14. The element of Claim 1, wherein the impurities are disposed to cover 5% to 40% of grain boundaries of the conductive material.

15. The element of Claim 1, wherein the conductive feature comprises 20 parts per million (ppm) to 5000 ppm of the impurities.

16. The element of Claim 1, wherein the conductive feature comprises 200 parts per million (ppm) to 1000 ppm of the impurities.

17. The element of Claim 1, wherein the amount of impurities is configured such that potential energy of the conductive material is maintained in a room temperature.

18. The element of Claim 1, wherein the conductive feature comprises 20 parts per million (ppm) to 5000 ppm of the impurities near the contact surface.

19. The element of Claim 1, wherein the conductive feature comprises 200 parts per million (ppm) to 1000 ppm of the impurities near the contact surface.

20. The element of Claim 1, wherein the conductive feature comprises a contact pad.

21. The element of Claim 1, wherein the conductive feature comprises a through- substrate via (TSV).

22. The element of Claim 1, wherein the bonding temperature is in a range of 100°C to 250°C.

23. A bonded structure comprising: a first element including a first conductive feature and a first nonconductive region at a first contact surface of the first element; and a second element including a second conductive feature directly bonded to the first conductive feature to define bonded conductive features, and a second nonconductive region directly bonded to the first nonconductive region, wherein the bonded conductive features include a conductive material and a concentration of impurities, the impurities have a non-alloying material that does not form an alloy with the conductive material.

24. The bonded structure of claim 23, wherein the impurities are at a grain boundary of the conductive material.

25. The bonded structure of Claim 23, wherein the impurities comprise a metallic compound.

26. The bonded structure of Claim 24, wherein the impurities comprise a metal oxide.

27. The bonded structure of Claim 23, wherein the impurities comprise a non-metallic compound.

28. The bonded structure of Claim 27, wherein the impurities comprise a non-metal oxide.

29. The bonded structure of Claim 23, wherein the impurities comprise a chemical compound.

30. The bonded structure of Claim 23, wherein the conductive material comprises copper.

31. The bonded structure of Claim 30, wherein the impurities comprise a refractory material.

32. The bonded structure of Claim 30, wherein the impurities comprise tantalum.

33. The bonded structure of Claim 30, wherein the impurities comprise zirconium.

34. The bonded structure of Claim 30, wherein the impurities comprise molybdenum.

35. The bonded structure of Claim 23, wherein the conductive feature is configured such that grains of the conductive material grow slower than the conductive material without the impurities at room temperature.

36. The bonded structure of Claim 23, wherein bonded conductive features comprise 20 parts per million (ppm) to 1000 ppm of the impurities.

37. The bonded structure of Claim 23, wherein bonded conductive features comprise 200 parts per million (ppm) to 1000 ppm of the impurities.

38. The bonded structure of Claim 23, wherein an amount of impurities is configured such that potential energy of the conductive material is maintained in a room temperature.

39. A method of forming an element comprising: forming an opening in a dielectric material; providing a conductive material in the opening; providing non-alloying impurities at grain boundaries of the conductive material; and polishing a surface of the dielectric material and the conductive material.

40. The method of Claim 39, wherein the providing the non-alloying impurities comprises providing a seed layer comprising the non-alloying impurities.

41. The method of Claim 39, wherein the providing the non-alloying impurities comprises co-depositing the non-alloying impurities with the conductive material.

42. The method of Claim 39, wherein the providing the non-alloying impurities comprises co-sputtering the non-alloying impurities with the conductive material.

43. The method of Claim 39, wherein the impurities comprise a metallic compound.

44. The method of Claim 43, wherein the impurities comprise a metal oxide.

45. The method of Claim 39, wherein the impurities comprise a non-metallic compound.

46. The method of Claim 45, wherein the impurities comprise a non-metal oxide.

47. The method of Claim 39, wherein the impurities comprise a chemical compound.

48. The method of Claim 39, wherein the conductive material comprises copper.

49. The method of Claim 48, wherein the impurities comprise a refractory material.

50. The method of Claim 48, wherein the impurities comprise tantalum.

51. The method of Claim 48, wherein the impurities comprise zirconium.

52. The method of Claim 48, wherein the impurities comprise molybdenum.

53. A method of forming a bonded structure comprising: providing a first element having a first conductive feature and a first nonconductive region at a first contact surface of the first element and a second element having a second conductive feature and a second nonconductive region at a second contact surface of the second element; directly bonding the first nonconductive region to the second nonconductive region without an intervening adhesive; and annealing to join the first conductive feature to the second conductive feature to form bonded conductive features, wherein the bonded conductive features include a conductive material and a concentration of impurities, the impurities have a non-alloying material that does not form an alloy with the conductive material.

54. The method of Claim 53, wherein the impurities comprise a metallic compound.

-32-

55. The method of Claim 54, wherein the impurities comprise a metal oxide.

56. The method of Claim 53, wherein the impurities comprise a non-metallic compound.

57. The method of Claim 56, wherein the impurities comprise a non-metal oxide.

58. The method of Claim 53, wherein the impurities comprise a chemical compound.

59. The method of Claim 53, wherein the conductive material comprises copper.

60. The method of Claim 59, wherein the impurities comprise a refractory material.

61. The method of Claim 59, wherein the impurities comprise tantalum.

62. The method of Claim 59, wherein the impurities comprise zirconium.

63. The method of Claim 59, wherein the impurities comprise molybdenum.

64. The method of Claim 53, wherein the conductive feature is configured such that grains of the conductive material grow slower than the conductive material without the impurities at room temperature.

65. The method of Claim 53, wherein bonded conductive features comprise 20 parts per million (ppm) to 1000 ppm of the impurities.

66. The method of Claim 53, wherein bonded conductive features comprise 200 parts per million (ppm) to 1000 ppm of the impurities.

67. A bonded structure comprising: a first element including a first conductive feature and a first nonconductive region at a first contact surface of the first element; and

-33- a second element including a second conductive feature directly bonded to the first conductive feature to define bonded conductive features, and a second nonconductive region directly bonded to the first nonconductive region, wherein a bonded surface area of the first element is smaller than a bonded surface area of the second element, and wherein a coefficient of thermal expansion (CTE) difference of a material of the first element and a material of the second element is greater than 5ppm/°C.

68. The bonded structure of Claim 67, wherein the first conductive feature comprises impurities.

-34-