CN116830256A - Structure with through-substrate via and method of forming the same - Google Patents
Structure with through-substrate via and method of forming the same Download PDFInfo
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- CN116830256A CN116830256A CN202180092102.9A CN202180092102A CN116830256A CN 116830256 A CN116830256 A CN 116830256A CN 202180092102 A CN202180092102 A CN 202180092102A CN 116830256 A CN116830256 A CN 116830256A
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Abstract
A microelectronic structure having through-substrate vias (TSVs) and a method of forming the same are disclosed. The microelectronic structure may include a bulk semiconductor having a via structure. The via structure may have a first conductive portion and a second conductive portion. The via structure may also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure may have a second barrier layer between the first conductive portion and the second conductive portion. The second conductive portion may extend from the second barrier layer to an upper surface of the bulk semiconductor. The microelectronic structure including the TSVs is configured such that the microelectronic structure can be bonded to a second element or structure.
Description
Cross Reference to Related Applications
The present application claims priority from U.S. provisional patent application No. 63/216,389 entitled "STRUCTURES WITH THROUGH-SUBSTRATE VIAS AND METHODS FOR FORMING THE SAME" filed on month 29 of 2021 and U.S. provisional patent application No. 63/131,263 entitled "STRUCTURES WITH THROUGH-SUBSTRATE VIAS AND METHODS FOR FORMING THE SAME" filed on month 28 of 2020, the entire contents of which are incorporated herein by reference.
Technical Field
The field relates to structures having through-substrate vias and methods of forming the same.
Background
Semiconductor elements such as integrated device dies or chips may be mounted or stacked on other elements. For example, the semiconductor element may be mounted to a carrier such as a package substrate, interposer, reconstituted wafer or element, or other semiconductor element. As another example, a semiconductor element may be stacked on top of another semiconductor element, e.g., a first integrated device die may be stacked on a second integrated device die. In some arrangements, through-substrate vias (TSVs) may extend vertically through the thickness of the semiconductor element to transmit electrical signals through the semiconductor element, e.g., from a first surface of the semiconductor element to an opposing second surface of the semiconductor element. There remains a need for improved methods for forming TSVs.
Drawings
The detailed implementation will now be described with reference to the following figures, which are provided by way of example and not limitation.
Fig. 1A-1F illustrate conventional process steps for forming TSVs in a device.
Fig. 2 shows an etch depth map of a processed wafer.
Fig. 3A and 3B are example wafer diagrams of etched wafers.
Fig. 4A-4I illustrate a method of forming a microelectronic structure, in accordance with various embodiments.
Fig. 5A-5I illustrate a method for forming a microelectronic structure, in accordance with various embodiments.
Fig. 6A-6H illustrate a method for forming a microelectronic structure, in accordance with various embodiments.
Detailed Description
Fig. 1A-1F illustrate various conventional process steps for forming TSVs in microelectronic structures. Conventionally, the formation of TSVs may be performed using a via-middle or front-side via last processing method. Both methods are high volume manufacturing processes for different dies, including, for example, 40um thick dies. Both of these processes involve etching through the TSV into the bulk silicon after integrated circuit fabrication. The technical challenges of these processes increase as die thickness decreases. These challenges may include TSV etch uniformity, die thickness uniformity, and overall quality of the formed backside dielectric layer.
In fig. 1A, the microelectronic structure includes a portion of a semiconductor wafer 102. The illustrated via structure includes a via intermediate structure in which active circuitry 106 (e.g., a transistor or other active circuit element) may be formed on or in an active surface of bulk semiconductor portion 102, one or more insulating layers 112 and 113 may be formed over active circuitry 106, and an opening 104 for a TSV may be formed through one or more insulating layers 112 and 113 and a portion of bulk semiconductor portion 102. In some arrangements, the metallization layer 110 (e.g., a back end of line (BEOL) or a redistribution layer (RDL)) may be disposed over or within one or more insulating layers.
In fig. 1B, a via structure 108 may be provided. The via structure 108 may extend into the opening and over the insulating layers 112 and 113. In fig. 1C, conductive pads 114 may be disposed over one or more of the insulating layers and electrically connected to metallization layer 110. The conductive cap layer resulting from electroplating the via structure 108 in fig. 1B may be removed (e.g., polished off) in fig. 1C. As shown in fig. 1D, conductive pads 117 may be disposed over one or more insulating layers 112 and 113 and electrically connected to via structures 108. The conductive pad 117 may also be configured to be electrically connected to another element. In some arrangements, the conductive pad 117 may be part of a BEOL or RDL.
As shown in fig. 1E, the front side of the microelectronic structure 114 may be attached to a carrier 120 by an adhesive 118. The carrier 120 may include a temporary handle wafer for supporting the microelectronic structure 114 during processing. In some embodiments, the adhesive 118 may include an organic adhesive and may be sensitive to high temperatures. Thus, the use of the adhesive 118 to attach the carrier 120 to the microelectronic structure 114 may limit the temperature that may be applied during processing. However, in other embodiments, the carrier 120 may be directly bonded to the front side of the microelectronic structure 114 without the adhesive 118. The back side of semiconductor portion 124 may be ground or lapped to expose via 108 when front side 114 is attached to carrier 120. As shown in fig. 1F, a dielectric layer 122 may be deposited on the back surface of semiconductor 124. A back side metallization layer 116, such as a back end of line (BEOL) or a redistribution layer (RDL), may be disposed over the dielectric layer 122 and may be configured to electrically connect to the via structure 108.
Conventional via formation processes have several problems that result in non-uniform via lengths. For example, the etching process for forming openings for vias is not uniform across the substrate (e.g., wafer), particularly for high aspect ratio openings for vias, which results in via openings having different depths. Such non-uniformity in the resulting vias results in yield loss during the TSV exposure process. Furthermore, dielectric deposition as part of the TSV exposure process may be limited by the temporary bonding material used to adhere the die to the carrier. The adhesive limits the backside dielectric deposition temperature and may lead to various processing complications. In addition, the non-uniformity of the temporary bonding layer thickness may increase the uniformity of the thinned silicon wafer thickness. In fact, as shown in fig. 2, for a 12 inch wafer, the etching process used to form the via openings may have a non-uniformity of about 7 microns. In some areas of the wafer, the etch depth may be higher 202, while some areas of the wafer have a low etch depth 206, and other areas of the wafer will have an etch depth 204 between the low 206 and high 202 etch depths. Once the conductive material (e.g., copper) is filled into the openings, the varying depth of the via openings results in different via structure lengths.
As shown in fig. 3A, different via lengths may result in significant yield loss. For example, such thickness loss may further reduce TSV yield when combined with wafer thickness variations caused by temporary processes. For example, a die with too short TSVs 304 to be effective and a die with too long TSVs 302 to be effective may not be used. For example, some dies within a wafer may have TSVs 302 that are too long and break during grinding or polishing. The other vias are too short 304 and buried in the semiconductor portion of the device. Furthermore, in some processes, non-uniform TSVs may be caused by incomplete or non-uniform plating processes. For example, in such a process, the via openings may be uniformly etched, but the plating process through the high aspect ratio openings may not uniformly fill the via openings. Such process variations reduce the number 306 of active dies. Thus, various processing methods may result in non-uniform TSV lengths.
Fig. 3B shows the thickness variation of an 8 "wafer that can be measured after TSV planarization. It can be seen that the thickness of the wafer can vary by 4 microns. Some regions of the wafer may have a thickness of up to 58.09 microns while other regions of the wafer may have a thickness of 56.09 microns while other regions of the wafer may have a lower thickness of about 54.67 microns. Variations in wafer thickness can also cause some TSVs to become ineffective and result in a lower level of process control.
As described above, due to, for example, die thickness non-uniformity and TSV opening etch non-uniformity, the length of the TSV may vary significantly across the wafer after grinding the back side of the semiconductor portion to expose the TSV. Thus, when the back side of the bulk semiconductor portion is grounded or otherwise thinned, the exposed vias may protrude from the thinned back side of the semiconductor portion by varying lengths, and as described above, some vias may remain unexposed and buried in the semiconductor portion. To reduce the non-uniform length of the TSVs while preventing breakage of the protruding TSVs, one or more backside dielectric layers may be provided over the backside of the semiconductor portion and over the TSVs. Although there is some variability in TSV height, it is still possible to employ solder bumps, this variability can lead to lack of levelness and make stacking difficult. Some stacking techniques (such as direct hybrid bonding) are particularly sensitive to topographical variations.
For example, in some processes, a TSV of about 6 to 7 microns protrudes from the back side of the semiconductor portion after an initial back side silicon grind and selective removal of silicon relative to the liner of the TSV by wet or dry etching methods. A barrier layer (e.g., a dielectric barrier layer such as silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon, or any other suitable dielectric barrier material layer) may be deposited over the back surface of the semiconductor portion, over the sidewalls of the exposed TSVs, and over the exposed end surfaces of the exposed TSVs. A second dielectric layer, such as silicon oxide or any other suitable dielectric, may be deposited over the dielectric barrier layer, including over the upper surface of the barrier layer, over the portion of the barrier layer extending along the sidewalls of the exposed TSV, and over the portion of the barrier layer disposed along the end surfaces of the exposed TSV. After deposition of the backside dielectric layer(s), the via and portion(s) of the dielectric layer(s) may be polished or otherwise removed to planarize the via and reduce non-uniformity.
In other processes, thin layer(s) of the first dielectric barrier layer and/or the second dielectric barrier layer may be deposited over the thinned semiconductor portion and the via. For example, in other processes, the dielectric layer(s) may be only 1 or 2 microns thick, e.g., significantly thinner than the length of the protruding portion of the via. When polishing the via and dielectric layer(s), some of the via may fracture such that the end of the via is embedded in the semiconductor portion and recessed relative to the back side of the semiconductor portion. Broken TSVs can reduce device yield.
In some of these processes, the metal selected within the TSV may cause significant variation in TSV performance. For example, copper (Cu) may be an effective deposit metal in some processes. When used in TSVs, copper is an alloy metal that can be used, and can alter the expansion and polishing characteristics of the TSVs. Copper at the bottom of the etched via may be generally limited and may not anneal at the same rate or at the same temperature as the free copper. These different properties may result in Cu TSVs that do not have stable crystallography prior to exposing the TSVs during deposition. Furthermore, TSV metallization may include unsuitable routing through Direct Bond, for example The process is carried out with reliable direct bonding of metallic or organic impurities. Furthermore, shrinkage of the TSV during storage or thermal processing has been shown to cause topographical problems, such as the formation of edges or trenches in the isolation oxide that may surround the TSV.
Some major problems that reduce the yield of conventional TSV formation processes include non-uniformity in TSV etch depth and TSV breakage during polishing. TSVs may have a typical depth variation of 2 to 4 microns over 300mm wafers, for a total depth of 55 microns. Such depth variations can present challenges in achieving uniform surface engagement. In addition, uneven TSVs can lead to cracking during processing, resulting in lower yields. Chemical Mechanical Process (CMP) planarization may be used to planarize the silicon wafer. During CMP planarization, some TSVs may be broken. Such breakage may be caused in part by excessive TSV exposure, which is typically caused by a change in the depth of the TSV.
Traditionally, backside TSV processes have not been used for direct bonding in high volume manufacturing. Conventional processes for planarizing TSVs on the back side of a wafer may also rely on patterning copper pads and adding solder bumps to the wafer. The conventional backside process also cannot prevent breakage of the TSV, and may not achieve planarity suitable for direct bonding. These processes may not be suitable for mass production because of the length of the polishing time, the number of polishing cycles (which may be between 4 and 6 cycles, requiring a machine time as long as 2 hours), the amount of material deposited (5 um), the amount of material removed (2-4 um depending on the oxide deposited), and the total annealing time used between polishes (3-5 one hour annealing cycles).
Various embodiments disclosed herein may improve device yield by ensuring that the TSV length is uniform across the thinned wafer. Some embodiments may use a copper wet etch to lower the copper TSV surface to a few microns below the silicon surface. In some embodiments, surrounding the silicon body will help to inhibit and stabilize copper within the TSV. In some embodiments, the barrier layer is deposited prior to depositing the copper seed layer. In some embodiments, the vias are filled using electroplating techniques. In some embodiments, some TSVs may be deeper than others, and an electroplating process may be used to accommodate the additional depth of broken TSVs.
In some embodiments, the annealing process stabilizes the copper plug material, providing it with similar chemical and structural properties as the device side copper used for bonding. In some embodiments, the annealing process stabilizes the copper plug material to have the same impurity and texture characteristics as the device side bond copper. In some embodiments, copper plating may be annealed as a direct bond interface. This anneal may stabilize the copper plug material such that the plug material is chemically and physically similar to the device side direct bond interface copper pads.
In some embodiments, the CMP used on the copper layer may include standard direct bond interface CMP slurries and processes. In some embodiments, CMP for TSVs may be the same as device side CMP in terms of slurry usage and machine time. In some embodiments, the CMP parameters may be the same or similar to the device side CMP parameters. In some embodiments, such CMP uniformity may be achieved with or without additional photolithographic steps. In some embodiments, the only lithography step used during the CMP process may be the blanket backside process.
Fig. 4A-4I illustrate a method for forming a microelectronic structure, according to one embodiment. As shown in fig. 4A, TSV structure 410 may be provided at least partially through the thickness of the substrate including bulk semiconductor portion 404, as described above. In some embodiments, bulk semiconductor portion 404 may comprise silicon, germanium, silicon carbide, or any other suitable semiconductor material. One or more liner layers 412 may be disposed in the opening from the front surface 406 of the substrate. In some embodiments, the one or more liner layers 412 may include a dielectric liner 415. The dielectric liner 415 of the one or more liner layers 412 may include silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon, and any other suitable dielectric material. In some embodiments, the one or more liner layers 412 may additionally or alternatively include a first liner barrier layer 413. Although fig. 4A schematically illustrates layer 412 as a single layer, it should be understood that layer 412 may include multiple layers or sublayers including, for example, dielectric liner 415 and liner barrier layer 413. The first conductive via 402 may be disposed in an opening over the liner layer(s) 412. In some embodiments, the first conductive via 402 may comprise copper, but other suitable metals may be used. The first conductive via portion 402 may be disposed from a front surface of the substrate 406. The first liner barrier 413 may include a conductive barrier layer for reducing diffusion of the conductive via material. The first liner barrier 413 may be a material different from the conductive material of the first conductive via portion 402 and the second conductive via portion 424. The first liner barrier 413 may be configured to reduce diffusion of the conductive material of the first conductive via portion 402 and/or the second conductive via portion 424 into the surrounding dielectric and/or semiconductor material. Examples of materials for the first liner barrier layer 413 include metal and metal nitride materials such as titanium nitride, tantalum nitride, and any other suitable metal and metal nitride materials. The first conductive via portion 402 may be electroplated within the opening above the seed layer. The front or front surface (e.g., first surface 406) of the wafer may include an active face of the semiconductor portion in or on which active integrated circuit systems, such as transistors, are formed. The front or first surface 406 of the wafer may be mounted to a carrier 414. In some embodiments, carrier 414 may be used as a temporary handle wafer. In some embodiments, the microelectronic structure may be attached to the carrier 414 with an adhesive. In other embodiments, the microelectronic structure may be directly bonded to the carrier 414 using a direct bonding technique described in more detail below, without intervening adhesive. As shown in fig. 4A-4C, TSV 410 may have a variable height across the substrate due to the variable etching through the significant depth of the bulk semiconductor.
In fig. 4B, the back surface (second surface) 408 of the semiconductor portion (which is also the back surface of the substrate at this stage) may be thinned by dry etching or otherwise removed to expose the TSV. As shown, TSV 410 may protrude beyond the back side of semiconductor portion 408. As described above, the length of TSV 410 may be non-uniform across the wafer such that TSV 410 protrudes over semiconductor portion 416 by varying lengths. The etching process may leave the via structure 410 intact such that one or more liner layers 412 including the dielectric liner 415 and the first liner barrier 413 remain disposed over the sidewalls 411 of the first conductive via portion and along the sidewalls 411. In fig. 4C, one or more dielectric layers 418 may be disposed (e.g., deposited) over the upper surface 408 of the bulk semiconductor portion 416 along the sidewalls 411 of the via structure 410, and over the end surfaces of the via structure 410 to define a rear surface of the substrate 408. Although fig. 4C schematically illustrates layer 418 as a single layer, it should be understood that layer 418 may include multiple layers or sublayers. In various embodiments, the dielectric layer(s) 418 may be a first dielectric barrier layer 419 disposed over the bulk semiconductor portion 416 and over the via structure 410. Dielectric layer(s) 418 may also include a second dielectric layer 421 over first dielectric barrier layer 419. In various embodiments, first dielectric barrier 419 may include a material for reducing copper migration, such as silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, diamond-like carbon (DLC), or any other suitable dielectric barrier material. The second dielectric layer 421 may comprise a low-k dielectric material and may be an inorganic dielectric such as silicon oxide. As shown in fig. 4C, TSV 410 may protrude beyond semiconductor portion 408 by a distance in the range of approximately 0 to 10 microns, 1 to 7 microns, or 5 to 6 microns. Furthermore, as explained herein, TSV 410 may fracture, as seen in TSV 420, and be recessed within semiconductor portion 416 and/or dielectric layer(s) 418 by a distance in the range of 0 to 10 microns, 1 to 7 microns, or 2-6 microns. In one embodiment, the thickness of the dielectric layer(s) 418 may be in the range of about 2 to 7 microns, in the range of about 3 to 7 microns, or in the range of 4 to 6 microns, or in the range of about 5 microns.
In fig. 4D, the via structure 410 and dielectric layer(s) 418 may be planarized, for example, using a Chemical Mechanical Polishing (CMP) process applied to the back surface of the substrate 408. As explained herein, the planarization process may fracture one or more of TSVs 410, such as intermediate TSV 420. For example, in fig. 4D, the intermediate TSV 420 is shown as having been broken such that the TSV 420 is embedded within and recessed below the surface of the dielectric layer(s) 418 and/or the semiconductor portion 416. As described above, broken TSVs (e.g., intermediate TSVs 420) may reduce the device yield of the wafer. Some or all of the other TSVs 410 may also be recessed below the dielectric layer(s) and/or semiconductor portion, depending on the selected chemistry of the CMP slurry.
In fig. 4E, the first conductive via portion 402 may be selectively etched so as to be recessed below the rear surface of the substrate 408, for example, below the dielectric layer(s) 418 and/or the semiconductor portion 408. Because the intermediate TSV 420 breaks, the etch depth of the intermediate via structure 420 is deeper than the etch depth of the other via structures 410. In various embodiments, a selective copper wet etch may be performed to etch only a portion of the first conductive via portion 402. Advantageously, in the illustrated embodiment, all TSVs 410 on the entire substrate 416 are recessed to some extent, at least below the upper surface of the added dielectric layer(s) 418. In other embodiments, recessing of TSV 410 may be accomplished during CMP as described above with respect to fig. 4D. In other embodiments, not all TSVs 410 are recessed, and only some TSVs 410 are recessed, whether or not a separate recessing process is employed. For example, in some embodiments, a conventional CMP process is employed, wherein some TSVs 410 are recessed substantially below surface 408, e.g., due to breakage.
As shown in fig. 4F, a second barrier layer 422 may be provided over the exposed end surfaces of the first conductive via portion 402 and along the liner barrier layer 412 in order to improve yield and provide a planarized high quality bonding surface. A seed layer (not shown) may be disposed over the second barrier layer 422 and a second conductive via portion 424 may be disposed over the second barrier layer 422 from a rear surface of the substrate 416 by, for example, electroplating. The microelectronic structure may be annealed, which may advantageously promote grain growth to improve direct bonding. Advantageously, both the deposition process (e.g., electroplating) and the annealing process may be selected to produce a direct hybrid bond, as opposed to the plating process originally used to fill the TSV 410 via, which is selected to improve the filling of the high aspect ratio deep via.
In various embodiments, an alloy additive may be provided to the conductive material of TSV 410. Alloying additions may be provided to control the thermal expansion of the conductor and/or to improve the corrosion resistance of the conductor. In some embodiments, the conductor is copper, silver, gold, or any other suitable conductive material. The alloy additive material(s) may include metallic elements, such as beryllium, indium, gallium, nickel, and manganese, which generally represent less than 5 atomic percent of TSV 410 and more particularly less than 2 atomic percent of TSV 410. The alloying additions may be provided as part of the seed layer or the second barrier layer 422 and diffuse therefrom. Such alloying elements may be present in different amounts to affect the hardness, corrosion resistance, and/or pinning grain formation of TSV 410 during subsequent anneals. Because larger grains are needed in the second conductive portion to aid in interdiffusion in the direct metal-to-metal bonding process, the first conductive portion 402 may contain a smaller percentage of alloying elements than the second conductive portion 424. For example, in some embodiments, the second conductive via portion 424 may have at least less than 5%, at least less than 10%, at least less than 15%, or at least less than 20% alloying element(s) as compared to the first conductive via portion.
Further, during the formation of TSV 410, one or more organic additives, such as levelers, inhibitors, accelerators, may be provided to the plating bath to improve filling. In various embodiments, different additives and/or different proportions of additives, e.g., fewer additives, may be provided in plating the second conductive via portion 424 than the type or amount of additives used in plating the first conductive via portion 402 filling the opening. For example, in some embodiments, additives may be used when plating both the first conductive via portion 402 and the second conductive via portion 424, but the amount of additive for the first conductive via portion 402 may be substantially different than the amount for the second conductive via portion 424. In some embodiments, more additives may be used when plating the first conductive via portion 402 than when plating the second conductive via portion 424. In some embodiments, additives, such as organic additives, may be provided during electroplating of the first conductive via portion 402, for example, to improve filling, but different proportions or different types of organic additives may be provided during electroplating of the second conductive via portion 424. In various embodiments, the plating bath for the first conductive via portion 402 may include a higher percentage of organic additives than the plating bath used to form the second conductive via portion 424. Accordingly, the first conductive via portion 402 may have a higher percentage of impurities, such as sulfur, oxygen, nitrogen, and/or carbon, than the second conductive via portion 424. In various embodiments, the first conductive via portion 402 may be formed in a plating bath having a higher concentration of a leveler, e.g., janus Green, that introduces more impurities, such as nitrogen, carbon, and/or oxygen, than the second conductive via portion 424. In portions 402 and 424, impurities from the additives may be measured in parts per million (ppm).
After electroplating, impurities (e.g., carbon, nitrogen, sulfur, oxygen, and other impurities) from plating additives may be incorporated in the first conductive via portion 402 and/or the second conductive via portion 424. In some embodiments, the amount of impurities present in the first conductive via portion 402 may be greater than the amount of impurities present in the second conductive via portion 424. In some embodiments, only trace amounts of impurities may be present in the second conductive via portion 424. Further, the impurities present in the second conductive via portion 424 may have a different composition and/or concentration than the first conductive via portion 402. These compositions may be selected to affect the grain size, orientation, or thermal stability of the interconnect that may be formed by the second conductive portion. The impurities may include other material elements present within the conductive via at a concentration of less than 2atm.%, for example less than 100ppm or less than 50ppm. In one embodiment, the impurities in the second conductive via portion 424 may be smaller than the impurities in the first conductive via portion 402. For example, in some embodiments, the second conductive via portion 424 may have at least 5% less, at least 10% less, or at least 20% less non-copper elements (e.g., such as metal alloying elements or impurities from plating bath additives) than the first conductive via portion 402.
In fig. 4G, the portions of the second conductive via portion 424 and the second barrier layer 422 overlying the dielectric layer 418 may be removed, for example, using a CMP process applied to the back surface of the substrate. The polishing process may expose and planarize the dielectric layer(s) 418 and may be used as a preparatory step to direct bonding, i.e., a very high degree of polishing achieves planarity sufficient for direct bonding. Advantageously, the middle broken TSV420 has been repaired, a metal recess is provided at a suitable depth, and the polished dielectric layer(s) 418 and the second conductive via portion 424 can be used in a direct bonding process. For example, the plating and annealing process may form grains, such as copper, gold, or silver grains, or metal textures, such as copper, that are oriented along 111 crystal planes that are primarily perpendicular to the bonding surface, which may enhance metal diffusion and bonding during the direct bonding process. In various embodiments, the metallic texture may be oriented to have a geometric component that is substantially perpendicular to the joining surface. In some embodiments, the second conductive via portion 424 may have a first ratio of 111 planes oriented within 30 ° of the vertical direction, for example, within 30 ° of a vertical axis extending along the longitudinal dimension of the via structure, within 20 ° of the vertical direction, or within 10 ° of the vertical direction. The second conductive via portion 424 may have a second proportion of 111 planes oriented within 30 ° of the vertical direction, for example, within 30 ° of a vertical axis extending along the longitudinal dimension of the via structure, within 20 ° of the vertical direction, or within 10 ° of the vertical direction. In some embodiments, the second ratio may be greater than the first ratio. In the illustrated embodiment, the CMP selection (see fig. 4D and corresponding description) or subsequent recessing (see fig. 4E and corresponding description) is selected to ensure a degree of recessing across the substrate, each TSV 410 may include both a first conductive via portion 402 and a second conductive via portion 424. In other embodiments, at the stage of fig. 4E, not all TSVs 410 are recessed over the entire substrate, and only some TSVs 410 include second conductive via portions 424. In any event, the CMP process selected to implement the structure of fig. 4G may be selected to facilitate subsequent direct hybrid bonding. Thus, each of TSVs 410 may be recessed below the upper surface of dielectric layer(s) 418, e.g., less than 40nm, less than 30nm, less than 20nm, less than 15nm, or less than 10nm, but greater than or equal to about 5nm, e.g., greater than or equal to about 2nm.
As shown in fig. 4H, the microelectronic element described above may be used in a multi-chip or multi-element stack. For example, the first stacked die 434 may be directly bonded to the substrate wafer 432 without an adhesive. In some embodiments, the front active surface may be bonded to the substrate wafer. As described below, the contact pads 426 of the first die may be directly bonded to the contact pads 426 of the wafer without adhesive, and the non-conductive regions may be directly bonded to corresponding non-conductive regions of the wafer without adhesive 430. Additional devices may be stacked and bonded directly to the back side of the microelectronic structure. For example, as shown, the contact pads 426 of the second element or die 436 may be directly bonded to the exposed TSV structures 410 of the first element 434 without an adhesive. The non-conductive region of the second element or die 436 may be directly bonded to the dielectric layer(s) 418 without adhesive. Additional elements may be directly bonded to the second element or die to form any number of elements in the stacked and directly bonded structure. In some other applications, wafers processed using the methods described herein may be assembled or stacked and bonded directly to one another without an intermediate adhesive layer.
Fig. 4I illustrates a via structure 410 formed using various disclosed embodiments. As shown, the microelectronic structure may include a bulk semiconductor portion 404, the bulk semiconductor portion 404 having a first/front surface 406 and a second/rear surface opposite the first surface 408. In some embodiments, the second surface 408 may include an active surface having active circuitry formed in or on the second surface. Additionally or alternatively, in some embodiments, the first surface 406 may include an active surface having active circuitry formed in or on the second surface. In other embodiments, the first surface 406 may include an inactive surface without active circuitry. The via structure 410 may be disposed in an opening that extends at least partially through, e.g., completely through, the bulk semiconductor portion 404 in a direction non-parallel to the first surface. The via structure may include a first conductive via portion 402, a second conductive via portion 424, and a second barrier layer 422. The second barrier layer 422 includes a first portion 440 disposed between the first conductive via portion 402 and the second conductive via portion 424. The second barrier layer 422 may further include a second portion 442 disposed along the sidewall 411 of the second conductive portion 402. The second conductive via portion 424 may extend from the second barrier layer 440 at least to the surface of the substrate 408. As described above, the second conductive via portion 424 may have a different composition than the first conductive via portion 402.
For example, both the first conductive via portion 402 and the second conductive via portion 424 may be formed of copper, but have different types and/or concentrations of alloying elements and impurities, e.g., from levelers, suppressors, accelerators, plating current densities, and/or different grain sizes and/or orientations used in the electroplating process. For example, the first conductive via portion 402 and/or the second conductive via portion 424 may have different proportions of non-copper elements, such as metal alloy elements, or impurities from plating bath additives. The first via portion 402 may have more non-copper elements than the second via portion 424. In some embodiments, the first via portion 402 may have alloying elements, such as Be, mn, ni, introduced via diffusion from the barrier layer 412 or via a seed layer. The second via portion 424 may have no such non-copper elements, or only trace amounts of such impurities. The second via portion 424 may have such a non-copper element, but in a smaller amount than the first via portion. Alloy material(s) introduced via barrier layer(s) 412 and/or seed layer(s) during plating may be provided in some arrangement to pin grains of first via portion 402. Further, one or more organic additives may be provided during plating of the first via portion 402 to improve filling, and the additives may not be used for the second conductive via portion 424. In other embodiments, organic or other additives may be provided for both the first via portion 402 and the second via portion 424, but the first via portion 402 may have a higher concentration of impurities left by the additives after plating. As explained herein, impurities such as sulfur, oxygen, carbon, or nitrogen may be present in TSV 410 at a higher concentration in first via portion 402 than in second via portion 424. In some embodiments, the composition of non-copper elements (including alloying elements and impurities from the additives) in the first conductive via portion 402 is higher than the composition in the second conductive via portion 424. For example, in some embodiments, the second conductive via portion 424 may have at least less than 5%, at least less than 10%, at least less than 15%, or at least less than 20% non-copper elements as compared to the first conductive via portion 402. The composition and grain structure of the first conductive portion 402 may be the result of a process selected to optimize the filling of deep high aspect ratio vias, wherein the composition and grain structure of the second conductive portion 424 may be selected to optimize subsequent direct hybrid bonding.
As shown in fig. 4I, a dielectric layer 418 may be disposed on the bulk semiconductor portion 404, wherein the second conductive via portion 424 extends through the dielectric layer 418 such that an end of the second conductive via portion 424 is flush with an upper surface of the dielectric layer 418 or slightly recessed relative to the upper surface of the dielectric layer 418, e.g., less than about 40nm, less than about 30nm, less than about 20nm, less than about 10nm, or less than about 5nm. Dielectric layer 418 may include a planarized dielectric bonding layer configured for direct bonding to another element. Dielectric layer 418 may also include a dielectric barrier layer on bulk semiconductor portion 404, with a planarized dielectric bonding layer disposed over the dielectric barrier layer. The first liner barrier 412 may extend along the sidewalls 411 of the first conductive portion 402 and the second conductive portion 424. As shown, the second barrier layer 440 may include a second portion 442, the second portion 442 extending along the first barrier layer 412 between the first barrier layer 412 and the second conductive via portion 424. Thus, the total barrier thickness between the second conductive portion 424 and the bulk substrate 404 is greater than the barrier thickness between the first conductive portion 402 and the bulk substrate 404, and may include two identifiable barrier layers that may or may not have the same composition.
Fig. 5A-5I illustrate a method for forming a microelectronic structure, according to another embodiment. The embodiments of fig. 5A-5I may be identical or substantially similar to similar components of fig. 4A-4I, unless otherwise indicated. For example, the steps of fig. 5A-5E may be the same as those described above in connection with fig. 4A-4E. However, in fig. 5F, a barrier layer may not be disposed over the first conductive via portion 410. Conversely, the second conductive via portion 424 may be plated directly onto the first conductive via portion 410, or onto the intervening seed layer alone, and onto the bulk semiconductor portion 416 without an intervening barrier layer. As described above, the structure of fig. 5F may be annealed, which may promote copper grain growth to facilitate direct bonding.
In various embodiments, the buried conductive material of the first conductive via portion 402 may be more constrained than the upper portion of the conductive material of the second conductive via portion 424. During annealing, the first conductive via portion 402 and the second conductive via portion 424 may form different metal textures and/or have different concentrations of non-copper elements, such as alloying elements and/or impurities from plating additives. For example, the first metal texture of the first conductive via portion 402 may be different than the second metal texture of the second conductive via portion 424. In various embodiments, including the embodiments disclosed in fig. 4A-4I and 5A-5I, the crystal structure of the second conductive via portion 424 may have grains oriented vertically along the 111 crystal plane that is not parallel (e.g., generally perpendicular) to the bonding interface to enhance metal diffusion, such as copper diffusion, during direct bonding. The grains may have a geometric component generally perpendicular to the bonding interface. In some embodiments, the first conductive via portion 402 and the second conductive via portion 424 may comprise different metals or different alloys. For example, in some embodiments, the first conductive via portion 402 may comprise a copper alloy and the second conductive via portion 424 may comprise substantially pure copper.
Fig. 5G and 5H are generally similar to the steps described in fig. 4G and 4H. Fig. 5I shows a microelectronic structure without the intervening barrier layer of fig. 4I. As shown in fig. 5I, the second conductive via portion 424 may be formed after the first conductive via portion 402 and separate from the first conductive via portion 402. Unlike fig. 4I, there is no intervening barrier layer 440 between the first conductive via portion 402 and the second conductive via portion 424.
Fig. 6A-6H illustrate another embodiment that enables formation of conductive vias 606 having a substantially uniform length while avoiding degradation of the vias 606 (e.g., copper vias or other suitable conductive metals) and/or contamination of the semiconductor portion 604 (e.g., silicon or other suitable semiconductor). Unless otherwise indicated, the components in fig. 6A-6H are generally similar to the components in fig. 4A-5I. For example, as described above, as shown in fig. 6A, a semiconductor element 604 (e.g., a semiconductor wafer) may have a plurality of conductive vias 606 formed in the semiconductor portion 604 (e.g., a silicon block or device portion). The front side of the bulk semiconductor 610 is shown facing upward and the opposite back side of the bulk semiconductor 612 is shown facing downward. In various embodiments, the front side 610 may include an active side of a semiconductor element such that active circuitry may be formed at or near the front side 610. The dielectric liner and/or barrier 608 may line the opening in which the via 606 is disposed. One or more front side dielectric layers 602 may be disposed over the front side of semiconductor portion 610. Although fig. 6A schematically illustrates the layer 602 as a single layer, it should be understood that the layer 602 may include multiple layers or sublayers. Front side dielectric layer(s) 602 may include any suitable type(s) of dielectric material including, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, diamond-like carbon (DLC), and any other suitable dielectric material.
As described above, the depth of the opening in which the conductive via 606 material is deposited (e.g., electroplated) may vary, which may result in the formation of vias having non-uniform lengths. Lack of uniformity can make it challenging to expose vias from the back side of the semiconductor element 612. In practice, the etch variation of the via opening 606 may be on the order of 2-3 microns or more, such that the TSV height may vary by 50% or more. In the process of fig. 4B and 5B, the semiconductor portion 604 is dry etched to expose the via 606, which may protrude above the semiconductor material 604 at different heights. However, with a device such as SF 6 Dry etching of semiconductor material 604 with an etchant such as silicon may result in severe attack of the copper via material, particularly if the dielectric liner and/or liner stop layer 608 is etched before the via 606 is fully exposed. Further, the processing of the conductive vias 606 (e.g., by CMP, grinding, and other processing methods) may cause some of the conductive material (e.g., copper material) of the vias to contaminate the semiconductor portion 604, such as silicon.
Thus, unlike the process of fig. 4B and 5B, in fig. 6B, the back side of the semiconductor portion 612 may be ground and polished, for example using CMP, to expose the via 606. The grinding and polishing process may uniformly expose the conductive vias 606, which may accommodate the non-uniform length of the vias 606 prior to grinding and polishing. For example, the back side of the semiconductor element 612 may be ground and polished until all of the vias 606 are exposed at the planarized, ground, and polished back side of the semiconductor element 614. Thus, in the illustrated embodiment, grinding and polishing processes may be used to expose vias 606 having a substantially uniform length. Because exposing the via 606 (which may include copper and other materials) to CMP may contaminate semiconductor portions, such as silicon, in other embodiments, such as those described above in connection with fig. 4A-5I, it may not be desirable to expose the via 606 with CMP. In such embodiments, as described above, an etching process (e.g., SF 6 Etching) to initially expose the via 606.
Turning to fig. 6C, conductive via 606 may be etched from back surface 614 to form an etched recess in the conductive material, which may include copper. For example, in one embodiment, the conductive material may be etched to a depth in the range of 0.25 microns to 3 microns, in the range of 0.5 microns to 3 microns, such as about 1 micron. In fig. 6D, a first backside dielectric layer 616 may be disposed (e.g., deposited) over the ground and polished backside of semiconductor portion 618 and into etched recesses formed in vias 620. As shown, the first backside dielectric layer 616 may extend within the recess over the copper via and abut a dielectric liner and/or barrier layer disposed in the opening 620. In some embodiments, the first backside dielectric layer 616 may include multiple layers. For example, in the illustrated embodiment, the first backside dielectric layer 616 may include a first dielectric layer 617 (e.g., a low temperature silicon nitride dielectric layer) and a second dielectric layer 619 (e.g., a low temperature silicon oxide dielectric layer), the first dielectric layer 617 being disposed on the backside of the semiconductor portion and the via 606, the second dielectric layer 619 being located over the first dielectric layer 617. For example, in various embodiments, first dielectric layer 617 and/or second dielectric layer 619 may be formed using a low temperature Chemical Vapor Deposition (CVD) process. However, in other embodiments, the first backside dielectric layer 616 may include only a single dielectric layer, or more than two dielectric layers.
Turning to fig. 6E, the back side of the semiconductor element 614 may be polished (e.g., with CMP) to remove a first portion of the first back side dielectric layer 616 that covers the semiconductor portion 604, thereby exposing the semiconductor portion 604. A second portion of the first backside dielectric layer 620 may remain in the recess over the conductive via 606, as shown in fig. 6E. The remaining second portion of the first backside dielectric layer 620 may be used to protect the conductive via material during a subsequent dry etch of the semiconductor portion 604, as shown in fig. 6F. The dry etch of fig. 6F may correspondingly uniformly expose the vias 606 and the second portion of the first backside dielectric layer 620 may be used to preserve during the dry etchCopper for protecting vias, e.g. using SF 6 . In addition, the step of FIG. 6F may use an etchant, such as SF 6 The etchant is highly selective to silicon over the first back side dielectric layer 620, and the first back side dielectric layer 620 may include silicon oxide at the exposed surface. Thus, as shown, after the dry etch of fig. 6F, the via 606, the first portion of the first backside dielectric layer 620, and the dielectric liner/barrier layer 608 may protrude with respect to the etched surface of the backside of the semiconductor portion 604. In various embodiments, the vias may protrude by an amount in the range of 3 microns to 4 microns.
Turning to fig. 6G, a second backside dielectric layer(s) 624 may be disposed (e.g., deposited) over the etched surface 622 of the semiconductor portion 604, along the sidewalls of the exposed liner layer of the via 606, over the ends of the liner layer 608, and over the second portion of the first backside dielectric layer 620. In some embodiments, the second backside dielectric layer 624 may comprise multiple layers. For example, in the illustrated embodiment, the second backside dielectric layer may include a first dielectric layer 625 (e.g., a low temperature silicon nitride dielectric layer) and a second dielectric layer 627 (e.g., a low temperature silicon oxide dielectric layer), the first dielectric layer 625 being disposed on the etched surface of the semiconductor portion 622 and on the second portion of the first backside dielectric layer 620, the second dielectric layer 627 being located over the first dielectric layer 625. However, in other embodiments, the second backside dielectric layer 624 may comprise only a single dielectric layer, or more than two dielectric layers. The thickness of the second backside dielectric layer 624 may be any suitable thickness, for example in the range of 4 microns to 5 microns in various embodiments. Advantageously, the thickness of one or both of the first back side dielectric layer 625 and the second back side dielectric layer 627 may be selected so as to provide adequate support or stress compensation, particularly for thinned die.
As shown in fig. 6H, the back side of the semiconductor element may be polished (e.g., with CMP) to expose the vias 606. In particular, polishing may remove a portion of the second back dielectric layer 624 disposed over the first back dielectric layer 616, a remaining second portion of the first back dielectric layer 620, and may thin a portion of the second back dielectric layer covering the semiconductor portion. Thus, in the structure of fig. 6H, a second backside dielectric layer 624 may be disposed over the etched surface 622 of the semiconductor portion 604 and may surround the via liner layer(s) 608, such as a liner dielectric layer and/or a liner barrier layer. In various embodiments, polishing may also be used to recess conductive material into the via 606 with respect to the second backside dielectric 624 layer to prepare the backside of the semiconductor element for direct bonding. In various embodiments, the polishing may recess the conductive material by an amount in the range of 1nm to 20nm or in the range of 1nm to 10 nm. As described above, a semiconductor element may be directly bonded and/or stacked to another element. The front side dielectric layer(s) 602 may also be removed to expose the vias 606 at the front side, and one or more additional elements may be stacked on and directly bonded to the front side of the semiconductor element.
Examples of direct bonding method and direct bonding structure
Various embodiments disclosed herein relate to a direct-bonded structure in which two elements can be directly bonded to each other without intervening adhesive. Two or more semiconductor elements (such as integrated device die, wafer, and other semiconductor elements) may be stacked on top of each other or bonded to each other to form a bonded structure. The conductive contact pads of one element may be electrically connected to corresponding conductive contact pads of another element. Any suitable number of elements may be stacked in the engagement structure.
In some embodiments, the elements are directly bonded to one another without adhesive. In various embodiments, the non-conductive or dielectric material of the first element may be directly bonded to the corresponding non-conductive or dielectric field region of the second element without adhesive. The non-conductive material may be referred to as a non-conductive bonding region or bonding layer of the first element. In some embodiments, the non-conductive material of the first element may be directly bonded to the corresponding non-conductive material of the second element using a dielectric-to-dielectric bonding technique. For example, a dielectric-to-dielectric bond may be formed without adhesive using direct bonding techniques disclosed in at least U.S. patent nos. 9,564,414, 9,391,143, and 10,434,749, the entire contents of each of which are incorporated herein by reference in their entirety and for all purposes.
In various embodiments, a hybrid direct bond may be formed without intervening adhesive. For example, the dielectric engagement surface may be polished to a high degree of smoothness. The bonding surface may be cleaned and exposed to a plasma and/or etchant to activate the surface. In some embodiments, the surface may be terminated with a substance after activation or during activation (e.g., during a plasma and/or etching process). Without being limited by theory, in some embodiments, an activation process may be performed to break a chemical bond at the bonding surface, and a termination process may provide additional chemicals at the bonding surface that increase the bonding energy during direct bonding. In some embodiments, the activation and termination are provided in the same step, e.g., a plasma or wet etchant for activating and terminating the surface. In other embodiments, the bonding surfaces may terminate in separate processes to provide additional substances for direct bonding. In various embodiments, the termination material may include nitrogen. Further, in some embodiments, the engagement surface may be exposed to fluorine. For example, one or more fluorine peaks may be present near the layer and/or the bonding interface. Thus, in some embodiments, in a direct-bonded structure, the bonding interface between the two dielectric materials may include a very smooth interface with higher nitrogen content and/or fluorine peaks at the bonding interface. Additional examples of activation and/or termination processes can be found in U.S. patent nos. 9,564,414, 9,391,143, and 10,434,749, each of which is incorporated by reference in its entirety and for all purposes.
In various embodiments, the conductive contact pads of the first element may also be directly bonded to corresponding conductive contact pads of the second element. For example, hybrid bonding techniques may be used to provide direct conductor-to-conductor bonding along a bonding interface that includes covalently directly bonded dielectric to dielectric surfaces prepared as described above. In various embodiments, conductor-to-conductor (e.g., contact pad-to-contact pad) direct bonding and dielectric-to-dielectric hybrid bonding may be formed using direct bonding techniques disclosed in at least U.S. patent nos. 9,716,033 and 9,852,988, each of which is incorporated by reference in its entirety and for all purposes.
For example, dielectric bonding surfaces may be prepared and bonded directly to each other without an intervening adhesive as described above. The conductive contact pads, which may be surrounded by the non-conductive dielectric field regions, may also be directly bonded to each other without intervening adhesive. In some embodiments, the respective contact pads may be recessed below an outer (e.g., upper) surface of the dielectric region or the non-conductive bonding region, e.g., recessed less than 30nm, less than 20nm, less than 15nm, or less than 10nm, e.g., in the range of 2nm to 20nm, or in the range of 4nm to 10 nm. In some embodiments, the non-conductive bonding regions may be directly bonded to each other without an adhesive at room temperature, and subsequently, the bonded structure may be annealed. Upon annealing, the contact pads may expand and contact each other to form a metal-to-metal direct bond. Advantageously, hybrid bonding techniques (such as direct bond interconnection or (commercially available from Xperi, san jose, california)) can achieve high density pads that are connected across the direct bond interface, e.g., small or fine pitch of a conventional array. In some embodiments, the pitch of the bond pads or conductive traces embedded in the bonding surface of one of the bonding elements may be less than 40 microns or less than 10 microns or even less than 2 microns. For some applications, the ratio of the pitch of the bond pads to one of the bond pad dimensions is less than 5, or less than 3, and sometimes less than 2 is desirable. In other applications, the width of the conductive trace embedded in the bonding surface of one of the bonding elements may be between 0.3 microns and 3 microns. In various embodiments, the contact pads and/or traces may comprise copper, but other metals maySo as to be suitable.
Thus, in a direct bonding process, a first element may be directly bonded to a second element without intervening adhesive. In some arrangements, the first element may include a singulated element, such as a singulated integrated device die. In other arrangements, the first element may include a carrier or substrate (e.g., a wafer) that includes a plurality (e.g., tens, hundreds, or more) of device regions that, when singulated, form a plurality of integrated device dies. Similarly, the second element may comprise a singulated element, such as a singulated integrated device die. In other arrangements, the second element may comprise a carrier or substrate (e.g., a wafer).
As described herein, the first and second elements may be directly bonded to each other without an adhesive, unlike the deposition process. In one application, the width of the first element in the joined structure may be similar to the width of the second element. In some other embodiments, the width of the first element in the engagement structure may be different than the width of the second element. The width or area of the larger elements in the joined structure may be at least 10% greater than the width or area of the smaller elements. The first element and the second element may accordingly comprise non-deposited elements. Furthermore, unlike the deposited layer, the directly bonded structure may include a defective region along the bonding interface in which nanovoids are present. Nanovoids may be formed as a result of activation of the bonding surface, such as exposure to plasma. As described above, the bonding interface may include a concentration of material from the activation and/or final chemical treatment process. For example, in embodiments where activation is performed with a nitrogen plasma, a nitrogen peak may be formed at the bonding interface. In embodiments where activation is performed with an oxygen plasma, an oxygen peak may be formed at the bonding interface. In some embodiments, the bonding interface may include silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. As explained herein, the direct bond may include a covalent bond that is stronger than the van der waals bond. The bonding layer may also include a polished surface that is planarized to a high degree of smoothness.
In some embodiments, a metal-to-metal bond is formed between the contact pads. In some embodiments, the contact pads comprise copper or copper alloy. In various embodiments, the metal-to-metal bond between the contact pads may be bonded such that copper grains grow with each other across the bond interface. In some embodiments, the copper may have grains oriented along the 111 crystal plane to improve copper diffusion across the bonding interface. The bonding interface may extend substantially entirely to at least a portion of the bonding contact pad such that there is substantially no gap between non-conductive bonding regions at or near the bonding contact pad. In some embodiments, a barrier layer may be provided under the contact pad, for example, the barrier layer may include copper. However, in other embodiments, there may be no barrier layer below the contact pads, for example as described in US 2019/0096741, which is incorporated herein by reference in its entirety and for all purposes.
In one embodiment, a microelectronic structure is disclosed. The microelectronic structure may include a bulk semiconductor portion having a first surface and a second surface opposite the first surface; and a via structure disposed in the opening, the opening extending at least partially through the bulk semiconductor portion in a direction non-parallel to the first surface, the via structure including a first conductive via portion, a second conductive via portion, a first barrier layer extending along a sidewall of the first conductive via portion, and a second barrier layer including a first portion disposed between the first conductive via portion and the second conductive via portion, the second conductive via portion extending from the second barrier layer to at least the first surface.
In some embodiments, the microelectronic structure includes a dielectric layer on the bulk semiconductor portion, the second conductive via portion extending through the dielectric layer such that an end of the second conductive via portion is flush with or recessed from an upper surface of the dielectric layer. In some embodiments, the dielectric layer includes a planarized dielectric bonding layer configured for direct bonding to another element. In some embodiments, the dielectric layer further includes a dielectric barrier layer on the bulk semiconductor portion, and the planarizing dielectric engagement layer is disposed on the dielectric barrier layer. In some embodiments, the second barrier layer includes a second portion extending along the first barrier layer between the first barrier layer and the second conductive via portion. In some embodiments, the first metal texture of the first conductive via portion is different than the second metal texture of the second conductive via portion. In some embodiments, the second metal texture has grains oriented along 111 crystal planes that are not parallel to the bonding interface. In some embodiments, the first conductive via portion and the second conductive via portion comprise copper with an impurity material therein. In some embodiments, the first conductive via portion has a higher impurity concentration than the second conductive via portion. In some embodiments, the first conductive via portion further includes one or more alloying elements including one or more of beryllium (Be), indium (In), gallium (Ga), manganese (Mn), and nickel (Ni). In some embodiments, the impurity material includes one or more of sulfur, oxygen, carbon, or nitrogen. In some embodiments, the first conductive via portion and the second conductive via portion comprise different metals or different alloys. In some embodiments, the second surface comprises an active surface comprising active integrated circuit systems formed in or on the second surface. In some embodiments, the microelectronic device is directly bonded to another element without intervening adhesive. In some embodiments, an end surface of the second conductive via portion is directly bonded to a contact pad of another element without intervening adhesive. In some embodiments, the non-conductive bonding regions of the microelectronic element and the other element are directly bonded without intervening adhesive. In some embodiments, the microelectronic structure may include a second via structure having a first conductive via portion, a second conductive via portion, a first barrier layer extending along a sidewall of the first conductive via portion, and a second barrier layer including a first portion disposed between the first conductive via portion and the second conductive via portion, wherein the second conductive via portion of the via structure extends along a length different from a length of the second conductive via portion of the second via structure.
In another embodiment, a microelectronic structure is disclosed. The microelectronic structure may include a bulk semiconductor portion having a first surface and a second surface opposite the first surface; and a via structure disposed in the opening, the opening extending at least partially through the bulk semiconductor portion through the first surface in a direction non-parallel to the first surface, the via structure including a first conductive via portion and a second conductive via portion disposed directly onto and in contact with the first conductive via portion without intervening barrier layers, the second conductive via portion disposed between the first surface and the first conductive via portion, the first conductive via portion having a different material composition than the second conductive via portion.
In some embodiments, the microelectronic structure includes a barrier layer extending along sidewalls of the first and second conductive portions. In some embodiments, the microelectronic structure includes a dielectric layer on the bulk semiconductor portion, the second conductive via portion extending through the dielectric layer such that an end of the second conductive via portion is flush with or recessed below an upper surface of the dielectric layer. In some embodiments, the dielectric layer includes a planarized dielectric bonding layer configured for direct bonding to another element. In some embodiments, the dielectric layer further includes a dielectric barrier layer on the bulk semiconductor portion, and the planarizing dielectric engagement layer is disposed on the dielectric barrier layer. In some embodiments, the first metal texture of the first conductive via portion is different than the second metal texture of the second conductive via portion. In some embodiments, the second metal texture has grains oriented along the 111 crystal plane. In some embodiments, the first conductive via portion and the second conductive via portion comprise copper with an impurity material therein. In some embodiments, the first conductive via portion includes one or more alloying elements including one or more of beryllium (Be), indium (In), gallium (Ga), manganese (Mn), and nickel (Ni). In some embodiments, the impurity material includes one or more of sulfur, oxygen, carbon, or nitrogen. In some embodiments, the first conductive via portion and the second conductive via portion comprise different metals or different alloys. In some embodiments, the microelectronic device is directly bonded to another element without intervening adhesive. In some embodiments, an end surface of the second conductive via portion is directly bonded to a contact pad of another element without intervening adhesive. In some embodiments, the non-conductive bonding regions of the microelectronic element and the other element are directly bonded without intervening adhesive.
In another embodiment, a microelectronic structure is disclosed. The microelectronic structure may include a bulk semiconductor portion having a first surface and a second surface opposite the first surface; and a via structure disposed in the opening, the opening extending at least partially through the bulk semiconductor portion through the first surface in a direction non-parallel to the first surface, the via structure including a first conductive via portion and a second conductive via portion disposed directly onto and in contact with the first conductive via portion without intervening barrier layers, the second conductive via portion disposed between the first surface and the first conductive via portion, the first conductive via portion formed before and separate from the second conductive via portion.
In some embodiments, the microelectronic structure includes a barrier layer extending along sidewalls of the first and second conductive portions. In some embodiments, the first metal texture of the first conductive via portion is different than the second metal texture of the second conductive via portion. In some embodiments, the second metal texture has grains oriented along the 111 crystal plane. In some embodiments, the first metal texture has a first proportion of 111 planes oriented within 30 ° of the vertical direction, wherein the second metal texture has a second proportion of 111 planes oriented within 30 ° of the vertical direction, the second proportion being greater than the first portion. In some embodiments, the first conductive via portion and the second conductive via portion comprise copper with an impurity material therein. In some embodiments, the first conductive portion has a higher percentage of alloying elements than the second conductive via portion. In some embodiments, the microelectronic device is directly bonded to another element without intervening adhesive. In some embodiments, an end surface of the second conductive via portion is directly bonded to a contact pad of another element without intervening adhesive. In some embodiments, the non-conductive bonding regions of the microelectronic element and the other element are directly bonded without intervening adhesive.
In another embodiment, a method of forming a microelectronic structure is disclosed. The method may include forming an opening at least partially through a substrate having a front surface and a rear surface opposite the front surface, the opening extending through the front surface in a direction non-parallel to the second surface; providing a first conductive via portion in the opening from the front surface; exposing the first conductive via portion by removing material from the rear surface; and providing a fill structure in the opening from the back surface over the first conductive via portion after the exposing.
In some embodiments, providing the fill structure includes providing a second conductive via portion in the opening from the back surface over the first conductive via portion. In some embodiments, the method comprises: after the exposing, the first conductive via portion is recessed from the rear surface. In some embodiments, the method comprises: a second barrier layer is provided over the first conductive via portion after the first conductive via portion is provided but before the second conductive via portion is provided. In some embodiments, the method includes providing a first barrier layer along sidewalls of the first conductive via portion. In some embodiments, the method includes providing a first barrier layer prior to providing the first conductive via portion. In some embodiments, providing the second barrier layer includes providing the second barrier layer along the first barrier layer between the first barrier layer and the second conductive via portion. In some embodiments, the method includes providing a dielectric layer on the bulk semiconductor portion, the dielectric layer at least partially defining a rear surface of the substrate, the second conductive via portion extending through the dielectric layer such that an end of the second conductive via portion is flush with or recessed from the rear surface of the substrate. In some embodiments, the method includes preparing a dielectric layer for direct bonding to another element. In some embodiments, the method includes providing a dielectric barrier layer on the bulk semiconductor portion, the dielectric bonding layer being disposed on the dielectric barrier layer. In some embodiments, the method includes directly bonding the dielectric layer to another element without intervening adhesive. In some embodiments, the method includes directly bonding the end surface of the second conductive via portion to a contact pad of another element without intervening adhesive. In some embodiments, providing the fill structure includes providing a dielectric layer in the recess over the first conductive via portion. In some embodiments, the method may include removing a portion of the substrate from the back surface such that the first conductive via portion protrudes from the back surface of the substrate, and removing the dielectric layer to expose the conductive via. In some embodiments, removing the portion of the substrate includes etching a rear surface of the substrate. In some embodiments, the method may include providing a second backside dielectric layer over at least the etched back surface of the substrate and a portion of the dielectric layer disposed in the recess. In some embodiments, the method may include removing at least a portion of the second backside dielectric layer, at least partially covering a portion of the dielectric layer disposed in the recess. In some embodiments, the method may include planarizing the second backside dielectric layer and recessing the first conductive via portion relative to the second backside dielectric layer.
In another embodiment, a method of forming a microelectronic structure is disclosed. The method may include forming an opening partially through a substrate having a front surface and a back surface opposite the first surface, the opening extending through the front surface in a direction non-parallel to the front surface; filling the opening with a first conductive via portion; exposing the first conductive via portion by removing material from the rear surface; and refilling a portion of the opening with a filling structure after exposing the first conductive portion.
In some embodiments, refilling portions of the opening with the fill structure includes providing a second conductive via portion in the opening from the back surface over the first conductive via portion. In some embodiments, the method includes recessing the first conductive portion after the exposing to define a portion of the opening. In some embodiments, the method includes depositing a second barrier layer over the first conductive via portion after recessing and before refilling. In some embodiments, the method includes depositing a first barrier layer to line the opening prior to filling. In some embodiments, depositing the second barrier layer includes depositing the second barrier layer over the first barrier layer in the portion of the opening. In some embodiments, refilling portions of the opening with the filling structure includes providing a dielectric layer in the recess over the first conductive via portion. In some embodiments, the method may include removing a portion of the substrate from the back surface such that the first conductive via portion protrudes from the back surface of the substrate, and removing the dielectric layer to expose the conductive via. In some embodiments, removing the portion of the substrate includes etching a rear surface of the substrate. In some embodiments, the method may include providing a second backside dielectric layer over at least the etched back surface of the substrate and a portion of the dielectric layer disposed in the recess. In some embodiments, at least a portion of the second backside dielectric layer is removed, at least partially covering a portion of the dielectric layer disposed in the recess. In some embodiments, the method may include planarizing the second backside dielectric layer and recessing the first conductive via portion relative to the second backside dielectric layer.
In another embodiment, a joint structure is disclosed. The engagement structure may include a first element having a first engagement surface and a second element having a second engagement surface, the first element having a third surface opposite the first engagement surface; and a via structure disposed in the opening, the opening extending at least partially through the first element from the first bonding surface in a direction non-parallel to the first bonding surface, the via structure including a first conductive via portion and a second conductive via portion in contact with each other, the second conductive via portion being at least partially embedded within a bonding material at the bonding surface of the first element, the bonding material and the second conductive via portion being directly bonded to the bonding surface of the second element without intervening adhesive. In some embodiments, the non-conductive bonding regions of the first and second elements are directly bonded without intervening adhesive.
In another embodiment, a method of forming a microelectronic structure is disclosed. The method comprises the following steps: providing a substrate having an opening and a conductive via disposed in the opening, the conductive via extending partially through the substrate from a first face toward a second face of the substrate; removing a portion of the substrate from the second side to expose the conductive via; removing a portion of the conductive via from the second side of the substrate to form a recess; providing a dielectric layer in the recess over the conductive via; further removing a portion of the substrate from the second side such that the conductive via protrudes from the second side of the substrate; and removing the dielectric layer to expose the conductive via.
In some embodiments, removing the portion of the substrate includes at least one of grinding and polishing the second face. In some embodiments, at least one of grinding and polishing includes planarizing the substrate and the conductive via. In some embodiments, removing portions of the conductive vias includes etching the conductive vias. In some embodiments, providing the dielectric layer includes providing a first backside dielectric layer over the backside of the substrate and in the recess. In some embodiments, providing the first backside dielectric layer includes providing a plurality of dielectric layers. In some embodiments, providing the plurality of dielectric layers includes providing a first silicon nitride layer over the back side of the substrate and over the conductive via, and providing a second silicon oxide layer over the first silicon nitride. In some embodiments, the method may include: a portion of the first backside dielectric layer disposed over the backside of the substrate is removed prior to further removing portions of the substrate. In some embodiments, further removing portions of the substrate includes etching a back side of the substrate. In some embodiments, the method may include providing a second backside dielectric layer over at least the etched backside of the substrate and a portion of the first backside dielectric layer disposed in the recess. In some embodiments, the method may include removing at least a portion of the second backside dielectric layer that covers a portion of the first backside dielectric layer disposed in the recess. In some embodiments, the method may include planarizing the second back dielectric layer and recessing the conductive via relative to the second back dielectric layer.
Throughout the specification and claims, unless the context clearly requires otherwise, the words "comprise", "comprising", "include", and the like are to be construed in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to". The term "coupled," as generally used herein, refers to two or more elements, either directly connected or connected by one or more intervening elements. Also, the term "coupled" as generally used herein refers to two or more elements that may be directly connected or connected through one or more intervening elements. Furthermore, the words "herein," "above," "below," and words of similar import, as used in this application, shall refer to this application as a whole and not to any particular portions of this application. Furthermore, as used herein, when a first element is described as being "on" or "over" a second element, the first element can be directly on or over the second element such that the first element and the second element are in direct contact, or the first element can be indirectly on or over the second element such that one or more elements are interposed between the first element and the first element. Words in the above detailed description using singular or plural numbers may also include plural or singular numbers, respectively, where the context permits. The term "or" refers to a list of two or more items, which term encompasses all of the following interpretations of the term: any item in the list, all items in the list, and any combination of items in the list.
Furthermore, conditional language as used herein, such as "may," possible, "" may, "" e.g., (e.g.), "e.g., (for example)," and the like, are generally intended to convey that certain embodiments include and other embodiments do not include certain features, elements and/or states unless specifically stated otherwise or otherwise understood in the context of use. Thus, such conditional language is not generally indicative of features, elements and/or states which are in any way required by one or more embodiments.
While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while blocks are presented in a given arrangement, alternative embodiments may utilize different components and/or circuit topologies to perform similar functions, and some blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these blocks may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.
Claims (85)
1. A microelectronic structure, comprising:
a bulk semiconductor portion having a first surface and a second surface opposite the first surface; and
a via structure disposed in an opening extending at least partially through the bulk semiconductor portion in a direction non-parallel to the first surface, the via structure including a first conductive via portion, a second conductive via portion, a first barrier layer extending along a sidewall of the first conductive via portion, and a second barrier layer including a first portion disposed between the first conductive via portion and the second conductive via portion, the second conductive via portion extending from the second barrier layer to at least the first surface.
2. The microelectronic device of claim 1, further comprising a dielectric layer on the bulk semiconductor portion, the second conductive via portion extending through the dielectric layer such that an end of the second conductive via portion is flush with or recessed from an upper surface of the dielectric layer.
3. The microelectronic device of claim 2, wherein the dielectric layer includes a planarized dielectric bonding layer configured for direct bonding to another element.
4. The microelectronic device of claim 3, wherein the dielectric layer further comprises a dielectric barrier layer on the bulk semiconductor portion, the planarizing dielectric bonding layer being disposed on the dielectric barrier layer.
5. The microelectronic device of any of claims 1-4, wherein the second barrier layer includes a second portion extending along the first barrier layer between the first barrier layer and the second conductive via portion.
6. The microelectronic device of any of claims 1 to 5, wherein a first metal texture of the first conductive via portion is different from a second metal texture of the second conductive via portion.
7. The microelectronic device of claim 6, wherein the second metal texture has grains oriented along 111 crystal planes that are not parallel to the bonding interface.
8. The microelectronic device of any of claims 1 to 7, wherein the first and second conductive via portions comprise copper, the copper of the first conductive via portion having an impurity material therein.
9. The microelectronic device of claim 8, wherein the first conductive via portion has a higher impurity concentration than the second conductive via portion.
10. The microelectronic device of claim 8, wherein the first conductive via portion further comprises one or more alloying elements including one or more of beryllium (Be), indium (In), gallium (Ga), manganese (Mn), and nickel (Ni).
11. The microelectronic device of claim 8, wherein the impurity material comprises one or more of sulfur, oxygen, carbon, or nitrogen.
12. The microelectronic device of any of claims 1 to 11, wherein the first and second conductive via portions comprise different metals or different alloys.
13. The microelectronic device of any of claims 1 to 12, wherein the second surface comprises an active surface comprising active integrated circuit systems formed in or on the second surface.
14. A bonding structure comprising a microelectronic device according to any of claims 1 to 13, wherein the microelectronic device is directly bonded to another element without intervening adhesive.
15. The bonding structure of claim 14, wherein an end surface of the second conductive via portion is directly bonded to a contact pad of the other element without intervening adhesive.
16. The bonding structure of claim 14 or 15, wherein the non-conductive bonding regions of the microelectronic element and the further element are directly bonded without intervening adhesive.
17. The microelectronic device of any of claims 1 to 16, further comprising a second via structure having a first conductive via portion, a second conductive via portion, a first barrier layer extending along sidewalls of the first conductive via portion, and a second barrier layer including a first portion disposed between the first conductive via portion and the second conductive via portion, wherein the second conductive via portion of the via structure extends along a length different from a length of the second conductive via portion of the second via structure.
18. A microelectronic structure, comprising:
a bulk semiconductor portion having a first surface and a second surface opposite the first surface; and
a via structure disposed in an opening extending through the first surface at least partially through the bulk semiconductor portion in a direction non-parallel to the first surface, the via structure including a first conductive via portion and a second conductive via portion disposed directly onto and in contact with the first conductive via portion without an intervening barrier layer, the second conductive via portion disposed between the first surface and the first conductive via portion, the first conductive via portion having a different material composition than the second conductive via portion.
19. The microelectronic device of claim 18, further comprising a barrier layer extending along sidewalls of the first and second conductive portions.
20. The microelectronic device of any of claims 18 to 19, further comprising a dielectric layer on the bulk semiconductor portion, the second conductive via portion extending through the dielectric layer such that an end of the second conductive via portion is flush with or recessed below an upper surface of the dielectric layer.
21. The microelectronic device of claim 20, wherein the dielectric layer includes a planarizing dielectric bonding layer configured for direct bonding to another element.
22. The microelectronic device of claim 21, wherein the dielectric layer further includes a dielectric barrier layer on the bulk semiconductor portion, the planarizing dielectric bonding layer being disposed on the dielectric barrier layer.
23. The microelectronic device of any of claims 18 to 22, wherein a first metal texture of the first conductive via portion is different from a second metal texture of the second conductive via portion.
24. The microelectronic device of claim 23, wherein the second metal texture has grains oriented along 111 crystal planes.
25. The microelectronic device of any of claims 18 to 24, wherein the first and second conductive via portions include copper, the copper of the first conductive via having an impurity material therein.
26. The microelectronic device of claim 25, wherein the first conductive via portion includes one or more alloying elements including one or more of beryllium (Be), indium (In), gallium (Ga), manganese (Mn), and nickel (Ni).
27. The microelectronic device of claim 25, wherein the impurity material comprises one or more of sulfur, oxygen, carbon, or nitrogen.
28. The microelectronic device of any of claims 18 to 27, wherein the first and second conductive via portions comprise different metals or different alloys.
29. A bonding structure comprising a microelectronic device according to any of claims 18 to 28, wherein the microelectronic device is directly bonded to another element without intervening adhesive.
30. The bonding structure of claim 29, wherein an end surface of the second conductive via portion is directly bonded to a contact pad of the other element without intervening adhesive.
31. The bonding structure of claim 29 or 30, wherein the non-conductive bonding regions of the microelectronic element and the further element are directly bonded without intervening adhesive.
32. A microelectronic structure, comprising:
a bulk semiconductor portion having a first surface and a second surface opposite the first surface; and
a via structure disposed in an opening extending through the first surface at least partially through the bulk semiconductor portion in a direction non-parallel to the first surface, the via structure including a first conductive via portion and a second conductive via portion disposed directly onto and in contact with the first conductive via portion without an intervening barrier layer, the second conductive via portion disposed between the first surface and the first conductive via portion, the first conductive via portion formed before and separate from the second conductive via portion.
33. The microelectronic device of claim 32, further comprising a barrier layer extending along sidewalls of the first and second conductive portions.
34. The microelectronic device of claim 32 or 33, wherein a first metal texture of the first conductive via portion is different from a second metal texture of the second conductive via portion.
35. The microelectronic device of claim 34, wherein the second metal texture has grains oriented along 111 crystal planes.
36. The microelectronic device of claim 35, wherein the first metal texture has a first proportion of 111 planes oriented within 30 ° of vertical, wherein the second metal texture has a second proportion of 111 planes oriented within 30 ° of vertical, the second proportion being greater than the first portion.
37. The microelectronic device of any of claims 32 to 36, wherein the first and second conductive via portions include copper, the copper of the first conductive via having an impurity material therein.
38. The microelectronic device of any of claims 32 to 37, wherein the first conductive portion has a higher percentage of alloying elements than the second conductive via portion.
39. A bonding structure comprising a microelectronic device according to any of claims 32 to 38, wherein the microelectronic device is directly bonded to another element without intervening adhesive.
40. The bonding structure of claim 39, wherein an end surface of the second conductive via portion is directly bonded to a contact pad of the other element without intervening adhesive.
41. The bonding structure of claim 39 or 40, wherein the non-conductive bonding regions of the microelectronic element and the further element are directly bonded without intervening adhesive.
42. A method of forming a microelectronic structure, the method comprising:
forming an opening at least partially through a substrate, the substrate having a front surface and a rear surface opposite the front surface, the opening extending through the front surface in a direction non-parallel to the second surface;
providing a first conductive via portion in the opening from the front surface;
exposing the first conductive via portion by removing material from the rear surface; and
after the exposing, a fill structure is provided in the opening from the rear surface over the first conductive via portion.
43. The method of claim 42, wherein providing the filling structure comprises: a second conductive via portion is provided in the opening from the rear surface over the first conductive via portion.
44. The method of claim 43, further comprising: after exposing, recessing the first conductive via portion from the back surface.
45. The method of claim 44, further comprising: a second barrier layer is provided over the first conductive via portion after the first conductive via portion is provided but before the second conductive via portion is provided.
46. The method of claim 45, further comprising: a first barrier layer is provided along sidewalls of the first conductive via portion.
47. The method of claim 46, further comprising: the first barrier layer is provided prior to providing the first conductive via portion.
48. The method of claim 46 or 47, wherein providing the second barrier layer comprises: the second barrier layer is provided along the first barrier layer between the first barrier layer and the second conductive via portion.
49. The method of any one of claims 43 to 48, further comprising: a dielectric layer is provided on the bulk semiconductor portion, the dielectric layer at least partially defining the rear surface of the substrate, the second conductive via portion extending through the dielectric layer such that an end of the second conductive via portion is flush with or recessed from the rear surface of the substrate.
50. The method of claim 49, further comprising: the dielectric layer is prepared for direct bonding to another element.
51. The method of claim 50, further comprising: a dielectric barrier layer is provided on the bulk semiconductor portion, the dielectric bonding layer being disposed on the dielectric barrier layer.
52. The method of claim 50 or 51, further comprising: the dielectric layer is directly bonded to another element without intervening adhesive.
53. The method of claim 52, further comprising: an end surface of the second conductive via portion is directly bonded to a contact pad of the other element without intervening adhesive.
54. The method of claim 42, wherein providing the filling structure comprises: a dielectric layer is provided in the recess over the first conductive via portion.
55. The method of claim 54, further comprising: removing a portion of the substrate from the rear surface such that the first conductive via portion protrudes from the rear surface of the substrate, and removing the dielectric layer to expose the conductive via.
56. The method of claim 55, wherein removing the portion of the substrate comprises: the rear surface of the substrate is etched.
57. The method of claim 56, further comprising: a second backside dielectric layer is provided over at least the etched back surface of the substrate and a portion of the dielectric layer disposed in the recess.
58. The method of claim 57, further comprising: at least a portion of the second backside dielectric layer is removed, the at least portion covering the portion of the dielectric layer disposed in the recess.
59. The method of claim 57 or 58, further comprising: the second backside dielectric layer is planarized and the first conductive via portion is recessed relative to the second backside dielectric layer.
60. A method of forming a microelectronic structure, the method comprising:
forming an opening partially through a substrate, the substrate having a front surface and a back surface opposite the first surface, the opening extending through the front surface in a direction non-parallel to the front surface;
filling the opening with a first conductive via portion;
exposing the first conductive via portion by removing material from the rear surface; and
after exposing the first conductive portion, a portion of the opening is refilled with a filling structure.
61. The method of claim 60, wherein refilling the portion of the opening with the filling structure comprises: a second conductive via portion is provided in the opening from the rear surface over the first conductive via portion.
62. The method of claim 61, further comprising: after exposure, the first conductive portion is recessed to define the portion of the opening.
63. The method of claim 62, further comprising: a second barrier layer is deposited over the first conductive via portion after recessing and before refilling.
64. The method of claim 63, further comprising: a first barrier layer is deposited to line the opening prior to filling.
65. The method of claim 64, wherein depositing the second barrier layer comprises: the second barrier layer is deposited over the first barrier layer in the portion of the opening.
66. The method of claim 60, wherein refilling the portion of the opening with the filling structure comprises: a dielectric layer is provided over the first conductive via portion in the recess.
67. The method of claim 66, further comprising: removing a portion of the substrate from the rear surface such that the first conductive via portion protrudes from the rear surface of the substrate, and removing the dielectric layer to expose the conductive via.
68. The method of claim 67, wherein removing the portion of the substrate comprises: the rear surface of the substrate is etched.
69. The method of claim 68, further comprising: a second backside dielectric layer is provided over at least the etched back surface of the substrate and a portion of the dielectric layer disposed in the recess.
70. The method of claim 69, further comprising: at least a portion of the second backside dielectric layer is removed, the at least portion covering the portion of the dielectric layer disposed in the recess.
71. The method of claim 69 or 70, further comprising: the second backside dielectric layer is planarized and the first conductive via portion is recessed relative to the second backside dielectric layer.
72. A joint structure, comprising:
a first element having a first engagement surface and a second element having a second engagement surface, the first element having a third surface opposite the first engagement surface; and
A via structure disposed in an opening extending at least partially through the first element from the first bonding surface in a direction non-parallel to the first bonding surface, the via structure including first and second conductive via portions in contact with each other, the second conductive via portion being at least partially embedded within a bonding material at the bonding surface of the first element, the bonding material and the second conductive via portion being directly bonded to the bonding surface of the second element without intervening adhesive.
73. The bonding structure of claim 72, wherein non-conductive bonding regions of the first and second elements are bonded directly without intervening adhesive.
74. A method of forming a microelectronic structure, the method comprising:
providing a substrate having an opening and a conductive via disposed in the opening, the conductive via extending partially through the substrate from a first face toward a second face of the substrate;
removing a portion of the substrate from the second side to expose the conductive via;
removing a portion of the conductive via from the second side of the substrate to form a recess;
Providing a dielectric layer in the recess over the conductive via;
further removing a portion of the substrate from the second side such that the conductive via protrudes from the second side of the substrate; and
the dielectric layer is removed to expose the conductive via.
75. The method of claim 74, wherein removing the portion of the substrate comprises: at least one of grinding and polishing the second.
76. The method of claim 75, wherein at least one of grinding and polishing comprises: planarizing the substrate and the conductive via.
77. The method of claim 74, wherein removing the portion of the conductive via comprises: etching the conductive via.
78. The method of claim 74, wherein providing the dielectric layer comprises: a first backside dielectric layer is provided over the backside of the substrate and in the recess.
79. The method of claim 78, wherein providing the first backside dielectric layer comprises: a plurality of dielectric layers is provided.
80. The method of claim 79, wherein providing the plurality of dielectric layers comprises: a first silicon nitride layer is provided over the back surface of the substrate and over the conductive via, and a second silicon dioxide layer is provided over the first silicon nitride.
81. The method of any one of claims 78 to 80, further comprising: a portion of the first backside dielectric layer disposed over the backside of the substrate is removed prior to further removing the portion of the substrate.
82. The method of claim 78, wherein further removing the portion of the substrate comprises: the back surface of the substrate is etched.
83. The method of claim 82, further comprising: a second backside dielectric layer is provided over at least the etched backside of the substrate and a portion of the first backside dielectric layer disposed in the recess.
84. The method of claim 83, further comprising: at least a portion of the second backside dielectric layer is removed, the at least portion covering the portion of the first backside dielectric layer disposed in the recess.
85. The method of claim 83 or 84, further comprising: the second backside dielectric layer is planarized and the conductive via is recessed relative to the second backside dielectric layer.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US63/131,263 | 2020-12-28 | ||
| US202163216389P | 2021-06-29 | 2021-06-29 | |
| US63/216,389 | 2021-06-29 | ||
| PCT/US2021/073122 WO2022147429A1 (en) | 2020-12-28 | 2021-12-27 | Structures with through-substrate vias and methods for forming the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116830256A true CN116830256A (en) | 2023-09-29 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202180092102.9A Pending CN116830256A (en) | 2020-12-28 | 2021-12-27 | Structure with through-substrate via and method of forming the same |
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| CN (1) | CN116830256A (en) |
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