TWI230392B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TWI230392B
TWI230392B TW091111316A TW91111316A TWI230392B TW I230392 B TWI230392 B TW I230392B TW 091111316 A TW091111316 A TW 091111316A TW 91111316 A TW91111316 A TW 91111316A TW I230392 B TWI230392 B TW I230392B
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Taiwan
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drain
charge
source
transistor
patent application
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TW091111316A
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Pierre Christophe Fazan
Serguei Okhonin
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Innovative Silicon Sa
Ecole Polytech
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Priority claimed from EP01810587A external-priority patent/EP1271547A1/fr
Priority claimed from EP02405247A external-priority patent/EP1351307A1/fr
Priority claimed from EP02405315A external-priority patent/EP1355357A1/fr
Application filed by Innovative Silicon Sa, Ecole Polytech filed Critical Innovative Silicon Sa
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Publication of TWI230392B publication Critical patent/TWI230392B/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C2211/4016—Memory devices with silicon-on-insulator cells
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/905—Plural dram cells share common contact or common trench
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/907—Folded bit line dram configuration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/982—Varying orientation of devices in array

Description

1230392 五、發明說明（ι) 本發明係關於一種半導體裝置，尤其是但又不限於使用 SOI(矽在絕緣體上）技術之DRAM記憶體裝置。爲人所熟 知之DRAM記憶體，其中的每一個記憶體單胞都是由一 個電晶體和一個電容器所組成的，而儲存在DRAM中之 資料的2位元1和0，則是藉由每一個單胞電容器的充電 和放電狀態表示。電容器的充電和放電係藉由對應電晶體 的切換作控制，而其也控制儲存在單胞中之資料的讀取。 此種裝置發表在美國專利第3 3 87286號，而且將會被精於 此項技術的人士所熟知。 結合M0SFET(金氧半場效電晶體）型裝置之半導體裝置 已廣爲人知，而採用SOI(矽在絕緣體上）之裝置則變得愈 來愈可用。SOI技術牽涉到載有被一層矽塗著之絕緣二氧 矽層之矽基板的製備，其中個別的場效電晶體係藉由形成 由相反極性摻雜矽之本體分隔之極性摻雜矽的源極和汲極 區所形成的。 SOI技術有缺點，因爲各個電晶體的本體區係與下層之 矽基板電性絕緣的，所以在某些狀況下，本體會發生放電 。此會影響電晶體的電性能，而且通常是不想要的影響。 通常採取多方面的量測可以避免此效應的發生，此詳細說 明在由 Ter ukazu Oh no 等人發表在 IEEE Transactions on Electron Devices 1998年5月第45期第5卷，一篇名爲a suppression of parasitic bipolar action in ultra thin film fully depleted CMOS/simox by Ar-ion implantation into S o u l· c e / d r a i n r e g i ο n s 之論文中 0 1230392 五、 發明說明 ( 2) 美國專 利 第 4298962號中也有 說明已 知的 DRAM裝置 ， 該 DRAM 係 由許多 單胞形成， 每一個單胞都是由直接 形 成在矽 基 板 上之IGFET(絕緣閘極場效電晶體）所構成 〇 此 DRAM 能 使 電荷載 ,子從相反於位在源極或源極中之源 極 和汲極 區 極 性的半 導體雜質區 注入， 或是 從矽基板注 入 電 荷載子 0 此已知 之 裝 置有缺 點，即其至 少要有 四個 用以操作之 終 端 接點（連接到汲極， 源極和極性相反於基板之雜質區） ， 其 會增加 裝 置 的複雜 性。此外， 每一個 單胞 的記憶功能 只 有在外加 電 壓 到電晶 體源極和汲 極時確 保， 此會影響裝 置 的 可靠度 而 儲存資 訊的寫入， 讀取和 更新 必須在所謂 的 穿 透模式下 執 行，此 會造成置消耗大量 的電 能。 被揭露 的 美 國專利 第 5448513 號企圖 使用 SOI技術製 造 DRAM 記 憶 體 。在此 已知的裝置 中。每 一個 記憶體單胞 都 是 由兩個 電 晶 體所組 成，其中之 一係用 以將 資料寫入記 憶 體 單胞， 而另 一則是 用以讀取儲 存在裝 置中 的資料。由 兩 個 個別的 電 晶 體組成 每一個單胞 的結果 ，就 是每一個單 胞 需 要4個 用 以 操作之 終端接點， 此會增 加裝 置的複雜性 1 而 且提供 兩 個 電晶體 的結果，就 是增加 每一 個記億體單 胞 所 需的表 面 積 〇 本發明 之 優 選實施 例試圖克服 上述習 知技 術之缺點。 根據本 發 明 之方向 ，所提供之 半導體 裝置 包含： 基板； 至少一 個 提 供在該 基板某一側 -4- 上之資 料儲 存單胞，其 中 1230392 五、發明說明（3) 每一個包含個別的場效電晶體之該資料儲存單胞，包含（i) 源極；（ii)汲極；（iii)位在該源極和該汲極間之本體，而 且適合至少暫時性保存產生在該本體中之淨電荷，使該淨 電荷的量可以電應用到該電晶體的輸入訊號作調整；及 (iv)至少一個鄰近該本體之閘極；及 電荷調整裝置，藉由在至少一個對應的該閘極和對應的 該汲極之間，和在對應的該源極和該汲極之間，應用第一 預定電壓訊號，至少可以消除部分因該輸入訊號對該淨電 荷所作之調整。 本發明係基於產生且保留在電晶體本體中之多出電荷之 前述不想要的特性，可以用以表示資料之驚人的發現。藉 由提供可以將資料當作電荷儲存場效電晶體的本體中之半 導體裝置，因爲每一個資料單胞，例如，當該半導體裝置 係DRAM記憶體時，就不再需要電容器，而可以只由單 一電晶體組成，所以此提供一個優點，即可以提供遠高於 習知技術層次之積體電路。此外，因爲該電荷係產生在場 效電晶體的本體中（提供源極或汲極之基板或雜質區的相 對位置），所以此提供另一個優點，即不需要製作特別的 接點連接基板或雜質區，因此可以減少操作裝置所需之終 端接點數。 在優選點施例中，該輸入訊號包含應用在至少一個對應 的該閘極和對應的該汲極之間，和在對應該源極和汲極之 間之第二預定電壓訊號。 該裝置可爲記憶體裝置。 1230392 五、發明說明（4) 該裝置可爲感測器，而且至少儲存在一個被使用的該本 體中之電荷表示物理參數。 輸入訊號包含電磁輻射。 該裝置可爲電磁輻射感測器。 該裝置還可包含至少部分覆蓋該基板之第一絕緣層，其 中每一個該資料儲存單胞體提供在遠離該基板之該第一絕 緣層的那一邊之上。 該裝置還可包含提供在至少一個的該本體和每一個對應 的該閘極之間之個別的第二絕緣層。 在優選實施例中，至少一個的該電晶體包含許多在至少 一個對應的該本體和對應的該第二絕緣層之間之介面附近 ，用以捕捉跟儲存在本體中之電荷載子極性相反的電荷載 子之缺陷。 此提供能使儲存在電晶體本體中之電荷，因儲存電荷載 子與被捕捉在介面附近而極性相反之電荷載子複合而減少 之優點。在該介面附近的缺陷密度可在1 09和1 0 12/cm 2之 間。 該裝置還可包含資料讀取裝置，用以藉由在至少一個對 應的該閘極和該汲極之間，和在該源極和該汲極之間，應 用第三預定電壓訊號，使電流在至少一個的該資料儲存單 胞之該源極和該汲極之間流動。 第一絕緣層可包含許多絕緣層。 至少一個的該資料儲存單胞適合儲存至少二個該電荷可 辦別的階層。 1230392 五、 發明說明 ( 5 ) 在 優 •:巳B 實 施 例 中 ， 至 少一個的該資料儲存單胞適合儲存 至 少 二 個 該 電 荷可 辨 別的階層。 此 提 供 可 以 用 表 示 資 料儲存單胞中之資料有更多可辨別 的 電 荷 階 層 儲 存在各 單胞中之資料可以有更多的位元之 優 點 〇 例如 爲 了 表 示 η位元的資料，需要2n辨別的電 荷 階 層 結 果 會 產 生 高密度資料儲存裝置。 至 少 -- 個 的 該 電 晶 體 之汲極/本體電容可大於對應之源 極 /本體電容。 此 提 供 可 以 減 少 應 用 到電晶體，以調整儲存在本體中電 荷所 需 的 電 壓 然 後 改 善裝置操作的可靠度之優點。 至 少 —* 個 的 該 電 晶 體 之本體，其在該汲極附近的摻雜密 度 可 高 於在 該 源 極 附 近的摻雜密度。 在 至 少 —* 個 的 該 電 晶 體的汲極和本體之間之介面面積， 可大於在 源 極 和本 體 之 間之介面面積。 共 源 極 和 /或汲極區可在該裝置鄰近的電晶體之間共用 此 提 供改 善 裝 置 可以 小型化的程度之優點。 根 據 本 發 明 的 另 一 方 向，提供一種將資料儲存在包含基 板 和 至 少 一 個 提 供在 該基板某一側上之資料儲存單胞之 半 導 體 元 件 中 之 方 法 其中每一個包含個別的場效電晶體 之 該 資 料 儲 存 單 胞 包含（i)源極；（Π )汲極；（iii )位 在 該 源 極 和 該 汲 極 之 間 之本體，而且適合至少暫時性保存 產 生在 該 本 體 中 之 淨 電 荷，使該淨電荷的量可以由應用到 該 電 晶 體 的 輸 入 訊 號 作 調整；及（iv )至少一個鄰近該本 體 之 閘 極 該 方 法 之 步 驟包含： 將 第 一 預 定 電 壓 訊 號 應用在至少一個對應的該閘極和對 應 的 該 汲 極 之 間 5 和在 對應的該源極和該汲極之間，至少 -7- 1230392 五、發明說明（6) 部分消除該浮電荷因該輸入訊號輸入訊號所作之調整。 該方法還可包含：將第二預定電壓訊號應用在該資料儲 存單胞至少一個的該閘極和對應的該汲極之間，和在對應 的該源極和該汲極之間步驟。應用第二預是電壓訊號之步 驟，可以藉由穿透效應調整保存在對應的該本體中之電荷。 此提供能使電晶體在非導通的狀態完成電荷調整之優點 ，其中只有電流係從電晶體的本體移除少數電荷載子。然 後，此致使電荷調整操作只有非常低的功率消粍。此也提 供可以將相當高的電荷儲存在電晶體的本體中之優點，因 爲本發明相信：電荷基本上係儲存在電晶體的整個本體之 中，而不只是在第一絕緣層附近之部分的電晶體。結果， 可以儲存表示幾個位元資料之電荷的幾個階層。 電荷可以藉由在至少一個的該閘極和對應的汲極之間電 壓訊號的應用，使其在對應的本體和汲極之間之介面作調 整，本體和汲極之價電帶和導電帶的變形，而使電子可以 藉由穿透效應從價電帶注入到導電帶，造成在本體中多數 載子的形成。該電荷可以藉由電子從價電帶穿透到至少一 個的該場效電晶體之閘極而調整。 應用該第一預定電壓訊號之步驟，可包含：應用電壓訊 號在至少一個的該閘極和對應的該汲極之間，使得至少會 有一些儲存在對應本體中之電荷載子，會與在該本體中相 反極性的電荷載子複合。 此提供儲存特殊電晶體本體之電荷，不用將電晶體切換 成導通狀態就能調整，結果，電荷調整可以在非常低的功 1230392 五、發明說明（7) 率消耗下完成之優點。此特徵尤其是在含有大量電晶體之 半導體元體的情形下特別有利，如個別的像素係由電晶體 •提供之檢光器。在原理下操作之過程稱爲電荷激勵，而更 詳細的說明係在由Groeseneken等人發表在1984年IEEE Transactions on Electron Devices 第 3 1 期，第 42 頁到第 53 頁’ ·一篇名爲 A reliable approach to charge pumping Measurement in MO S transistors之論文中，其提供其在非 常低的電流階級下操作，致使可以根據該過程最小化裝置 操作的功率消耗之優點。 該方法還可包含應用至少一個的該電壓訊號之步驟，其 中該電壓訊號包含致使導通通道形成在源極和汲極之間之 第一部份，其中通道含有電荷載子，其極性相反於儲存在 該本體中之電荷載子；及防止通道形成，且使至少一些該 儲存的電荷載子朝向已先被該通道佔領之位置遷移，而與 該通道中極性相反於之前的電荷載子複合之第二部份。 該方法還可包含重複將至少一個的該電壓訊號應用在十 分快速的單電荷調整操作步驟之步驟，在相反極性的該電 荷載子完全遷移到該源極或該汲極之前，致使至少一些儲 存在本性中之該電荷載子與相反極性的電荷載子複合。 現在將參考附圖說明發明的優選實施例，這只是當作舉 例，而沒有任何限制的意思，其中 第1圖爲用在本發明半導體裝置之M0SFET型SOI電 晶體之第一實施例的示意圖； 第2圖爲應用到第1圖的電晶體，以根據第一種方法， 1230392 五、發明說明（8) 在電晶體的本體中產生正電荷之電脈衝時序； 第3圖爲應用到第1圖的電晶體，以根據第一種方法， 在電晶體的本體中產生負電荷之電脈衝時序； 第4圖爲對於正向充電，不充電和負向充電之電晶體的 本體，第1圖之電晶體的源極一汲極電流對閘極電壓的關 係圖； 第5a圖爲用在本發明半導體裝置之第二實例的SOI M0SFET電晶體之示意圖； 第5b圖爲說明第5a圖之電晶體在應用閘極電壓時，對 電晶體的價電帶和導電帶的影響； 第6a圖到第6c圖爲本發明用以消除儲存在第1圖的電 晶體本體中之正電荷的第一種方法； 第7a圖到第7d圖爲本發明用以消除儲存在第1圖的 電晶體本體中之正電荷的第二種方法； 第8圖爲用在本發明半導體裝置之第三實例的SOI M0SFET電晶體之示意圖； 第9圖爲用在本發明半導體裝置之第四實施例的電晶 體閘極’源極和汲極區之不意圖； 第10圖和第Π圖爲第1圖之電晶體的多重充電階級； 第12圖爲根據弟6圖和弟7圖所完成的第1圖之電晶 體的多重充電階級； 第1 3圖爲本發明所用之部DRAM記憶體裝置和含有第 1，5，6，7，8或9圖之電晶體之示意圖； 第1 4圖爲本發明另一實施例之部分DRAM記億體裝置 -10- 1230392 五、發明說明（9) 和含有第1，5，6，7，8或9圖之電晶體之示意圖； 第15圖爲第14圖之部分DRAM記憶體裝置之平面圖； 第1 6圖爲第i 5圖中沿著線a-A之橫截面圖； 第1 7圖爲與DRAM性能相較之積性電路處理器性能的 發展圖；及 第18圖爲本發明所用之感光器和含有第1，5, 6, 7， 8或9圖之電晶體之示意圖。 首先參考第1圖，NMOS SOI (絕緣體上之矽） MOSFET (金氧半場效電晶體）包含以二氧化矽層12塗著 之的矽晶圓1 0，晶圓1 0和層1 2構成基板1 3。形成在基 板1 3上之層丨4係由以雜質摻雜而在η型材料上形成源極 1 8之矽島1 6，與二氧化矽的之蜂巢式絕緣結構24在一起 之Ρ型材料本體20和η型材料汲極22所構成的，該蜂巢 式結構可以被許多島1 6塡滿。源極1 8和汲極22延伸穿 過整過矽層14的厚度。絕緣膜26形成在本體20之上， 而摻雜之半導體材料的閘極28則提供在介電質膜26上。 用以製造第1圖電晶體之生產製程步驟，化學成分和摻雜 摻雜條件將會被精於此項技術的人士所熟知，同時其也由 A. J.Auberton-Herve更詳細地發表在1 996年IEDM之 A S ΟI : M a t e 1· i a 1 s t 〇 S y s t e m s硏討會中。此篇論文還揭露 此種電晶體因爲本體20係浮動電性之事實，所以會造成 電性上的不穩定性，因此其可以獲得電荷，此取決於應用 到電晶體之電壓脈衝序列。 示於第1圖之電晶體，精於此項技術的人士將此種電晶 -11- 1230392 五、發明說明（1〇 ) 體稱之爲”部分空乏型”（PD )，其中空乏區（即在相對極 性形式的半導體之間形成接面之區域，而且此區域並無自 由電荷載子）並沒有佔據整個矽層1 4的厚度。 現在參考第2圖，爲了要在第1圖NMOS電晶體的本 體中產生正電荷，先將閘極電壓Vg和汲極電壓vd，以源 極電壓起始化爲零。在時間tG，使閘極電壓爲_ 1 .5 v，而在 時間U + Ato (其中Δΐ〇可以大於，小於或等於零），使汲 電壓Vd爲-2V，而源極電壓仍然爲零。藉由將負電壓脈衝 應用到閘極，而將更負的電壓脈衝應用到汲極，使負電荷 集中形成在閘極28附近的本體20中，而正電荷則集中形 成在絕緣層1 2附近的本體中。在此同時，會在本體20之 中形成連結源極1 8和汲極22之傳導通道，以允許電子在 源極1 8和汲極22之間傳導。此允許電子自源極1 8和汲 極22之間傳導。此允許電子自源極1 8和/或汲極22引進 該通道。 如第2圖所示，相對於源極，汲極22爲負電壓之應用 ，會因在源極附近的撞擊離化而產生電子一電洞對。累積 在浮動本體中之電洞會產生正電荷。 然後，在時間1，汲極電壓Vd回到零，而在時間 ti + Δη，閘極電壓Vg回到零，以移除在源極18和汲極22 之間之傳導通道，時間區間tl-tG典型在幾個奈秒和幾十 個奈秒之間，而At!則爲1奈秒的階次。藉由應用正汲極 電壓脈衝，也可在本性2 0中產生正電荷’此取決於源極 ，汲極和閘極彼此相對之電壓。爲了要在本體中產生正電 -12- 1230392 五、發明說明（11) 荷，汲極電壓必須先閘極電壓切回零。 現在參考第3圖，藉由在tQ時將閘極電壓Vg增加到 + 1 V，而源極和汲極電壓則保持在零，然後在時間“ + 時，汲極電壓Vd減少到-2V，而源極電壓則保持在零，就 可在本體20之中產生負電荷。然後分別在時間tl和 h + M!，使閘極電壓VJ汲極電壓Vd成爲零，其中Μ丨 可以爲正或負（或零）。相對於應用到源極1 8和汲極22 的電壓，閘極2 8爲正電壓之應用，會在源極1 8和汲極 22之間再次導致通道的形成，此與參考第2圖之上述多 出正電荷形成的情形相同。應用到閘極28之正電壓也可 以在閘極28附近產生集中在本體20中之負電荷，而正電 荷則集中在本體遠離閘極28的部分，即毗鄰絕緣層1 2。 將負電壓應用到汲極22的結果，使得本體一汲極接面 爲順向偏壓，此結果會使電洞自本體20之外傳導到汲極 22。此效應爲會在本體20之中產生多出的負電荷。此處 應該注意，在這些偏壓條件之下，藉由撞擊離化所產生的 電洞是相當微弱的。或者，可以將正電壓脈衝應用到汲極 和閘極，結果，本體一源極接面爲順向偏壓，而電洞則自 本體移至源極。同理，不用在本體20中產生負電荷，而 改以儲存在本體中之正電荷也可以被移除。 現在參考第4圖，汲極電流Id與應用的閘極電壓Vg有 關，圖示汲極電壓爲0.3 V時的此種關係，由線3 4，3 6， 和38分別表示具有正或負多出電荷，或零多出電荷之本 體20。因此可以藉由將校正電壓應用到閘極28和汲極22 -13- 1230392 五、發明說明（12) 及藉由量測汲極電流Id，知道有可能可以決定本體20是 否是帶正電荷或負電荷，或是否不帶電。此現象可以致使 第1圖的電晶體被用以當作資料儲存單胞，不同的帶電層 次表示資料是在高準位和低準位狀態，或是某些要被量測 的物理參數，此將更詳細的說明於下。 參考第5 a圖，其中與第1圖之實施例共同的部分以相 像的參考數字表示，但是加1〇〇，圖示SOI電晶體的另一 實施例，其中電晶體係藉由穿透效應使正電荷儲存在其本 體120之中。第5a圖之電晶體係藉由一連串將會被精於 這些技術的人士熟知之微影製程’摻雜和蝕刻操作所製造 的。電晶體係以具有1018原子/cm3p型雜質密度之本體 120和1021n型原子/cm3之汲極122的0.13 μιη技術所製作 的。絕緣層126具有2nm階次之厚度。 爲了要操作第5a圖之電晶體，源極保持在0V，閘極電 壓Vg爲—1.5V，而汲極電壓Vd則爲+1V。示於第5b圖之 價電帶Bv和導電帶Be被扭曲的結果，會在本體1 20和汲 極1 22的接面造成穿透效應。這些能帶的曲褶可以藉由 lMV/cm階次之電場達成，其會造成電子由汲極122引出 ，而相關的電洞則留在本體1 20之中。此物理現象被稱爲 AGIDL (閘極引發的汲極漏電流），例如，其被更詳細的 說明在由Chi Chang等人發表在1 987年IEDM技術摘要 ，第 714 頁之 A Corner Field Induced Drain Leakage in Thin Oxide MOSFETS 的論文中。 對於參考第1圖到第3圖之說明，第5 a圖之帶電操作 -14- 1230392 五、發明說明（13) 具有在帶電過程爲電子因穿透效應而自本體120引出期間 ，才有電流流動之優點。結果，帶電操作只消耗非常低的 功率。再者，此處己發現：可儲存在本體120中之電荷， 比起先前的方法所得的高很多（大約是多2倍）。本發明 相信這是電荷儲存遍及整個本體120之體積，而不只是儲 存在本體1 2 0紙鄰絕緣層1 1 2的部份之結果。 本發明將會被精於此項技術之人士所瞭解，參考NMOS 電晶體說明之第5a圖的過程，也可以應用到PMOS電晶 體，其中閘極電壓爲正，汲極電壓爲負，及電洞由汲極引 出，而電子則被捕捉住。 現在參考第6a圖到第6c圖，其中與第1圖之實施例共 同的部份以相像的參考數字表示，但是加200，其說明移 除儲存在電晶體本體220中之電荷的過程。電晶體的本體 220和絕緣膜226要藉由幾個原子層厚，提供缺陷形成位 置，使與逮捕電子之介面23 0分隔是很重要的。 爲了要移除儲存在本體220中之電荷，將示於第6a圖 上部之週期性訊號應用到閘極，對第6a圖之即使說明係 以插入的箭頭圖示。開始時，將0V的電位應用到源極 21 8和汲極222，然後再將0.8V的電位應用到閘極228。 此具有在介面230產生傳導通道232之效應，而且電子自 源極21 8和/或汲極222引入通道232。將正電壓應用到閘 極228的結果，就是通道232具有高密度的電子234，其 中有些被缺陷捕捉在介面23 0。 當-2.0V的電壓被應用到閘極228時，如第6b圖所示 -15- 1230392 五、發明說明（14) ，通道232就會消失，但是束縛電子234仍然留在介面 23 0之中。此外，應用到極228的電壓容造成電洞236朝 向介面23 0遷移，使它們與束縛電子234複合。如可以在 第6c圖看到的，當具0.8V電壓的另一個週期開始應用到 閘極228時，又再一次形成通道232。但是，與示於第6a 圖的情形相較，電洞236的數自已減少。 介面230最好具有1〇9和1〇12每cm2之間之缺陷密度， 此密度和移除形成表示在裝置性能之間可接受的折衷之儲 存電荷的粒子之振盪需求數，係受限於缺陷數目和被捕捉 電子數的幫助。脈衝期間典型約爲1 0ns，上升和下降時間 爲1 ns之階次。此處也應該注意到某種電晶體，其也有可 絕緣層2 1 2附近的源極2 1 8和汲極222之間形成通道。在 此種情形下，電荷載子的複合條件稍有不同，但是操作原 理一般是一樣的。 第7a圖圖示一和第6a圖到第6c圖結構相同之電晶體 ，但是其能使儲存電荷比使用在介面23 0之電荷複合之第 6a圖到第6c圖的案例更快速地減少，但不會有電子被束 縛在缺陷。第7a圖圖示電晶體在開始電荷減少處理之前 之狀態，本體220具有多出的電洞23 6。如第7b圖所示 ，藉由應用正電壓，例如0.8V，到閘極22 8，而源極和汲 極則保持在0V，在介面23 0會產生通道23 2。通道23 2包 含多出的電子234，其取決於應用到閘極228之正電壓， 因爲電子係從源極218和/或汲極222引入通道232，所以 自由電子234的數量遠超過出現在本體220之電洞236的 -16- 1230392 五、發明說明（15) 數量。 如第7c圖所示，其圖示可以藉由將應用到閘極228之 訊號的極性快速地反轉，例如從0.8 V到-2.0V，在1〇_12 秒階次的時間內，在包含在本體220中的電洞23 6抵達先 前被通道232佔用的空間之前.，位在通道232中的電子 234沒有時間遷移。電洞23 6和電子234在本體220的內 部複合，而在源極和汲極之間沒有電流流動，但是多出電 子234朝向源極218和汲極222遷移。在此情形下，在非 常短的時間週期之後，所有儲存電荷的電洞236都被複合 ，如第7d圖所示。 爲了要達成要被用在半導體裝置之上述處理的切換速度 需求，有必要儘可能減少電路和控制線的電阻和寄生電容 。在記憶體的案例中，此會限制每條線和每行的電晶體數 。但是，此限制可以藉由大量的增加儲存電荷移除的速度 而顯著地補償。 參考第6圖和第7圖說明之電荷移除過程，可以藉由提 供非對稱性源極/汲極接面，以在汲極側給予較大的接面 電容而增強。在參考第1圖到第3圖說明之裝置中，可以 觀察到：爲了要確保以電荷層級表示之資料狀態的快速寫 入（即在幾個奈秒內），需要使用相當高的電壓，但是因 爲可靠度的問題，所以這些電壓因裝置最佳化而需要減少。 第8圖圖示電晶體的另一個實施例，其中減少移除儲存 在電晶體本體中之電荷所需的電壓。在帶電本體放電期間 ，將脈衝應用到電晶體的汲極和閘極，使得本體/源極或 -17- 1230392 五、發明說明（16) 本體/汲極接面是在順向偏壓。結果，當電晶體被切換到 傳導狀態時，多數載子自帶電的浮動本體移除，以減少通 道中的電流（參見第4個）。 浮動本體的電位可以藉由調整應用到電晶體接點的電壓 而改變，或是藉由改變本體/源極和/或本體/閘極電容而改 變。例如，若電晶體汲極的電位，相較於源極爲正，則浮 動本體的電位可以藉由增加汲極和浮動本體之間的電容而 使其更正。在示於第8圖的裝置中，MOSFET的汲極和源 極具有不同的摻雜縱深。尤其，在汲極附近有形成P +摻 雜區，其可導致汲極和浮動本體之間的電容增加。此可以 藉由先只在汲極側上增加佈植，然後在形成源極和汲極佈 植區之前，將此佈植擴散而製作。另一種方法係藉由使用 不同幾何形狀的汲極和源極，增加汲極和浮動本體之間的 電容耦(合，如第9圖所示。 參考第5圖到第9圖說明之改善的充電和放電技術，可 致使達成在電晶體的未帶電和最高帶電狀態之間有很大的 電流差。例如，在參考第1圖到第3圖所揭露的裝置中， 最大和最小電荷狀態之間的電流差與典型爲裝置寬度的5 到20μΑ/μιη。對於〇·13μιη技術而言，其中會使用0.2到 〇·3 μη的典型電晶體寬度，此意味著可用約爲1到6μΑ之 電流差。至少需要1 μ Α的電流才能感測藉由帶電狀態表 示之資料。 參考第5圖到第9圖所揭露之充電和放電裝置，提供高 達ΙΙΟμΑ/μηι之電流差。對於具有0.2到0·3μηι寬度的裝置 -18- 1230392 五、發明說明（17) 而言，110μΑ/μηι的訊號可用，意思就是可以達成每個裝 置22到3 3 μΑ的電流差。當1 μΑ足以偵測時，就可以知 道：在單一電晶體本體中可以儲存好幾個階層的電荷。 因此，可以儲存多位元的資料，例如，如第1 0圖所示 。第10a圖圖示一簡單的裝置，其中可用兩個階層，而且 可以儲存1個位元的資料。杢第1 Ob圖和第1 〇c圖中，在 最大和最小的充電階層之間的狀態中，可以儲存多位元的 資料。例如，要能夠儲存2個位元的資料，需要3 μ A的 總電流窗，而每個裝置儲存3個位元，需要7 μ A。對於 3 3 μ A之總電流窗，可以在相同的電晶體中儲存對應3 2個 階層的5個位元。在此將會明瞭；藉由儲存由數個資料位 元所組成的資料字元，相對於單一資料位元，使用此種技 術可以大量增加半導體記憶體的儲存容量。 第1 1圖圖示脈衝充電操作對時間的關係。藉由產生起 始的狀態，然後重複地寫入”1”脈衝，或是藉由從最高 的狀態開始，然後重複地寫入π 〇 ’’脈衝，就可以達成不同 階層之間的充電。另一種可能就是使用不同的寫入脈衝， 以得到不同的狀態，例如，可以藉由改變寫入脈衝的振幅 和週期，得到特別的階層。 另一種可圖示在第12圖，其圖示使用參考第6圖和第 7圖說明之電荷泵原理之可達成的階層。在每一個脈衝之 後所移除的電荷量都會造成電流減少，而且藉由改變 電荷泵脈衝的數量，就可以得到各種不同的階層。 如上面所指出的，可以使用電晶體，本體的電荷狀態產 -19- 1230392 五、發明說明（18) 生半導體記憶體裝置，資料”高準位”狀態係以在本體20 上之正電荷表示，而資料”低準位”狀態則以負電荷或零電 荷表示。儲存在電晶體中的資料可以藉由比較電晶體的源 極一汲極電流和未帶電的參考電晶體，自記憶體裝置讀取。 根據此原理操作之DRAM (動態隨機存取記憶體）裝置圖 示於第1 3圖。DRAM裝置係由資料儲存單胞矩陣所形成的 ，每一個單胞都由示於第1，5，6，7，8或9圖之該種場效 應電晶體所組成的，每一列的電晶體源極都連接在一起， 而每一行的電晶體閘極和及極也都接連在一起，電晶體 3 2ij對應位在第i行和第j列之電晶體，在第13圖中凸顯 電晶體3 222。電晶體32ij的閘極28，源極18和汲極22 被分別連接導電軌道4〇i，42i和44j。導電軌道40，42和 44連接到控制單元46和讀取單元48，精於此項技術之人 士將熟悉共結構和操作。源極係經由讀取單元48接地， 或可連接到結定的固定電位。 下面將說明示於第1 3圖之記憶體裝置的操作。 開始時，所有的閘極（軌道40 )都在-2V，而所有的汲 極（軌道44 )和源極（軌道42 )則保持0V。爲了要將狀 態”1”的資料位元寫入電晶體32ij，所有與i行不同之軌道 40仍保持在-2V，而使軌道4〇i爲-1.5V。在軌道4〇i的電 位爲-1.5V的時間期間，所有與j列不同之軌道仍保持在 0V，而使軌道44j爲- 2V。如上參考第2圖之所述，此過 程會在電晶體32ij的本體中產生正電荷’此正電荷表示狀 態” 1 ”之單一資料位元。然後使軌道44j的電位回到0 V， -20- 1230392 五、發明說明（19) 接著使軌道4 0 i的電位回到-2 V。 爲了要將態” 〇 M的資料位元寫入電晶體3 2 i .j，要根據下 列條件：所有的閘極開始時都保持在-2V，而所有的源極 和汲極則都保持在0 V，使軌道4 0 i的電壓爲+ 1 V，其他的 軌道40保持在-2V。在軌道4〇i的電位爲+1V的期間，除 了 j列之外的所有軌道44都保持在0V，但使軌道44j的 電位爲-2V。此會在電晶體的本體中產生淨負電荷，然後 使軌道44j的電位回到0V。接著使軌道4〇i的電位回到-2V。 爲了讀取電晶體32ij的資訊，使與i行不同之軌道40 的電壓爲0V，但軌道4〇i則保持在1 V，然後使與j列不 同之軌道44的電壓爲0V，但軌道44j則保持在+0.3V。 如第1 3圖所示，此能致使在軌道4.4j之上要被決定的電 流，其係在電晶體32ij的本體中之電荷的表現。但是，藉 由應用0.3V之汲極電壓，此也可以提供不像傳統DRAM 裝置，自電晶體32ij讀取資料，電晶體32 ij不用放電之優 點。換言之，因爲自資料儲存單胞讀取資料之步驟不破壞 儲存在單胞中的資訊，所以資料更新（即重寫入電晶體 3 2 ^ )不需像習知技術一樣頻繁。 但是，精於此項技術之人士將會明瞭：電荷遷移且與相 反符號之電荷複合之結果，儲存在電晶體3 2ij的本體中之 電荷會隨時間衰減，該時間取決於一些因素，包含裝置温 度，或輻射或粒子的出現’如撞擊電晶體之光子。此進一 步之應用將更詳細地說明於下。 在參考第1 3圖說明的記憶體單元中，每一個資料儲存 -21 - 1230392 五、發明說明（2〇) 單胞都是藉由位在絕緣蜂巢式結構24中之電晶體3 2所形 成的。鄰近電晶體之源極和汲極，分別位在相同列的兩個 相鄰電晶體之汲極和源極的附近。第二實施之DRAM裝 置示於第1 4圖，其中與第1 3圖之實施相同的部分以相同 的參考數字表示。在第1 4圖之實施例中，對於每一列的 電晶體而言，除了那些位在終端的電晶體之外，每一個電 晶體都將其汲極和源極區與其相鄰的電晶體分享。此幾乎 能使軌道42之數目和在軌道44上之接點的數目減少2倍。 第14圖和第15圖之DRAM裝置的橫截面圖示於第16 圖，該圖係沿著第1 5圖之線A-A所取的。該裝置包含含 有矽晶圓1 〇和絕緣層12之基板1 3，如第1圖所示，其 中源極1 8，本體20和汲極22形成在絕緣層12之上。介 電質膜26提供在本體20之上，而且朝向閘極28的側面 延伸。閘極藉由軌道40相互連接，而源極1 8則藉由軌道 42，經由個別的柱狀物50相互連接，軌道40，42在垂直 第1 6圖的紙面上之方向，彼此相互平行延伸。汲極22藉 由在垂直軌道40, 42的方向上延伸，且在第1 6圖中只 圖示一個之軌道44，經由個別的柱狀物52相互連接。 正如將會被精於此項技術之人士熟悉的，爲了要週期性 更新內含在記憶體裝置之單胞中的資料，交替執行讀取和 寫入操作，對於在討論中在讀取時所檢測的部分電荷會被 補充在電晶體之中。更新的頻率典型的範圍係從1 ms到1 秒，而更詳細的說明則提供在書碼爲ISBNO-7803 60 1 4-1 之 DRAM circuit design —書中。 -22- 1230392 五、發明說明（21) 除了上述使用電晶體本體的充電建構DRAM記憶體裝 置之外，充電過程也可以應用到其他型式之記憶體，如 S R A Μ (靜態隨機存取記憶體）。一種特殊的應用是隱藏 式SRAM的應用。在現代的微處理器（ΜΡυ)中，示於第 17圖之DRAM/MPU性能落差己迫使MPU製造商將—些 記憶體加到MPU之中。此種記憶體稱爲隱藏式記憶體。 例如，Intel 486處理器使用8k位元組的隱藏式記憶體。 此種記憶體被用以儲存MPU經常需要的資訊。在現代的 奔騰（Pentium)處理器之中，己加入高達256k位元組的二 階隱藏式記憶體，以保持其性能。根據產業趨勢，次世代 處理器（例如，l〇GHz奔騰處理器）將需要具有8到32M 位元組之隱藏式記憶體密度之三階隱藏式記憶體。 此種記憶體之前已由6個電晶體的SRAM單胞（6T ) 提供。該種單胞典型佔用100到150F2之面積，此面積相 當的大，其中F係最小特徵尺寸。應用上述之電荷儲在觀 念，1 T ( 1個電晶體）單胞可以取代6T電晶體單胞。整 合邏輯技術，共可以佔用1 〇到1 5F2之面積，此比之前的 小1 〇倍。這是非常重要的，因爲實際製造時，幾1 0個Μ 位元組的6Τ SRAM單胞需要很大的晶粒尺寸。 如上所指出的，儲存在電晶體本體中之電荷也可以表示 一些量測的物理參數，例如光輻射的入射。第1 8圖爲採 用本發明之CMOS影像感測器。 迄今之影像感測器已被製成具有感測裝置之矩陣，每一 個影像感測器都提供一個當作開關之MOS電晶體。爲了 -23- 1230392 五、發明說明（22) 要將包含在各像素中之資訊升壓，像素本身也提供一內建 的放大器。此種像素稱爲主動像素感測器（APS )，而典 型包含幾種裝置：典型具有1個光感測電容器和4個電晶 體之光閘極APS。光二極體APS典型具有1個光感測二 極體3或4個電晶體。在這些APS裝置之中，進入的光 入射在電路上（有時會透鏡），然後打在裝置的感測組件 上。然後完整週期可以允許累積藉由進入的光輻射所產生 之電荷，而且產生幾個ms或幾十個ms之電訊號。然後 將此訊號放大並讀取。該矩陣結構類似於記億體矩陣結構 ，典型的像素尺寸約爲400F2，其中F爲技術最小特徵尺 寸。 在示於第18圖的裝置中，其有可能可以產生具有與光 感測組件和放大器相同時間作用之單一電晶體之全像素。 爲了達成此作用，類似於上述之DRAM的應用，在矩陣 裝置中有放置SOI電晶體。進入的光可以來自頂端或底部 (在此第二種情形下，SOI技術的有利特徵係可以局部移 除感測器矩陣中在埋入的氧化物下之矽基板，以提供易於 從背面照光之選擇）。 操作感測器，需要有重置操作’重置操作係由自浮動本 體移除多數載子（在NM0S電晶體的案例中爲電洞）所構 成的。對NM0S裝置，在DRAM的應用中，此意味著會· 將所有的裝置置於稱爲0的狀態。正如參考第1圖到第3 圖之說明，此重置操作可以藉由電洞的撤離，尤其是可以 藉由參考第6圖和第7圖說明之電何激勵技術而達成。當 已完成重置時（典型爲1 F )’然後光在裝置的本體中產 生電子電洞對。少數載子透過接面被移除’而多數載子則 -24- 1230392 五、發明說明（23) 累積在本體中，其可以允許電荷統合。資訊之讀取類似上 述之DRAM記憶體。此種裝置可達成之像素面積可以和 4F2 —樣小，或是比習知技術之裝置小1 00倍。這些影像 器可以用在各種不同的應用上，如攜帶式錄影機，數位照 像術，薄金屬板凸輪，P C照像機，行動電話，指形印刷 確認等等。 精於此項技術之人士將會瞭解：上面之實施例己藉由只 是舉例但不是侷限任何觀念之方式說明，而各種不同的變 化例和修正例可能並沒有脫離本發明藉由附錄申請專利範 圍所定義之範圍。例如，參考NMOS電晶體說明之過程也 可以應用到PMOS電晶體，在此案例中，儲存電荷係負電 荷，即由電子形成，而在通道中的自由粒子係電洞。在該 案例中，通道係藉由將負電位應用到閘極所產生的。此外 ，在某種S 01電晶體中，基板也可以當作閘極。在該案例 中，絕緣層執行介電質膜的功能，而通道則形成在本體和 絕緣層的介面。此外，本發明可以應用到JFET (接面場 效電晶體）技術和上述之MOSFET技術。 符號之說明 10 石夕晶圓 12 二氧化矽 13 基板 14 石夕層 16 矽島 18 源極 20 本體 22 汲極 24 絕緣結體 26 絕緣膜 -25- 1230392 五、發明說明（24) 28 鬧極 32 電晶體 110 石夕晶圓 1 12 絕緣層 1 14 矽層 118 源極 120 本體 122 汲極 124 絕緣結構 126 絕緣層 128 閘極 210 ΐ夕晶圓 212 二氧化石夕 218 源極 220 本體 222 汲體 226 絕緣體 228 閘極 230 介面 232 通道 234 電子 236 電洞 40 軌道 42 軌道 44 軌道 46 控制單元 48 讀取單元 50 柱狀物 52 柱狀物 -26-

Claims (1)

1230392 六、申請專利範圍 第9 1 111 3 1 6號「半導體裝置」專利案 1 // (9 1年1 0月修正） 六申請專利範圍： 1. 一種半導體裝置，包含： 基板； 至少一^個提供在該基板某一側上之資料儲存卓胞 ，其中每一個包含個別的場效電晶體之該資料儲存 單胞，包含（i )源極；（ϋ )汲極；（iii )位在該源極和 該汲極之間之本體，而且適合至少暫時性保存產生 在該本體中之淨電荷，使該淨電荷的量可以由應用 到該電晶體的輸入訊號作調整；及（i v )至少一個鄰 近該本體之閘極；及 電荷調整裝置，藉由在至少一個對應的該閘極和 對應的該汲極之間，和在對應的該源極和該汲極之 間，應用第一預定電壓訊號，至少可以消除部分因 該輸入訊號對該淨電荷所作之調整。 2·如果請專利範圍第1項之裝置，其中該輸入訊號包 含應用在至少一個對應的該閘極和對應的該汲極之 間，和在對應的該源極和該汲極之間之第二預定電 壓訊號。 3.如申請專利範圍第2項之裝置，其中該裝置係記憶 體裝置。 4·如申請專利範圍第1至3項中任一項之裝置，其中 1230392 六、申請專利範圍 該裝置係感測器，而電荷至少儲存在一個該本體之 中，用以表示物理參數。 5·如申請專利範圍第1至3項中任一項之裝置，其中 該輸入訊號包含電磁輻射。 6·如申請專利範圍第5項之裝置，其中該裝置係電磁 輻射感測器。 7. 如請申利範圍第1至3項中任一項之裝置，還包含 至少部分覆蓋該基板之第一絕緣層，其中每一個該 資料儲存單胞係提供在遠離基板之該第一絕緣層的 那一邊之上。 8. 如申請專利範圍第1至3項中任一項之裝置，還包 含提供在至少一個的該本體和每一個對應的該閘極 之間之個別的第二絕緣層。 9. 如申請專利範圍第8項之裝置，其中至少一個的該 電晶體包含許多在至少一個對應的該本體和對應的 該第二絕緣層之間之介面附近，用以捕捉跟儲在本 體中之電荷載子極性相反的電荷載子之缺陷。 10. 如申請專利範圍第9項之裝置，其中在該介面附近 的缺陷密度係在1〇9和1〇12/cm2之間。 11. 如申請專利範圍第1至3項中任一項之裝置，還包 含資料讀取裝置，用以藉由在至少一個對應的該閘 極和該汲極之間，和在該源極和該汲極之間’應用 第三預定電壓訊號，使電流在至少一個的該資料儲 1230392 &'申請專利範圍 存單胞之該源極和該汲極之間流動。 12·如申請專利範圍第1至3項中任一項之裝置’其中 該第一絕緣層包含許多絕緣層。 13·如申請專利範圍第1至3項中任一項之裝置’其中 至少一個的該資料儲存單胞適合儲存至少二個該電 荷可辨別的階層。 14·如申請專利管圍第1 3項之裝置，其中至少一個的該 資料儲存單胞適合儲存至少三個該電荷可辨別的階 層。 15·如申請專利範圍第丨至3項中任一項之裝置’其中 至少一個的該電晶體之汲極/本體電容大於對應之源 極/本體電容。 16·如申請專利範圍第1 5項之裝置，其中至少一個的該 晶體之本體，其在該汲極附近的摻雜密度高於在該 源極附近的摻雜密度。 17.如申請專利範圍第1 5項之裝置，其中在至少一個的 該電晶體的汲極和本體之間之介面面積，大於在源 極和本體之間之介面面積。 18·如申請專利範圍第1 6項之裝置，其中在至少一個的 該電晶體的汲極和本體之間之介面面積，大於在源 極和本體之間之介面面積。 19.如申請專利範圍第1至3中任一項裝置，其中共源 極和/或汲極區係在該裝置鄰近的電晶體之間共用。 1230392 六、申請專利範圍 20. —種資料儲存方法，係將資料儲存在包含基板，和 至少一個提供在該基板某一側上之資料儲存單胞之 半導體裝置中之方法，其中每一個包含個別的場效 電晶體之該資料儲存單胞，包含：（i )源極；（ϋ ) 汲極；（迅）位在該源極和該汲極之間之本體，而且 適合至少暫時性保存產生在該本體中之淨電荷，使 該淨電荷的量可以由應用到該電晶體的輸入訊號作 調整；及（iv )至少一個鄰近該本體之閘極；該方法 之步驟包含： 將第一預定電壓訊號應用在至少一個對應的該閘 極和對應的該汲極之間，和在對應的該源極和該汲 極之間，至少部分消除該淨電荷因該輸入訊號所作 之調整。 21. 如申請專利範圍第20項之方法，還包含將第二預定 電壓訊號應用在該資料儲存單胞至少一個的該閘極 和對應的該汲極之間，和在對應的該源極和汲極之 間之步驟。 22. 如申請專利範圍第2 1項之方法，其中應用該第二預 定電壓訊號之步驟係藉由穿透效應調整保存在對應 的該本體中之電荷。 23. 如申請專利範圍第22項之方法，其中電荷係藉由在 至少一個的該閘極和對應的汲極之間電壓訊號的應 用，使其在對應的本體和汲極之間之介面作調整， 1230392 六、申請專利範圍 本體和汲極的價電帶和導電帶的變形，使電子可以 藉由穿透效應從價電帶注入到導電帶，造成在本體 中多數載子的形成。 24. 如申請專利範圍第22項之方法，其中該電荷藉由電 子從價電帶穿透到至少一個的該場效電晶體之閘極 而調整。 25. 如申請專利範圍第23項之方法，其中該電荷藉由電 子從價電帶穿透到至少一個的該場效電晶體之閘極 而調整。 26如申請專利範圍第20項到第25項中任一項之方法 ，其中應用該第一預定電壓訊號之步驟，包含：應 用電壓訊號在至少一個的該閘極和對應的該汲極之 間，使得至少會有一些儲存在對應本體中之電荷載 子，會與在該本體中相反極性的電荷載子複合。 27. 如申請專利範圍第26項之方法，還包含應用至少一 個的該電壓訊號之步驟，其中該電壓訊號包含致使 導通通道形成在源極和汲極之' 間之第一部份，其中 通通含有電荷載子，其極性相反於儲存在該本體中 之電荷載子，及防止通道形成，且使至少一些該儲 存的電荷載子朝向己先被該通道佔領之位置遷移， 而與該通道中極性相反於之前的電荷載子複合之第 二部份。 28. 如申請專利範圍第27項之方法，還包含將至少一個
1230392 六、申請專利範圍 的該電壓訊號應用在十分快速的單電荷調整操作步 驟之步驟，在相反極性的該電荷載子完全遷移到該 源極或該汲極之前，致使至少一些儲存在本體之該 電荷載子與相反極性的電荷載子複合。
1230392
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t0+At0 tj+At,
第2匮
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