CN111501013A - 用于先进图案化的软着陆纳米层压层 - Google Patents
用于先进图案化的软着陆纳米层压层 Download PDFInfo
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- CN111501013A CN111501013A CN202010119340.1A CN202010119340A CN111501013A CN 111501013 A CN111501013 A CN 111501013A CN 202010119340 A CN202010119340 A CN 202010119340A CN 111501013 A CN111501013 A CN 111501013A
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/34—Nitrides
- C23C16/345—Silicon nitride
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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Abstract
本发明涉及用于先进图案化的软着陆纳米层压层,具体提供了用于在芯部层上沉积纳米层压保护层以允许在芯部层上沉积供先进多图案化方案使用的高质量保形膜的方法。在某些实施例中,所述方法涉及使用低的高频射频(HFRF)等离子体功率通过基于等离子体的原子层沉积来沉积薄氧化硅或氧化钛薄膜,随后使用高HFRF等离子体功率沉积保形的氧化钛薄膜或间隔物。
Description
本申请是申请号为201410625311.7,申请日为2014年11月07日,申请人为诺发系统公司,发明创造名称为“用于先进图案化的软着陆纳米层压层”的发明专利申请的分案申请。
技术领域
本发明涉及加工衬底的方法,尤其涉及用于在芯部层上沉积纳米层压保护层以允许在芯部层上沉积供先进多图案化方案使用的高质量保形膜的方法。
背景技术
先进的集成电路通常涉及在大批量半导体制造中图案化1x nm的半节距特征。多图案化技术可以允许根据例如193nm的浸没式光刻技术的光刻技术缩放特征尺寸。自对准双图案化是多图案化技术的实例。多图案化技术的量级扩展到11nm半节距及以下存在挑战。
发明内容
本文提供了用于加工半导体衬底以允许沉积供多图案化集成方案使用的高质量保形膜的方法。
一方面涉及通过在衬底上沉积纳米层压层并且在纳米层压层上沉积氧化钛层来加工半导体衬底的方法。所述纳米层压层的厚度在约至约之间且密度低于所述氧化钛层的密度。在各种实施例中,所述方法还包括沉积非晶碳层。在一些实施例中,非晶碳层被图案化。在各种实施例中,纳米层压层包括堆层,该堆层包括两个或更多个副层。在一些实施例中,所述两个或更多个副层包括氧化硅、氧化钛或它们的组合。在某些实施例中,所述堆层仅包括两个副层。在一些实施例中,所述纳米层压层包括氧化硅的第一副层和氧化钛的第二副层。
在各种实施例中,所述纳米层压层是氧化硅或氧化钛。在某些实施例中,所述纳米层压层通过使用例如等离子体增强原子层沉积(PEALD)的基于等离子体的方法被沉积:使所述衬底暴露于含钛前体或含硅前体;使所述衬底暴露于氧化剂;并且在所述衬底暴露于氧化剂的同时启动等离子体。在某些实施例中,所述纳米层压层在约50℃至约150℃之间的温度下被沉积并且所述等离子体在每平方毫米衬底面积的高频射频(HFRF)功率在约1.768×10-4W/mm2至约1.768×10-3W/mm2之间被启动。在某些实施例中,所述纳米层压层在小于约100℃的温度被沉积。可结合本文公开的方法使用的含钛前体的实例是三(二甲基氨基)钛(TDMAT)。含钛前体的实例是双(叔丁基胺)硅烷(SiH2(NHC(CH3)3)2(BTBAS)。
在各种实施例中,所述氧化钛层使用PEALD通过以下被沉积:使所述衬底暴露于含钛前体;使所述衬底暴露于氧化剂;并且在所述衬底暴露于所述氧化剂的同时在每平方毫米衬底面积的HFRF功率至少约为1.768×10-3W/mm2启动第二等离子体。氧化物的实例包括一氧化二氮、氧气、二氧化碳或它们的组合。在一些实施例中,所述氧化钛层可以在约50℃至约400℃之间的温度被沉积。
另一方面涉及通过以下步骤处理半导体衬底的方法:在衬底上沉积芯部层;在芯部层上沉积纳米层压层;并且在纳米层压层上沉积金属氮化物或金属氧化物层。在一些实施例中,芯部层被图案化。在某些实施例中,芯部层可以是非晶碳或光致抗蚀剂。在各种实施例中,所述纳米层压层可以是氧化硅或氧化钛。在一些实施例中,沉积的纳米层压层的厚度在约至约之间。
在某些实施例中,所述纳米层压层使用PEALD通过以下被沉积:使所述衬底暴露于含钛前体或含硅前体;使所述衬底暴露于氧化剂;并且在所述衬底暴露于氧化剂的同时启动等离子体。在各种实施例中,所述纳米层压层在约50℃至约150℃之间的温度下被沉积并且所述等离子体在每平方毫米衬底面积的HFRF功率在约1.768×10-4W/mm2至约1.768×10- 3W/mm2之间被启动。在一些实施例中,所述纳米层压层在小于约100℃的温度被沉积。
在各种实施例中,金属氮化物或金属氧化物层包括氧化钛或氧化硅。金属氮化物或金属氧化物层可以对芯部具有蚀刻选择性。在某些实施例中,所述金属氮化物或金属氧化物层使用PEALD通过以下被沉积:使所述衬底暴露于含金属前体;使所述衬底暴露于氧化剂;并且在所述衬底暴露于所述氧化剂的同时在每平方毫米衬底面积的HFRF功率至少约为1.768×10-3W/mm2启动等离子体。氧化物的实例包括一氧化二氮、氧气、二氧化碳或它们的组合。在一些实施例中,所述金属氮化物或金属氧化物层在约50℃至约400℃之间的温度被沉积。
另一方面涉及一种加工半导体衬底的方法,所述方法包括:(a)使所述衬底暴露于第一含钛前体或含硅前体;(b)使所述衬底暴露于第一氧化剂;(c)在所述衬底暴露于所述第一氧化剂的同时在每平方毫米衬底面积的HFRF功率在约1.768×10-4/mm2至约1.768×10-3/mm2之间启动第一等离子体;(d)使所述衬底暴露于第二含钛前体;(e)使所述衬底暴露于第二氧化剂;并且(f)在所述衬底暴露于所述第二氧化剂的同时在每平方毫米衬底面积的HFRF功率至少约为1.768×10-3W/mm2启动第二等离子体。
在一些实施例中,(a)至(c)在约50℃至150℃之间的温度进行处理。在一些实施例中,(d)至(f)在约50℃至400℃之间的温度进行处理。在一些实施例中,(d)至(f)在比(a)至(c)高的温度下进行处理,使得从(c)到(d)的过渡包括使所述衬底的温度升高至少约50℃,至少约100℃,至少约150℃,或者至少约200℃。
第一含钛前体和第二含钛前体可以是同一种前体,例如,TDMAT。在一些实施例中,第一氧化剂可以与第二氧化剂相同(例如,一氧化二氮、氧气、二氧化碳或它们的组合)。在一些实施例中,有利的是使用不同的氧化剂或混合物。在一些实施例中,所述衬底包括非晶碳。在一些实施例中,非晶碳被图案化。
在各种实施例中,所述方法还包括在启动第二等离子体之后,使所述衬底平面化以暴露所述非晶碳,并且选择性地蚀刻所述非晶碳以形成掩模。
另一方面涉及通过以下步骤图案化半导体衬底的方法:在保形膜沉积在芯部层上之前,在图案化的芯部层上沉积纳米层压保护层;在所述纳米层压保护层上沉积保形膜;平面化所述保形膜以暴露所述芯部;并且选择性地蚀刻所述芯部以形成掩模。
在某些实施例中,芯部层包括非晶碳。在各种实施例中,所述纳米层压保护层包括氧化硅或氧化钛。在某些实施例中,所述纳米层压保护层的厚度在约至约之间。在许多实施例中,所述纳米层压保护层使用PEALD通过以下被沉积:使所述衬底暴露于含钛前体或含硅前体;使所述衬底暴露于氧化剂;并且在所述衬底暴露于氧化剂的同时启动第一等离子体。
在一些实施例中,所述纳米层压保护层在小于约100℃的温度被沉积。在各种实施例中,所述纳米层压保护层在约50℃至约150℃之间的温度下被沉积并且所述第一等离子体在每平方毫米衬底面积的高频射频功率在约1.768×10-4W/mm2至约1.768×10-3W/mm2之间被启动。
在一些实施例中,所述氧化钛层使用PEALD通过以下被沉积:使所述衬底暴露于含钛前体;使所述衬底暴露于氧化剂;并且在所述衬底暴露于所述氧化剂的同时启动第二等离子体,此时每平方毫米衬底面积的HFRF功率至少约为1.768×10-3W/mm2。
另一方面涉及一种用于加工半导体衬底的设备,所述设备包括:一个或多个处理室;进入所述处理室的一个或多个气体入口和相关的流量控制硬件;HFRF发生器;以及具有至少一个处理器和存储器的控制器,使得所述至少一个处理器和所述存储器彼此通信连接,所述至少一个处理器至少操作性地连接所述流量控制硬件以及HFRF发生器;并且所述存储器存储计算机可执行指令,所述计算机可执行指令用于:使所述衬底暴露于含金属前体;使所述衬底暴露于第一氧化剂;在所述衬底暴露于所述第一氧化剂的同时在HFRF功率为约12.5W至约125W之间启动第一等离子体;使所述衬底暴露于含钛前体;使所述衬底暴露于第二氧化剂;并且在所述衬底暴露于所述第二氧化剂的同时在HFRF功率至少约为125W启动第二等离子体。
以下参照附图进一步描述这些和其他方面。
附图说明
图1至图11是根据公开的实施例的集成方案的示意性描述。
图12至图18是根据公开的实施例的集成方案的示意性描述。
图19是根据公开的实施例的方法的工艺流程图。
图20A和图20B是根据公开的实施例的方法的工艺流程图。
图21是用于实施根据公开的实施例的方法的反应室的图示。
图22是根据公开的实施例的可以用于执行操作的多站设备的图示。
图23A至图23C是在执行根据公开的实施例的方法的实验中获得的沉积膜的图像。
具体实施方式
在以下描述中,阐述了许多具体细节以便提供对提出的实施例的透彻理解。公开的实施例可以在没有一些或所有的这些具体细节的情况下实施。在其他实例中,未详细描述公知的方法操作以便不会不必要地模糊公开的实施例。尽管将会结合具体实施例描述公开的实施例,但是应当理解,这些实施例并不旨在限制公开的实施例。
制造半导体器件通常涉及在集成制造过程中沉积一个或多个薄膜并且可以包括图案化步骤。多图案化技术用于制造先进集成电路,例如,具有更小的特征或更高纵横比或者低至2x或1x nm节点的集成电路。术语“1x”节点的意思是在10nm与19nm之间的处理节点,并且术语“2x”节点的意思是在20nm与29nm之间的处理节点。多图案化的实例是自对准双图案化,这使得常规的光刻法所形成的图案的特征的数量翻倍。随着器件变得更小,通过使用先进的多图案化技术,例如,四重图案化或“四图案化”,可以获得更窄的半节距特征。
图1至图11给出了四图案化方案的实例。图1提供了在多层堆层中(例如,在适于半导体加工的晶圆上)可以包括的各种层的实例的示意性图示。图1中的多层堆层包括形成为硬掩膜104顶部上的第一芯部(也称为第一心轴)的第一芯部层103,该第一芯部可以在前一个处理中通过光刻法限定。硬掩膜104可以在第二芯部层105的顶部上,该第二芯部层本身沉积在层107上。层107可以包括硬掩膜层107a、覆盖层107b和硬掩膜层107c,它们可以用作图案化后续目标层150的掩模。阻挡层、覆盖层或蚀刻停止层可以在掩模层107c与目标层150之间。本领域技术人员应当理解,在上述层的任意两个层之间可以沉积一层或多层,并且目标层150可以包括一个或多个附加层。
第一芯部层(因此第一芯部103)可以相对于堆层中的其他材料具有高蚀刻选择性,例如,硅和/或硅基氧化物或氮化物,例如,并且可以是透明的。第一芯部层可以是光致抗蚀剂或者可以是由非晶碳材料或非晶硅材料制成的。在一些实施例中,第一芯部层可以通过例如等离子体增强化学气相沉积沉积(PECVD)的沉积技术沉积在硬掩膜104的顶部上,并且沉积技术可以涉及在沉积室中从包括碳氢化合物前体的沉积气体产生等离子体。碳氢化合物前体可以用化学式CxHy来限定,其中x是在2至10之间的整数,并且y是在2至24之间的整数。实例包括甲烷(CH4)、乙炔(C2H2)、乙烯(C2H4)、丙烯(C3H6)、丁烷(C4H10)、环己烷(C6H12)、苯(C6H6)和甲苯(C7H8)。可以使用包括高频(HF)功率和低频(LF)功率的双射频(RF)等离子体源。可替代地,可以使用单个射频等离子体源。通常,这种等离子体源会是高频射频源。
在形成为第一芯部103的第一芯部层下是第二芯部层105。在第一芯部层与第二芯部层105之间可以是硬掩膜104。硬掩膜104可以具有相对于第一芯部层和第二芯部层105的高蚀刻敏感性从而在图案化第一芯部层的同时不蚀刻第二芯部层105。第二芯部层105可以是由非晶碳材料或非晶硅材料制成的。沉积方法和沉积前体可以是以上参照第一芯部层描述的任何方法和前体。一旦图案化,第二芯部层105形成为第二芯部(也称为第二心轴)105’(如图5所示)并且可以用于蚀刻后续层中的掩模,例如,掩模层107c,然后可以将其用于图案化目标层150。在某些实施例中,掩模层107c可以是由非晶碳材料或非晶硅材料制成的。在四重图案化方案中,例如图1至图11所示的方案,掩模层107c可以是光致抗蚀剂图案的四重图案使得光致抗蚀剂中的一个特征被图案化并且被转移以形成目标层150中的四个特征。
在第二芯部层105与目标层150之间可以是其他层,例如,硬掩膜层107a或覆盖层107b或掩模层107c以用于图案化目标层150。目标层150可以是最终将要图案化的层。目标层150可以是半导体、介电层或其他层并且例如可以是由硅(Si)、二氧化硅(SiO2)、氮化硅(SiN)或氮化钛(TiN)组成的。目标层150可以通过原子层沉积(ALD)、等离子体增强ALD(PEALD)、化学气相沉积(CVD)或其他合适的沉积技术进行沉积。
在一个实例中,例如图1所示的四图案化堆层的成分和厚度可以如下:非晶碳第一芯部103,原硅酸四乙酯(TEOS)硬掩膜层104,非晶碳第二芯部层105,TEOS硬掩膜层107a,非晶硅覆盖层107b,非晶碳掩模层107c,氮化钛阻挡层108a和TEOS硬掩膜层108b,全部都在硅目标层或衬底150上。在一个实例中,在光刻图案化以限定如图1的实例所示的第一芯部层之前可以按顺序在非晶碳第一芯部层的顶部沉积:SiON蚀刻停止层,底部防反射涂层(BARC)层和光致抗蚀剂第一芯部层。
在图2中,保形膜109沉积在第一芯部103上。保形膜109也可以成为“间隔物”并且可以沉积以使多层堆层上的图案的形状保形从而在图案上形成均匀分布的层。如以下进一步所述,保形膜109可以形成为多个单独的间隔物,每个单独的间隔物与第一芯部103的侧壁相邻。保形膜109具有相对于芯部高的蚀刻选择性。例如,保形膜109相对于非晶碳层可以具有大于3:1的蚀刻选择性。在一些实施例中,保形膜109相对于卤化蚀刻化学物质中的多晶硅具有大于15:1的蚀刻选择性。
保形膜109可以是由介电材料,例如SiO2制成的。保形膜109还可以是氧化物,例如,二氧化钛(TiO2)或者可以是氮化硅。在一些实施例中,保形膜109可以是由稠密材料制成的以承受图案化的更多“道次”,并且可以通过以下简述的ALD、PEALD或保形膜沉积(CFD)方法进行沉积。
ALD过程使用表面介导的沉积反应以逐层堆叠沉积薄膜。在ALD工艺的一个实例中,包括一组表面活性位点的衬底表面暴露于第一薄膜前体(P1)的气相分布。P1的一些分子可以在衬底表面的顶部形成包括P1的化学吸附物质和物理吸附分子的致密相。反应器然后被抽真空以去除气相和物理吸附的P1使得仅留下化学吸附的物质。然后第二薄膜前体(P2)被引入反应器中使得P2的一些分子吸附在衬底表面上。反应器可以再次被抽真空,这次去除未结合的P2。随后,被提供给衬底的热能激活P1与P2的吸附分子之间的表面反应,从而形成膜层。最后,反应物被抽真空以去除反应副产物以及可能未反应的P1和P2,从而结束ALD循环。可以包括附加的ALD循环以形成薄膜厚度。在PEALD过程的实例中,在第二薄膜前体P2被引入反应器时启动等离子体以激活P1与P2之间的反应。
CFD可以用于沉积保形膜109。一般来讲,CFD不依赖于在形成薄膜的反应之前完全净化一种或多种反应物。例如,当等离子体(或其他激活能量)撞击时,可以存在一种或多种蒸气相的反应物。因此,在示例的CFD处理中可以缩短或消除在ALD过程中描述的一个或多个处理步骤。另外,在一些实施例中,等离子体激活沉积反应会导致比热激活反应更低的沉积温度,从而有可能减小组合处理的热预算。作为背景,提供了CFD的简短描述。CFD循环的概念与本文的多种实施例的论述有关。就ALD过程而言,一般来讲,一个循环是进行一次表面沉积反应所需的最小的一组操作。一个循环的结果是在衬底表面上产生至少部分薄膜层。通常,CFD循环只包括输送并吸附每种反应物到衬底表面,然后使这些吸附的反应物发生反应以形成部分薄膜层所需的这些步骤。循环可以包括某些辅助步骤,例如,清扫一种或多种反应物或副产物,以及/或者处理沉积的部分薄膜。一般来讲,循环只包含独特操作序列的一个实例。作为示例,循环可以包括以下操作:(i)输送/吸附反应物A;(ii)输送/吸附反应物B;(iii)从反应室中清扫出反应物B;以及(iv)施加等离子体以驱动反应物A和B的表面反应,从而在表面上形成部分薄膜层。本文使用的术语PEALD包括CFD过程。
以下条件是适于通过CFD过程沉积氧化硅保形薄膜109的条件的实例。进行沉积的温度在约50℃至约400℃之间,压强在约0.5托至约10托之间,并且四个站的射频功率在约100W至10kW之间。对于各种实施例,射频激活频率可以在约13.56MHz至40MHz之间变化。对于氧化硅保形薄膜109,可以使用的工艺气体包括(作为硅源)硅酰胺(例如,BTBAS、BDEAS(双-二乙基氨基硅烷)或DIPAS(二异丙基氨基硅烷)以及单独地或共同地用惰性载气(例如氩气或氮气)稀释的(作为氧源)氧气或一氧化二氮或二氧化碳。工艺气体流速可以如下:对于(液态)硅前体(例如,BTBAS、BDEAS和DIPAS),在约1sccm与3sccm之间,例如,BTBAS的流速约为2.5sccm;对于氧气前体(O2、N2O),在约5000sccm与10000sccm之间,例如N2O的流速为5000sccm;并且对于载气(Ar或N2),在约0sccm与10000sccm之间,例如约5000sccm的氩气。
在图3中,保形膜109被回蚀或平面化以暴露第一芯部103。在各种实施例中,保形膜109可以通过多步骤过程进行平面化。在一个实例中,保形膜109可以通过以下方式进行回蚀:首先流入在约10sccm与约100sccm之间的氯气(Cl2),然后流入约10sccm至约100sccm的甲烷(CH4),接着流入约10sccm至约100sccm的氮气(N2)约30s。在一些实施例中,保形膜109进行蚀刻的温度可以在约10℃至约20℃之间,压力在约2毫托与约20毫托之间,时间约为30s。在一些实施例中,衬底进行蚀刻的温度可以在约40℃至约60℃之间,压力在约5毫托约约100毫托之间。在许多实施例中,进行各向异性等离子体蚀刻以暴露芯部并限定从保形膜109到间隔物109’的结构。
在图4中,第一芯部103被剥离或蚀刻,从而在衬底上留下自立式间隔物109’。如果第一芯部层是光致抗蚀剂,那么第一芯部103可以通过流入流速在约100sccm至约200sccm之间、温度在约40℃至约60℃之间并且压力在约5毫托至约20毫托之间的氧气(O2)进行蚀刻。
如果第一芯部层是由非晶碳材料制成的,那么第一芯部103可以使用灰化技术进行剥离或蚀刻。灰化方法可以取决于用于材料去除的化学反应,而不是高能离子的方向性运动。例如,暴露于在灰化操作中使用的工艺气体的任何表面可以由于暴露而经历材料去除,所以在第一芯部103中使用的非晶碳材料可以具有相对间隔物109’高的蚀刻选择性,使得间隔物109’在第一芯部103灰化时不被蚀刻。另外,与一些化学蚀刻过程相反,灰化操作可以产生完全处于气相的反应产物。用于碳膜的灰化操作可以例如利用离解的氢气(H2)或氧气(O2)作为工艺气体,其可以与碳膜发生反应以形成这种气相反应副产物。在一些实施例中,剩余的间隔物109’可以使用各种蚀刻条件形成供后续处理的形状。
在图5中,第二芯部层105使用间隔物109’作为掩模进行回蚀,从而转移图案以形成第二芯部105’。第二芯部层105可以通过使用适于蚀刻第二芯部层105而不蚀刻间隔物109’的化学物质进行蚀刻,温度在约50℃至约70℃之间,压强在约5毫托至约100毫托之间。第二芯部层105因此相对间隔物109’具有高的蚀刻选择性。第二芯部层105可以是非晶碳层,或非晶硅层。在第二芯部层105上方可以是覆盖层104,该覆盖层可以是硅防反射涂层或PECVD介电层或旋涂玻璃。
在图6中,间隔物109’和覆盖层104被蚀刻或者说是被去除,从而留下图案化的第二芯部105’。在一些实施例中,间隔物109’可以在约10℃至约20℃之间的温度、在约2毫托至约20毫托之间的压强经过约30s的时间被去除。在一些实施例中,衬底进行蚀刻的温度可以在约40℃至约60℃之间,压强在约5毫托至约100毫托之间。在许多实施例中,进行各向异性等离子体蚀刻。在一个实例中,间隔物109’通过以下方式进行蚀刻:首先流入在约10sccm与约100sccm之间的氯气(Cl2),然后流入约10sccm至约100sccm的甲烷(CH4),接着流入约10sccm至约100sccm的氮气(N2)约30s。
在图7中,第二保形膜119沉积在图案化的第二芯部105’上方。在许多实施例中,第二保形膜119可以是氧化钛层,其可以通过PEALD方法进行沉积。
在图8中,第二保形膜119被蚀刻或图案化以暴露第二芯部105’。条件和方法可以是以上参照图3讨论的任何条件和方法。
在图9中,第二芯部105’被蚀刻或去除,从而留下自立式第二间隔物119’。条件和方法可以是以上参照图4讨论的任何条件和方法。
在图10中,掩模层107c通过使用第二间隔物119’作为掩模而被回蚀,从而将第二间隔物119’的图案转移以形成图案化掩模107c’。掩模层107c对第二保形膜119可以具有高蚀刻选择性,并且可以根据掩模层107c的化学成分通过上述参照图5讨论的任何方法进行蚀刻。
在图11中,第二间隔物层119’连同蚀刻停止层107a和覆盖层107b被去除,从而留下图案化掩模107’。用于去除第二间隔物119’的条件和方法可以是上述参照图6讨论的任何条件和方法。掩模107’然后可以用于图案化后续的层,例如,目标层150。图1至图11所述的处理步骤的结果是四图案化方案,使得单个光刻限定的特征(例如,图1中的第一芯部103)导致衬底上的四个更小的特征。四图案化方案可以用于形成具有小至10nm的半节距或者在10nm至20nm之间的半节距的特征,其无法通过当前的双图案化方案来实现。
由于形成更小特征的性质,用作第二保形膜119的材料的质量可以高于在更宽芯部的间隔物中使用的保形膜的质量,以便维持健壮性并且在其暴露于后续图案化步骤中的恶劣条件下时防止弯曲。高质量的保形膜材料可以具有接近理想的化学计量性,例如,当保形膜是氧化钛时,高质量的氧化钛保形膜可以具有接近理想的Ti:O化学计量性,例如1:2,以及低碳含量。高质量保形膜可以通过ALD沉积,其可以从氧化半反应完成完全转化,从而形成接近理想的化学计量性。因此,高质量的保形膜材料就可以具有低蚀刻率和高蚀刻选择性以及对氧化物和氮化物还具有极大地选择性。这些薄膜也可以具有更高的模量,例如,大于约150MPa,这有助于提高作为间隔物的保形膜的机械稳定性,从而提高临界尺寸均匀性(CDU)。本文公开的高质量的保形膜材料也可以是稠密的以承受后续的集成步骤。
本文提供了沉积薄的保形纳米层压保护层的方法。还提供了形成可用作间隔物的高质量薄膜的方法,该方法包括沉积纳米层压层。纳米层压层可以在沉积保形膜期间防止底层芯部层恶化的情况下提高间隔物的健壮性。
直接在芯部层上沉积高质量薄膜,例如,高质量氧化钛,会由于在沉积间隔物期间的恶劣条件而导致芯部恶化或消耗,从而损坏底层的图案化芯部。例如,在沉积高质量保形膜期间,图案化芯部可以暴露于氧自由基,例如,使用至少约1000W的高HFRF功率从N2O/O2顺序等离子体产生的氧自由基。由于更高的功率,形成更多的氧自由基,这增大了芯部层上的自由基轰击以及芯部图案化的后续恶化。氮化物如果在芯部层上用作覆盖物则能够承受这种轰击,但是由于氮化物对某些芯部材料不具有选择性,所以氮化物不合适。在沉积保形膜之后,衬底就可以被平面化以暴露芯部并去除芯部,但是由于芯部已经被消耗或已经恶化,所得的间隔物之间的宽度会减小,这导致半导体衬底中不规则的图案。与使用低质量保形膜以防止芯部恶化相反,本文公开的方法使用高质量间隔物材料。
由于在沉积期间使用更低的高频射频功率,纳米层压保护层可以比保形膜更不致密。这样,纳米层压保护层可以沉积成适合保护芯部的最小厚度。最小化纳米层压保护层可以便于后续集成。纳米层压保护层可以保护底层使得高质量保形膜可以沉积在其上。芯部消耗和恶化由此减少并且芯部可以在沉积高质量保形膜期间承受更恶劣的条件。在后续图案化步骤中,高质量保形膜可以承受其他恶劣条件并且作为自立式结构仍然维持其强健壮性。纳米层压保护层通过维持芯部几何结构的完整性并且给自立式间隔物结构提供机械支撑也可以防止间隔物倾斜并且允许临界尺寸波动,从而增强在半导体处理中形成更小半节距的更精密特征的能力。
使用纳米层压保护层的方法的实例可以始于提供具有光刻限定或图案化的第一芯部层的多堆层半导体衬底,例如上述参照图1所述的半导体衬底。在一些实施例中,纳米层压保护层可以在沉积保形膜109之前沉积在第一芯部103上,如以下结合图13的实施例所述。在各种实施例中,保形膜109可以沉积在第一芯部103上,例如如图2所示。在保形膜109被平面化之后,例如如图3所示,第一芯部103可以被蚀刻或去除以露出剩余的间隔物109’,例如如图4所示。第二芯部层105可以通过使用间隔物109’作为掩模而被蚀刻,从而转移图案以形成第二芯部105’,例如如图5所示。间隔物109’可以被去除以露出图案化的第二芯部105,例如如图12所示。第二芯部层105可以是非晶碳层或非晶硅层。
在图13中,纳米层压保护层111可以保形地沉积在第二芯部105’上。纳米层压层111的厚度的实例在约至约之间,在约至约之间,或者在约至约之间。要注意,图13所示的厚度被夸大了,目的是为了说明并仅作为实例。
在一些实施例中,纳米层压层111可以包括堆层,该堆层可以具有两个或更多个副层(未示出)。例如,堆层可以是双层。在一些实施例中,副层具有相同的成分,并且在一些实施例中,副层具有不同的成分。在一些实施例中,纳米层压层111是一层。在一个实例中,纳米层压层111是一层氧化硅。在另一个实例中,纳米层压层111是一层氧化钛。在双层纳米层压层111的一个实例中,上层是氧化硅,并且下层是氧化钛。在双层纳米层压层111的另一个实例中,上层是氧化钛,并且下层是氧化硅。
由于可用于沉积纳米层压层111的低HFRF功率,所以纳米层压层111也可以比保形膜中沉积的材料不致密。在一些实施例中,纳米层压层111可以是ALD氧化物,例如,二氧化硅(SiO2)或二氧化钛(TiO2)并且被称为“软”ALD氧化物。当配置用于图案化方案的处理条件并确定有待蚀刻的图案时可以考虑纳米层压层111的厚度。在各种实施例中,纳米层压层111通过保形膜沉积(CFD)或PEALD进行沉积。
在图14中,第二保形膜129沉积在纳米层压层111上方。在某些实施例中,第二保形膜129是高质量氧化钛薄膜,例如,具有低的湿蚀刻率和对例如二氧化硅(SiO2)的氧化物和例如氮化硅(SiN)的氮化物具有极大选择性的高的干蚀刻选择性的氧化钛层。例如,第二保形膜129相对于非晶碳层可以具有大于3:1的蚀刻选择性。在一些实施例中,第二保形膜129相对于卤化蚀刻化学物质中的多晶硅具有大于15:1的蚀刻选择性。在一个实例中,沉积至厚度约为的纳米层压层111能够足以使第二芯部105’免于沉积约的第二保形膜129。在各种实施例中,第二保形膜129通过CFD或PEALD进行沉积。在一些实施例中,第二保形膜129比纳米层压层111更致密。
在图15中,衬底被平面化以暴露具有纳米层压层111侧壁的第二芯部105’并得到侧壁第二间隔物129’。用于平面化的条件可以是上述参照图3所述的任何条件。
在图16中,第二芯部105’被蚀刻并被去除。条件和方法可以是上述参照图9所讨论的任何条件和方法。在一些实施例中,一小部分纳米层压层111由于蚀刻步骤的性质可以被蚀刻。在一些实施例中,纳米层压层111被充分地选择性蚀刻并且在第二芯部105’被去除的同时不被蚀刻。要注意,第二间隔物129’坐靠在纳米层压层111的薄层上,在第二间隔物129’的侧壁上具有薄纳米层压层111,这由此可以增强第二间隔物129’的稳定性并防止倾斜。再者,在一些实施例中,纳米层压材料可以与第二芯部105’一起被完全去除。如以上指出的,在一些实施例中,纳米层压层111的厚度以及去除多少纳米层压层可以在计划图案化方案以达到所需尺寸时进行考虑。然而,在一些实施例中,纳米层压层111的厚度可以在图案化尺寸的公差内,并且可以不需要考虑到。
在图17中,掩模层107c通过使用第二间隔物129’作为掩模而被回蚀。由于高质量的第二间隔物129’增加的稳定性和健壮性,所以可以更容易且更充分地完成这种操作以形成具有高纵横比的精细、稳定的特征。
在图18中,纳米层压层111和第二间隔物129’被蚀刻或被去除以露出所得的图案化掩模107c’。条件和方法可以是上述参照图5所述的任何条件和方法。图案化掩模107c’随后可以用于图案化后续的层,其可用于图案化目标层150。在一些实施例中,图案化的掩模107c’可以用于图案化目标层150。
图19是根据各种实施例的方法的步骤的工艺流程图。本文所述的循环和暴露时间可以取决于所使用的设备和平台并且本领域技术人员可以相应地调节循环和暴露时间。在操作1901中,衬底可以暴露于第一前体,例如,含钛前体或含硅前体。在一些实施例中,衬底包括芯部层。在各种实施例中,芯部层是非晶碳、非晶硅或光致抗蚀剂。在一些实施例中,芯部层是通过光刻限定或图案化的。在某些实施例中,衬底包括图案化的非晶碳层。
含钛前体的实例包括三二甲基氨基钛(TDMAT)、四乙氧基钛、四二甲基氨基钛、异丙醇钛、四异丙氧基钛和四氯化钛。含硅前体可以是例如硅烷、卤代硅烷或氨基硅烷。硅烷包含氢基和/或碳基团,但是不包含卤素。硅烷的示例是甲硅烷(SiH4)、乙硅烷(Si2H6)和有机硅烷,例如甲基硅烷,乙基硅烷,异丙基硅烷,叔丁基硅烷,二甲基硅烷,二乙基硅烷,二-叔-丁基三甲氧基硅烷,烯丙基硅烷,仲丁基三甲氧基硅烷,叔己基硅烷,异戊硅烷,叔丁基二硅烷,二-叔丁基乙硅烷,正硅酸乙酯(也称为四乙氧基硅烷或TEOS)等。卤素硅烷包含至少一个卤素基,并且可以包含或不包含氢和/或碳基团。卤素硅烷的示例是碘硅烷、溴硅烷、氯硅烷和氟硅烷。在本文描述的某些实施例中,尽管卤素硅烷,特别是氟硅烷,可以形成能够蚀刻硅材料的反应性卤化物,但是当等离子体撞击时,不存在含硅反应物。具体的氯硅烷是四氯硅烷(SiCl4),三氯硅烷(HSiCl3),二氯硅烷(H2SiCl2),单氯硅烷(ClSiH3),氯代硅烷,三甲基氯硅烷,二氯甲基硅烷,氯二甲基硅烷,氯硅烷,叔丁基氯硅烷,二-叔丁基氯硅烷,氯丙基三甲氧基硅烷,氯仲-丁基硅烷,叔-二甲基氯硅烷,叔己基二甲基氯硅烷等。氨基硅烷包含至少一个结合在硅原子上的氮原子,但是还可以包含氢、氧、卤素和碳。氨基硅烷的示例是单、双、三和四氨基硅烷(分别为H3Si(NH2)4、H2Si(NH2)2、HSi(NH2)3和Si(NH2)4),以及取代的单、双、三和四氨基硅烷,例如,叔丁基氨基硅烷,甲基氨基硅烷,叔丁基硅烷胺,二(叔丁基氨基)硅烷(SiH2(NHC(CH3)3)2(BTBAS),叔丁基甲硅烷基氨基甲酸叔丁酯,SiH(CH3)-(N(CH3)2)2,SiHCl-(N(CH3)2)2,(Si(CH3)2NH)3等。氨基硅烷的进一步示例是三甲基烷胺(N(SiH3)3)。
在操作1901之后,沉积室可以在使用喷射器净化或泵送步骤的清扫阶段中被净化。一般来讲,清扫阶段从反应室去除或净化蒸气相反应物之一并且通常仅在完成这种反应物的输送之后进行。换句话讲,反应物在清扫阶段不再输送到反应室。然而,反应物在清扫阶段一直被吸附在衬底表面上。通常,清扫起到在反应物被以所需水平吸附到衬底表面上之后去除反应室中任何残留的气相反应物的作用。清扫阶段也可以从衬底表面去除较弱吸附的物质(例如,某些前体配体或反应副产物)。在ALD中,清扫阶段被视为是必要的以防止两种反应物的气相相互作用或者一种反应物与热、等离子体或用于表面反应的其他驱动力相互作用。一般而言,并且除非本文中另外指出,清扫/净化阶段可以按照以下方式完成:(i)对反应室进行抽真空;以及/或者(ii)使不包含待清除的物质的气体流过反应室。就(ii)而言,这种气体可以是例如惰性气体。
在操作1903中,衬底可以暴露于第二前体或氧化剂。在一些实施例中,氧化剂是一氧化二氮(N2O)或氧气(O2)或二氧化碳(CO2)或它们的混合物或组合。在一些实施例中,氧化剂可以是氧气(O2)和弱氧化剂(例如N2O、CO、CO2、NO、NO2、SO、SO2、CxHyOz和/或H2O)的混合物。在其他实施方式中,氧化反应物可以完全是弱氧化剂。可替代地,氧化反应物可以包括臭氧。在一些实施例中,氧化反应物是约0至50%的O2和约50%至100%的弱氧化剂。
在一些情况下,可以连续(例如,甚至在输送其他反应物期间和/或等离子体暴露期间)输送反应物之一。例如,可以连续输送氧化反应物。连续流动的反应物可以结合例如氩气的载气被输送到反应室。在一些情况下,通过使用分流阀/入口阀切换器来控制输送连续流动的反应物到反应室。气流变化可以转移或共流。在一个实例中,连续流动的反应物从反应室周期性地转移使得反应物仅在某些时期被输送到反应室。连续流动的气体可以通过使用合适的阀门被转移到出口/排泄口。例如,氧化反应物可以连续流动,但仅仅周期性地被输送到反应室。当氧化反应物未被输送到反应室时,氧化反应物可以被转移到出口、循环系统等。
在操作1905中,可以在衬底暴露于氧化剂的同时使用低HFRF功率启动等离子体。在一些实施例中,单位面积的晶圆的低HFRF功率可以在约1.768×10-4W/mm2至约1.768×10-3W/mm2之间,其中mm2代表晶圆表面积的单位。等离子体功率可以与晶圆表面积成线性地缩放。例如,对于300mm的晶圆,每个站的低HFRF功率可以在约12.5W至约125W之间,对于450mm的晶圆,每个站的低HFRF功率可以在约28W至约280W之间。沉积温度可以在约50℃至约150℃之间。在操作1905之后,沉积室可以再次进行净化。这些步骤可以重复进行直到沉积所需厚度的薄膜。
在一些实施例中,操作1905可以在低温进行,例如,在四站工具中,在小于约100℃的温度,在300nm衬底暴露于氧化剂时HFRF功率在约50W至约500W之间,功率为施加在四站工具上的总功率。
在操作1907中,衬底可以暴露于含钛前体。含钛前体的实例可以是上述参照操作1901描述的任何含钛前体。举例来说,衬底可以暴露于TDMAT约2s,这可以描述为一个“剂量”。在操作1907之后,沉积室可以使用喷射器净化或泵送步骤进行净化。举例来说,净化可以持续约10s。
在操作1909中,衬底可以暴露于另一种前体或氧化剂。在许多实施例中,氧化剂是一氧化二氮(N2O)或氧气(O2)或二氧化碳(CO2)或它们的混合物。举例来说,操作1909可以是约30s,使得对于前25s,无氧化剂流入并仅流入载气或惰性气体,并且在25s之后氧化剂开始流入并保持流动到下一个操作。载气的实例包括氩气(Ar)和氮气(N2)。这些载气的流速可以在约0sccm至约10000sccm之间。
在操作1911中,可以在衬底暴露于氧化剂的同时使用高HFRF功率启动等离子体。在许多实施例中,对于300mm的晶圆,每个站的HFRF功率可以在约125W至约1500W之间。举例来说,每站的HFRF功率可以是约625W。可以在约0.25s至约3s之间或约0.5s的时间启动等离子体。操作1907至1911可以在50℃至约400℃之间、或在约50℃至200℃之间或者约150℃的温度并且在约3托至约3.5托之间的压强进行。在操作1911之后,可以关闭等离子体并且净化反应室或者将其抽真空。在操作1901、1903、1905、1907、1909和1911之后使用的净化气体的实例可以是氩气(Ar)或氮气(N2)或者任何其他合适的净化气体。在一些实施例中,操作1901至1905中沉积的薄膜的密度可以比操作1907至1911中沉积的薄膜的密度更小。
根据各种实施例,操作1901至1905可以在比操作1907至1911更低的温度和/或更低的射频功率和/或更短的射频时间和/或更低的压强和/或使用更弱的氧化剂进行。这些沉积条件可以有助于在生产可操作器件时防止损坏底层的衬底。
图20A提供了根据各种实施例的使用纳米层压层的方法的工艺流程图。在操作2001中,可以沉积芯部层,例如参照图1所述的方式。芯部层可以是非晶碳层或非晶硅层,或者可以是光致抗蚀剂。在一些实施例中,芯部层被图案化。在操作2003中,纳米层压层沉积在芯部层上。纳米层压层可以通过CFD或PEALD方法进行沉积。通过使用上述结合图19描述的操作1901至1905可以沉积纳米层压层。在一些实施例中,纳米层压层可以是二氧化硅(SiO2)或二氧化钛(TiO2)。沉积的纳米层压层的厚度可以在约至约之间,或者在约至约之间。在操作2005中,金属氮化物或金属氧化物可以沉积在纳米层压层上。通过使用上述结合图19描述的操作1907至操作1911可以沉积金属氮化物或金属氧化物。在一些实施例中,金属氮化物或金属氧化物层是氧化硅或氧化钛层。在一些实施例中,金属氮化物或金属氧化物层是高质量氧化钛层。在各种实施例中,金属氮化物或金属氧化物层相对芯部具有高蚀刻选择性。在许多实施例中,金属氮化物或金属氧化物层比纳米层压层更致密。
图20B是根据各种实施例的使用纳米层压层的方法的实例的工艺流程图。在操作2011中,薄纳米层压层沉积在衬底上。纳米层压层可以是上述参照图13至图20A讨论的任何纳米层压层。通过使用上述结合图19描述的操作1901至1905可以沉积纳米层压层。在操作2013中,氧化钛层可以沉积在纳米层压层上。以上参照图14描述了沉积在纳米层压层上的氧化钛层的实例。通过使用上述结合图19描述的操作1907至操作1911可以沉积氧化钛层。
设备
本文提供的沉积技术可以在等离子体增强化学气相沉积(PECVD)反应器或保形膜沉积(CFD)反应器中实施。这种反应器可以采用多种形式,并且可以是包括一个或多个室或“反应器”(有时候包括多个站)的设备的一部分,这些室或“反应器”均可以容纳一个或多个晶圆并且可以被配置成执行各种晶圆处理操作。一个或多个室可以维持晶圆在一个或多个限定位置(在该位置运动或不发生运动,例如,旋转、振动或者说是搅动)。在一个实施方式中,经过薄膜沉积的晶圆可以在处理期间从一个站转移到反应室内的另一个站。在其他实施方式中,晶圆可以在设备内的室之间转移以执行不同的操作,例如,蚀刻操作或光刻操作。全部薄膜沉积可以完全在单站或者对于任何沉积步骤沉积总薄膜厚度的任何部分。尽管在处理期间,每个晶圆可以通过基座、晶圆卡盘和/或其他晶圆固定设备保持在位。对于将要加热晶圆的某些操作,设备可以包括例如加热板的加热器。由Lam Research Corp.(Fremont,CA)生产的VectorTM(例如,C3 Vector)或SequelTM(例如,C2 Sequel)反应器两者是可用于实施本文所述的技术的合适的反应器的实例。
图21提供了用于实施本文所述的方法所设置的各种反应器元件的简化方框图。如图所示,反应器2100包括加工室2124,该加工室封闭反应器的其他元件并且用于容纳由电容放电式系统产生的等离子体,该系统包括与接地的加热部件2120结合工作的喷头2114。高频(HF)射频(RF)发生器2104和低频(LF)RF发生器2102可以连接至匹配网络2106和喷头2114。匹配网络2106供应的功率和频率可以足以从供应至加工室2124的工艺气体产生等离子体。例如,匹配网络2106可以提供50W至500W的HFRF功率。在一些实例中,匹配网络2106可以提供100W至5000W的HFRF功率以及100W至5000W的LFRF功率总能量。在典型过程中,HFRF成分通常可以在5MHz至60MHz之间,例如,13.56MHz。在存在低频成分的操作中,低频成分可以在100kHz至2MHz之间变化,例如,430kHz。
在反应器内,晶圆基座2118可以支撑衬底2116。晶圆基座2118可以包括卡盘、叉子或升降销(未示出)以在沉积和/或等离子体处理反应期间或间隙固定并转移衬底。卡盘可以是静电卡盘、机械卡盘或各种其他类型的卡盘,只要在行业和/或研究中可用。
各种工艺气体可以经由入口2112引入。多源气线2110连接至歧管2108。气体可以经过预混合或未经预混合。可以采用合适的阀门和质量流控制机构来确保在过程的沉积和等离子体处理阶段期间输送正确的工艺气体。在化学前体以液体形式输送的情况中,可以采用液体流控制机构。然后这种液体可以在达到沉积室之前在歧管中输送期间被加热到以液体形式供应的化学前体的蒸发点之上而气化并与工艺气体混合。
工艺气体经由出口2122流出室2124。真空泵(例如,一级或两级机械式干泵和/或涡轮分子泵2140)通过使用闭环控制的流量限制装置(例如,节流阀或摆阀)可以用于从加工室2124抽出工艺气体并且在加工室2124内维持合适的低压。
如上所述,本文讨论的用于沉积的技术可以在多站或单站工具上实施。在具体实施方式中,可以使用具有4站沉积方案的300mm Lam VectorTM工具,或者具有6站沉积方案的200mm SequelTM工具。在一些实施方式中,可以使用用于处理450mm晶圆的工具。在各种实施方式中,晶圆可以在每次沉积和/或后沉积等离子体处理之后进行索引,或者如果蚀刻室或站也是相同工具的一部分,可以在蚀刻步骤之后进行索引,或者在索引晶圆之前可以在单站进行多次沉积和处理。
在一些实施例中,可以提供被配置成执行本文所述的技术的设备。合适的设备可以包括用于执行各种处理操作的硬件以及具有用于控制根据公开的实施例的处理操作的指令的系统控制器2130。系统控制器2130通常会包括一个或多个存储设备以及与各种处理控制设备(例如,阀门、射频发生器、晶圆传送系统等)通信连接的一个或多个处理器,并且所述处理器被配置成执行指令使得设备会执行根据公开的实施例的技术,例如,在图19的沉积步骤中提供的技术。包括用于控制根据本发明的处理操作的指令的机械可读介质可以连接至系统控制器2130。控制器2130可以与各种硬件设备(例如,质量流控制器、阀门、射频发生器、真空泵等以及连接上以便于控制与本文所述沉积操作相关联的各种处理参数。
在一些实施例中,系统控制器2130可以控制反应器2100的所有活动。系统控制器2130可以执行存储在大容量存储器中、装载到存储设备中并且在处理器上运行的系统控制软件。系统控制软件可以包括用于控制气流计时、晶圆运动、射频发生器激活等指令,以及用于控制气体的混合、室压和/或站压、室温和/或站温度、晶圆温度、目标功率水平、射频功率水平、衬底基座、卡盘和/或衬托器位置和反应器设备2100所执行的特定处理的其他参数的指令。系统控制软件可以被配置成任何合适的方式。例如,可以写入多个加工工具组件的子程序或控制对象以控制加工工具组件实现多个加工工具过程所需的操作。系统控制软件可以编码成任何合适的计算机可读的编程语言。
系统控制器2130通常可以包括一个或多个存储设备以及一个或多个处理器,这些处理器被配置为执行指令使得设备会实施根据本发明的技术。包括用于控制根据公开的实施例的处理操作的指令的机器可读的介质可以连接至系统控制器2130。
本文所述的方法和设备可以结合光刻图案化工具和方法使用,例如以下描述的用于制备或制造半导体器件、显示器、LED、光伏面板等的设备和处理。通常,尽管不一定,但是这些工具/方法可以在共同的制造设施中一起使用或操作。光刻图案化薄膜通常包括一些或全部以下步骤,每个步骤允许使用多种可用的工具:(1)使用旋涂或喷涂工具将光致抗蚀剂涂覆在工件上,即,在公开的实施例中提供的衬底或多层堆层;(2)使用热板或炉或紫外线固化工具固化光致抗蚀剂;(3)使用例如晶圆分档器的工具将光致抗蚀剂暴露于可见光或紫外线或X射线;(4)使用例如湿式清洗台的工具使光致抗蚀剂显影以便选择性地去除抗蚀剂从而使其图案化;(5)通过使用例如以下描述的干式或等离子体辅助刻蚀工具将蚀刻剂图案转移到下方的薄膜或工件,例如非晶碳层;并且(6)使用例如射频或微波等离子体抗蚀剂剥离器的工具去除抗蚀剂。在一个实施方式中,晶圆上的一个或多个间隙特征通过使用本文所述的技术填满碳薄膜。碳薄膜则可用于例如本文所述的目的之一。另外,实施方式可以包括一个或多个上述步骤(1)至(6)。
在多站加工工具中可以包括一个或多个处理站。图22示出了多站加工工具2200的实施例的示意图,该多站加工工具具有入站装载锁2202和出站装载锁2204,任意一个或两个装载锁可以包括远程等离子体源。在大气压下,机器人2206被配置成经由大气端口2210将穿过纵槽2208装载到晶圆匣的晶圆移动到入站装载锁2202中。机器人2206将晶圆放置在入站装载锁2202中的基座2212上,并且大气端口2210关闭,并且装载锁被泵吸关闭。在入站装载锁2202包括远程等离子体源的情况中,晶圆可以在引入到加工室2214之前在装载锁中暴露以进行远程等离子体处理。另外,晶圆同样可以在入站装载锁2202中受热,例如,用于去除水分和吸附气体。接着,到加工室2214的室输送端口2216打开,并且另一个机器人(未示出)将晶圆放入反应器中,在用于加工的反应器中所示的第一站的基座上。尽管图示的实施例包括装载锁,但是应当理解,在一些实施例中,可以提供晶圆进入处理站的直接入口。
图示的加工室2214包括四个处理站,在图22所示的实施例中从1编号到4。每个站具有受热的基座(站1的基座图示为2218)和气体管道入口。应当理解,在一些实施例中,每个处理站可以具有不同的或多个用途。例如,在一些实施例中,处理站可以在CFD与PECVD处理模式之间切换。另外或可替代地,在一些实施例中,加工室2214可以包括一个或多个配对的CFD和PECVD处理站。尽管图示的加工室2214包括四个站,应当理解,根据本发明的加工室可以具有任意合适数量的站。例如,在一些实施例中,加工室可以具有四个或更多个站,尽管在其他实施例中,加工室可以具有三个或更少的站。
图22还示出了用于在加工室2214内转移晶圆的晶圆搬运系统2290的实施例。在一些实施例中,晶圆搬运系统2290可以在多个处理站之间以及/或者在处理站与装载锁之间转移晶圆。应当理解,可以采用任何合适的晶圆搬运系统。非限制性实例包括晶圆旋转货架和晶圆搬运机器人。图22还示出了用于控制处理条件和加工工具2200的硬件状态的系统控制器2250的实施例。系统控制器2250可以包括一个或多个存储设备2256,一个或多个大容量存储设备2254和一个或多个处理器2252。处理器2252可以包括CPU或计算机,模拟和/或数字输入/输出连接,步进电机控制板等。
在一些实施例中,系统控制器2250控制加工工具2200的所有活动。系统控制器2250执行存储在大容量存储器2254中、装载到存储设备2256中并且在处理器2252上运行的系统控制软件2258。可替代地,控制逻辑可以硬编码在控制器2250中。专用集成电路、可编程逻辑器件(例如,现场可编程逻辑器件或FPGA)等可以用于这些目的。在以下讨论中,无论何处使用“软件”或“代码”,都可以使用功能上相当的硬编码逻辑来代替。系统控制软件2258可以包括用于控制计时、气体混合、室压和/或站压力、室温和/或站温度、晶圆温度、目标功率水平、射频功率水平、射频暴露时间、衬底基座、卡盘和/或衬托器位置以及加工工具2200执行特定处理的其他参数的指令。系统控制软件2258可以被配置成任何合适的方式。例如,可以写入多个加工工具组件的子程序或控制对象以控制加工工具组件实现多个加工工具过程所需的操作。系统控制软件2258可以编码成任何合适的计算机可读的编程语言。
在一些实施例中,系统控制系统2258可以包括用于控制如上所述的多个参数的输入/输出控制(IOC)序列指令。例如,CFD处理的每个阶段可以包括由系统控制器2250执行的一个或多个指令。对应的CFD的配方阶段中可以包括用于设定CFD处理阶段的处理条件的指令。在一些实施例中,可以顺序布置CFD的配方阶段,使得与该处理阶段同时执行用于CFD处理阶段的所有指令。
在一些实施例中可以采用存储在与系统控制器2250相关联的大容量存储设备2254和/或存储设备2256上的其他计算机软件和/或程序。用于该目的的程序或程序段的实例包括衬底定位程序、处理气体控制程序、压力控制程序、加热器控制程序和等离子体控制程序。
衬底定位程序可以包括用于加工工具组件的程序代码,该加工工具组件用于将衬底装载到基座2218上并且控制衬底与加工工具2200的其他零件之间的间距。
处理气体控制程序可以包括用于控制气体成分和流速的代码以及任选地用于在沉积之前使气体流入一个或多个处理站以便使处理站内的压力稳定的代码。在一些实施例中,控制器包括用于在芯部层上沉积纳米层压保护层并且在保护层上方沉积保形层的指令。
压力控制程序可以包括用于通过调节(例如,加工站的排气系统中的节流阀)流入加工站中的气流等来控制加工站中的压力的代码。在一些实施例中,控制器包括用于在芯部层上沉积纳米层压保护层并且在保护层上方沉积保形层的指令。
加热控制系统可以包括用于控制流到加热单元的电流的代码,该加热单元用于加热衬底。可替代地,加热控制程序可以控制输送传热气体(例如,氦气)到衬底。在某些具体实施中,控制器包括用于在第一温度沉积纳米层压保护层并且在第二温度在保护层上方沉积保形层的指令,其中第二温度高于第一温度。
等离子体控制程序可以包括用于根据本文的实施例在一个或多个处理站中设置射频功率水平和暴露时间的代码。在一些实施例中,控制器包括用于在第一射频功率水平和射频持续时间沉积纳米层压保护层并且在第二射频功率水平和射频持续时间在保护层上方沉积保形层的指令。第二射频功率水平和/或第二射频持续时间可以比第一射频功率水平/持续时间更高/更长。
在一些实施例中,可以存在与系统控制器2250相关联的用户界面。用户界面可以包括显示屏、设备和/或加工条件的图像软件显示器以及其他输入设备,例如,指向设备、键盘、触屏、麦克风等。
在一些实施例中,由系统控制器2250调节的参数可以涉及处理条件。非限制性实例包括工艺气体成分和流速、温度、压力、等离子体条件(例如,射频偏压功率水平和暴露时间)、压力、温度等。这些参数可以以配方的形式提供给用户,可以利用用户接口来输入配方。
用于监测过程的信号可以由系统控制器2250的模拟和/或数字输入连接从多个加工工具传感器提供。加工工具2200的模拟和数字输出连接可以输出用于控制处理的信号。可以监测的加工工具传感器的非限制性实例包括质量流控制器、压力传感器(例如压力计)、热电偶等。可以与来自这些传感器的数据一起使用适当编程的反馈和控制算法来维持处理条件。
系统控制器2250可以提供用于实施上述沉积处理的程序指令。程序指令可以控制各种处理参数,例如直流功率水平、射频偏压功率水平、压力、温度等。这些指令可以控制这些参数以根据本文所述的多个实施例原位沉积薄膜堆层。
系统控制器通常包括一个或多个存储装置和一个或多个处理器,所述处理器被配置成执行指令使得设备会执行根据公开的实施例的方法。包括用于控制根据公开的实施例的处理操作的指令的机器可读的、非暂时性介质可以连接至系统控制器。
实验
实验1
进行实验以比较在未保护的芯部上沉积的间隔物或保形膜以及沉积在受到纳米层压保护层的保护的芯部上的间隔物或保形膜。在第一次尝试中,提供具有未图案化的芯部层的衬底,该未图案化的芯部层是由非晶碳制成的。高质量氧化钛通过等离子体增强原子层沉积(PEALD)或保形膜沉积(CFD)方法直接沉积在芯部层上。室压约为3托并且温度约为150℃。衬底暴露于第一前体TDMAT持续2s,随后进行10s净化。然后衬底暴露于氧化剂N2O/O2的混合物持续30s,其中前25秒涉及仅流入载气N2(以高达9500sccm的流速),并且在最后5秒,N2O/O2流开启并维持直到等离子体启动0.5s。每个站以625W或者四个站以2500W的高频射频(HFRF)功率启动等离子体。在0.5s等离子体暴露时间之后,同时关闭N2O/O2流和等离子体,并且最后处理室被抽真空以净化处理器。图23A示出了沉积的保形膜和底层芯部层的图像。恶化的芯部层2304a被图示为在二氧化钛(TiO2)保形膜层2302a下方。
在第二次尝试中,也提供具有未图案化的芯部层的衬底,该未图案化的芯部层是由非晶碳制成的。二氧化硅(SiO2)纳米层压保护层通过PEALD沉积在芯部层上。沉积室温度为50℃并且室压为1.8托。衬底暴露于含硅前体0.2s,随后进行0.2s净化。然后衬底暴露于氧化剂N2O/O2的混合物持续0.3s。在四站1000W或者每个站约500W启动四站室的等离子体。关闭N2O/O2流和等离子体,并且净化处理器。随后,衬底暴露于TDMAT持续2s,随后进行10s净化。在净化之后,衬底暴露于氧化剂N2O/O2持续30s,使得混合物仅在最后5s流入,并且在30s之后,继续流入0.5s,同时以每站625W或者四站2500W启动等离子体以持续0.5s。在关闭等离子体和氧化剂N2O/O2流两者之后,处理室被再次净化。图23B示出了沉积的保形膜、纳米层压层和底层芯部层的图像。如图所示,沉积的保形膜2302b沉积在纳米层压层2306顶部上,该保形膜足够薄至难以辨别保形膜以及保形膜所邻接的芯部层。要注意,与图23A相比,芯部心轴2304b具有非常小的恶化或消耗。
在第三次尝试中,也提供具有未图案化的芯部层的衬底,该未图案化的芯部层是由非晶碳制成的。二氧化钛(TiO2)纳米层压保护层通过PEALD沉积在芯部层上。沉积室温度为150℃并且室压为3.0托。衬底暴露于TDMAT持续2s,随后进行10s净化。然后衬底暴露于氧化剂N2O/O2的混合物持续30s,使得混合物仅在最后5s流入,并且在30s之后,继续流入0.5s,同时以每站约500W或者四站室1000W启动等离子体。关闭N2O/O2流和等离子体,并且净化处理器。随后,衬底暴露于TDMAT持续2s,随后进行10s净化。在净化之后,衬底暴露于氧化剂N2O/O2持续30s,使得混合物仅在最后5s流入,并且在30s之后,继续流入0.5s,同时以每站625W或者四站2500W启动等离子体以持续0.5s。在关闭等离子体和氧化剂N2O/O2流两者之后,处理室被再次净化。图23C示出了沉积的保形膜、纳米层压层和底层芯部层的图像。如图所示,沉积的保形膜2302c沉积在纳米层压层2308顶部上,该保形膜足够薄至难以辨别保形膜以及保形膜所邻接的芯部层。要注意,芯部心轴2304c具有非常小的恶化或消耗。
实验2
使用参照上述三次试验描述的条件的相同条件进行另一个系列实验,但是对无特征的毯形衬底进行实验。在每次试验中,测量非晶碳层的厚度,然后沉积间隔物并测量间隔物的厚度,在间隔物沉积之后测量剩余的非晶碳层的厚度。通过将间隔物沉积之前的厚度减去间隔物沉积之后的厚度来计算碳消耗。表1示出了这个系列实验的结果。
表1.碳消耗和纳米层压层
如表所示,存在纳米层压层显著减小了碳消耗。在没有纳米层压层的情况下,碳消耗为15.4nm,而对于SiO2和TiO2纳米层压层两者,碳消耗仅约为8nm。因此,在非晶碳层上方沉积纳米层压层,特别是图案化的非晶碳层,在沉积间隔物时保护非晶碳层并且由于间隔物沉积可以沉积更高质量的薄膜。
结论
尽管为了理解清楚的目的描述了上述实施例的一些细节,但是应当认识到,在所附权利要求书的范围内可以进行某些变化和修改。应该指出的是,实施本实施例的过程、系统和设备的替代方式有很多。因此,本发明应当看成是说明性的而不是限制性的,并且实施例不限于本文给出的细节。
Claims (26)
1.一种加工半导体衬底的方法,所述方法包括:
沉积芯部层;
在所述芯部层上沉积纳米层压层;和
在所述纳米层压层上沉积金属氮化物或金属氧化物层,
其中所述纳米层压层包括氧化硅或氧化钛。
2.根据权利要求1所述的方法,其中,所述纳米层压层包括具有两个或更多个副层的堆层。
3.一种加工衬底的方法,该方法包括:
沉积芯部层;
在所述芯部层上沉积纳米层压层;和
在所述纳米层压层上沉积金属氮化物或金属氧化物层,其中使用等离子体增强原子层沉积(PEALD)通过以下沉积所述纳米层压层:
使所述衬底暴露于含钛前体或含硅前体;
使所述衬底暴露于氧化剂;和
在所述衬底暴露于氧化剂的同时引发等离子体。
4.一种加工衬底的方法,该方法包括:
沉积芯部层;
在所述芯部层上沉积纳米层压层;和
在所述纳米层压层上沉积金属氮化物或金属氧化物层,
其中,使用等离子体增强原子层沉积(PEALD)通过如下沉积所述金属氮化物或金属氧化物层:
使所述衬底暴露于含金属的前体;
使所述衬底暴露于氧化剂;和
当所述衬底以每平方毫米至少约1.768x 10-3W/平方毫米的HFRF功率暴露于氧化剂时,引发等离子体。
5.根据权利要求4所述的方法,其中,所述氧化剂包括一氧化二氮或氧气或二氧化碳或其混合物。
6.根据权利要求4所述的方法,其中,所述金属氮化物或金属氧化物层是在约3托至约3.5托之间的压力下沉积的。
7.根据权利要求4所述的方法,其中,所述金属氮化物或金属氧化物层是在约50℃至约400℃之间的温度下沉积的。
8.根据权利要求1至7中任一项所述的方法,其中,所述金属氮化物或金属氧化物层对所述芯部层具有蚀刻选择性。
9.根据权利要求1至7中任一项所述的方法,其中,所述芯部层包括非晶碳。
10.一种图案化半导体衬底的方法,该方法包括:
在芯部层上沉积保形膜之前,在图案化的芯部层上沉积纳米层压保护层;
在所述纳米层压保护层上沉积保形膜;
使所述保形膜平坦化以暴露出所述图案化的芯部层;和
选择性地蚀刻图案化的芯部层以形成掩模,
其中所述纳米层压保护层包括氧化硅或氧化钛。
11.权利要求10的方法,其中所述纳米层压保护层包括包含两个或更多个副层的堆层。
12.根据权利要求10所述的方法,其中,所述芯部层包括非晶碳。
13.根据权利要求10至12中任一项所述的方法,其中,所述纳米层压保护层的厚度在约15埃至约200埃之间。
14.根据权利要求10至12中任一项所述的方法,其中,
通过将所述半导体衬底暴露于含钛前体或含硅前体中,使用PEALD沉积所述纳米层压保护层;
使所述半导体衬底暴露于氧化剂;
在所述半导体衬底暴露于氧化剂的同时引发第一等离子体。
15.根据权利要求14所述的方法,其中所述纳米层压保护层在小于约100℃的温度下沉积。
16.如权利要求14所述的方法,其中所述纳米层压保护层是在约50℃至约150℃之间的温度下沉积的,并且所述第一等离子体是以每平方毫米衬底面积约1.768×10-4W到约1.768×10-3W的HFRF功率引发的。
17.根据权利要求14所述的方法,其中,
通过将所述半导体衬底暴露于含钛前体,使用PEALD沉积所述保形膜;
使所述半导体衬底暴露于氧化剂;
当所述半导体衬底以每平方毫米衬底面积至少约1.768×10-3W的HFRF功率暴露于所述氧化剂时,引发第二等离子体。
18.一种加工半导体衬底的方法,所述方法包括:
在所述半导体衬底上沉积纳米层压层;和
在所述纳米层压体层上沉积氧化钛层,该纳米层压体层的厚度为约15埃至约200埃,并且密度低于二氧化钛层的密度。
19.根据权利要求18所述的方法,还包括沉积非晶碳层,其中所述纳米层压层沉积在所述非晶碳层上。
20.根据权利要求19所述的方法,其中所述非晶碳层被图案化。
21.根据权利要求18、19、20中任一项所述的方法,其中,所述纳米层压层包括氧化硅或氧化钛。
22.根据权利要求18、19、20中任一项所述的方法,其中,使用等离子体增强的原子层沉积(PEALD)通过以下沉积所述纳米层压层:
使所述半导体衬底暴露于含钛前体或含硅前体;
使所述半导体衬底暴露于氧化剂;和
在所述半导体衬底暴露于氧化剂的同时启动等离子体。
23.一种加工半导体衬底的方法,所述方法包括:
(a)将所述半导体衬底暴露于第一含钛前体或含硅前体;
(b)使所述半导体衬底暴露于第一氧化剂;
(c)在每平方毫米衬底面积约1.768×10-4W到约1.768×10-3W的HFRF功率将所述半导体衬底暴露于所述第一氧化剂的同时引发第一等离子体;
(d)将所述半导体衬底暴露于第二含钛前体;
(e)使所述半导体衬底暴露于第二氧化剂;和
(f)在所述半导体衬底以每平方毫米衬底面积至少约1.768×10-3W的HFRF功率暴露于第二氧化剂的同时启动第二等离子体。
24.根据权利要求23所述的方法,其中,(a)至(c)在约50℃至150℃之间的温度下进行。
25.根据权利要求23所述的方法,其中,(d)至(f)在约50℃至400℃之间的温度下进行。
26.一种用于加工半导体衬底的设备,包括:
一个或多个处理室;
进入所述处理室的一个或多个气体入口和相关的流量控制硬件;
HFRF发生器;以及
具有至少一个处理器和存储器的控制器,其中
所述至少一个处理器和所述存储器彼此通信连接,
所述至少一个处理器至少操作性地连接所述流量控制硬件以及HFRF发生器;并且
所述存储器存储计算机可执行指令,所述计算机可执行指令用于:
使所述半导体衬底暴露于含金属前体;
使所述半导体衬底暴露于第一氧化剂;
在每平方毫米衬底面积约1.768×10-4W到约1.768×10-3W的HFRF功率将所述半导体衬底暴露于所述第一氧化剂的同时使第一等离子体产生;
使所述半导体衬底暴露于含钛前体;
使所述半导体衬底暴露于第二氧化剂;以及
在每平方毫米衬底面积至少约1.768×10-3W的HFRF功率将所述半导体衬底暴露于所述第二氧化剂的同时使第二等离子体产生。
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