TWI241718B - Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication - Google Patents

Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication Download PDF

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TWI241718B
TWI241718B TW092135851A TW92135851A TWI241718B TW I241718 B TWI241718 B TW I241718B TW 092135851 A TW092135851 A TW 092135851A TW 92135851 A TW92135851 A TW 92135851A TW I241718 B TWI241718 B TW I241718B
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semiconductor body
gate electrode
dielectric layer
gate
semiconductor
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TW200501424A (en
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Linton Thomas Jr
Rafael Rios
Robert Chau
Brian Doyle
Scott Hareland
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Intel Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
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  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
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Description

1241718 (1) 玖、發明說明 【發明所屬之技術領域】 本發明關係於半導體積體電路製造的領域，更明確地 說’關係於具有部份或完整包圍閘極電極之非平坦全空乏 基材電晶體及其製造方法。 【先前技術】 爲了增加裝置效能，絕緣層上覆矽（S0I)電晶體已經 提議出用以製造現代積體電路。第1圖例示標準全空乏絕 緣層上覆矽（S Ο I)電晶體〗〇 〇。s Ο I電晶體1 0 0包含一單結 晶砂基材1 02，具有一絕緣層〗04，例如一埋入氧化物形成 於其上。一單結晶矽主體106被形成在絕緣層1〇4上。一閘 極介電層1 0 8被形成在單一結晶矽主體！ 〇 6上及一閘極電極 1 1 〇被形成在閘極介電層1 〇 8上。源極1 1 2及汲極1 1 4被形成 在矽主體1 0 6中，沿著該閘極電極1 1 〇的兩側向相對側進行 〇 全空乏型SOI已經提出爲一電晶體結構，以利用理想 次臨限梯度，以最佳化導通電流/關閉電流比例。爲了完 成電晶體1 0 0之理想次臨限梯度，矽主體1 〇 6之厚度必須約 電晶體的閘極長度（Lg)尺寸的1/3，或Tsi = Lg/3。然而， 當閘極長度規格特別是當它們接近3 0奈米時’降低矽膜厚 度（Tsi)之強大需求使得此方法不實際。在30奈米閘長度時 ，矽主體的厚度被認爲需要低於1 〇奈米，及對於2 0奈米閘 極長度需要約6奈米。具有厚度低於10奈米之薄砂膜的製 -5 - 1241718 (2) 造被認爲極端困難。一方面，取得具有約奈米級之晶圓均 勻性係很困難的挑戰。另一方面，因爲在源極/汲極區中 之薄矽層在閘極蝕刻及各種閘極蝕刻及間隔層蝕刻後之淸 洗，留下不夠之矽1 0 6供成長，而在源極/汲極區域中之薄 矽層被消耗掉，所以，爲了能接觸這些薄膜，以形成上升 之源極/汲極區，以降低接面電極，變成幾乎不可能。 如第2A及2B圖所示之雙閘極（DG)已經被提出以避免 該矽厚度事項。該雙閘極（DG)裝置2 00包含一矽主體202， 形成在一絕緣基材2 0 4上。一閘極介電層2 0 6被形成在矽主 體202的兩側上及一閘極電極2 08被形成鄰近形成在矽主 體2 0 2的兩側上之閘極介電層2 0 6。一足夠厚絕緣層2 0 9， 例如氮化矽用以將閘極電極2 0 8與矽主體202的頂部電氣隔 絕開。 雙閘極（DG)裝置2 00基本上具有兩閘極，在裝置通道 的兩側各有一個。因爲雙閘極裝置2 0 0具有一閘極在通道 的每一側上，矽主體的厚度（Tsi)可以爲單閘極裝置厚度的 兩倍，並取得一全空乏電晶體操作。即，當於一雙閘極裝 置200時’可以形成一全空乏電晶體，其中Tsi = (2xLg)/3 。然而，雙閘極（DG)裝置200之最可製造形式需要主體2〇2 被以光微影術作出圖案，該微影爲用以圖案化裝置之閘極 長度（Lg)的0.7。爲了取得高密度積體電路，一般係想要 令最進步微影術相對於閘極電極20 8的閘極長度（Lg)發生 。雖然’雙閘極結構兩倍於矽膜的厚度（因爲在通道的兩 側均有一閘極），所以，此結構係很難加以隱藏製造。例 -6 - 1241718 (3) 如，矽主體2 Ο 2需要一矽主體蝕刻，其可以產生約5 : 1之 深寬比（高度對寬度）的矽主體2 0 2。
第3圖例示 MOSFET3 00之柱子。該MOSFET3 00柱包 含一汲極區3 02形成在一半導體基材中。一圓形矽柱3 0 3係 形成在半導體基材上。一閘極介電層3 0 6與一閘極電極3 0 4 係形成在圓形柱旁。一源極區3 0 8被形成在矽柱的頂部。 於源極及極區域間之電流流動於垂直於基材的方向。有關 柱形MOSFET3 0 0的問題爲以精心設計之非傳統製程技術 加以形成。柱形MOSFET的另一問題爲源極及汲極區係 分開處理，以造成用於區域之不同電氣特性。 【發明內容及實施方式】
本發明爲一新穎非平坦裝置結構，其具有一閘極電極 ’其係完全包圍於通道區域或閘極電極旁，並幾乎整個包 圍在通道區域旁，及其製造方法。於以下說明中，各種特 定細節係加以說明’以提供對本發明之完整了解。於其他 例子中’吾人知道半導體製程及製造技術並未特別詳細說 明’以避免不必要限制本發明。 本發明爲一新穎非平坦電晶體結構。於本發明之一實 施例中，非平坦電晶體具有一閘極電極，其係完全地包圍 在通道區旁。於本發明之另一實施例中，該非平坦電晶體 具有一閘極電極’其係部份或幾乎整個包圍住電晶體的通 道區域。具有閘極電極整個包圍通道區或幾乎整個包圍通 道區之電晶體的優點爲其更容易空乏裝置时通道區域，藉 1241718 (4) 以放鬆半導體主體的厚度（T s i)及寬度（W s i)尺寸限制。另 外，藉由完整或部份包圍住裝置的通道，裝置的驅動電流 係藉由提供兩個額外角落在裝匱中以增加載子密度而加以 加強。 第4 A圖爲非平坦電晶體4 0 0之立體圖，其係爲依據本 發明實施例之一全包屑閘極電極或部份包圍閘極霉極。第 4 B圖爲沿著第4 A圖閘極電極:新取f剖面圖，其中閘極電 極爲部份包圍該裝置的通道區域。第4C圖爲沿著第4A圖 閘極電極所取之剖面圖，其中閘極電極爲完整包圍裝置之 通道區域。該非平坦裝置結構在用於全空乏型基材電晶體 應用是相當理想。該非平#裝置結構包含一薄半導體主體 4 0 8形成在一絕緣基材402上。一閘極介電層422係形成在 半導體主體頂面、兩側壁及至少底面的至少一部份。一閘 極電極424被形成在閘極介電層422及半導體主體頂面上， 並形成鄰近形成在半導體主體側壁上之閘極介電層並形成 在半導體主體底面上之閘極介電層下。源極及汲極區被形 成於半導體主體408中並在閘極電極424的相對側上。因爲 閘極電極及閘極介電層包圍半導體主體408之通道區域並 在其三側及第四側之至少一部份，所以當電晶體被，，導通，， 時’半導體主體可以容易地完全空乏，藉以完成全空乏電 晶體的形成，其閘極長度低於30奈米，而不必使用特別薄 之半導體主體或者需要光微影圖形化半導體主體至低於裝 置閘極長度（Lg)的尺寸。即，本發明之非平坦電晶體結構 完成一全空乏電晶體，其中，半導體主體的厚度及半導體 1241718 (5) 主體的寬度等於裝置的閘極長度。因爲本發明之新穎非平 坦電晶體可以以全空乏方式動作，所以，裝置被特徵化有 理想（很陡峭）次臨限斜率（理想上，在2 5 °C 6 0 m V / d e c a d e)及 降低汲極感應阻障（DIB L)短通道效應低於i〇 〇mV/V及理想 上約60m V/V，其造成當裝置，，關閉，，時較低之洩漏電流， 造成較低功率消耗。 依據本發明實施例之非平坦電晶體4 0 0的例子係例示 於第4A-4C圖中。非平坦電晶體400係形成在一絕緣基材 402上。於本發明之一實施例中，絕緣基材4〇2包含一下單 結晶矽基材4 0 4，其上形成有一絕緣層4 0 6，其係例如爲二 氧化矽膜。然而，該非平坦電晶體400可以形成在任何已 知絕緣基材上，例如由二氧化矽、氮化物、氧化物及藍寶 石所形成之基材上。 非平坦電晶體400包含一半導體主體408。半導體主體 408提供裝置之源極區430、汲極區432及通道區域450。半 導體主體4 0 8可以由已知半導體材料，例如但並不限定於 矽（Si)、鍺（Ge)、矽鍺（SixGey)、砷化鎵（GaAs)、InSb、 GaP、GaSb及奈米碳管所形成。半導體主體408可以由任 何已知材料形成，其可以藉由施加外部電氣控制由一絕緣 狀態反轉至一導電狀態者。半導體主體4 0 8爲一理想單結 晶膜，當想要電晶體400之最佳電氣表現時。例如，電晶 體4 〇 〇被用於高效能應用，例如高密度電路，如微處理機 時，半導體主體4 0 8爲單一結晶膜。然而，當電晶體4 00用 於需要較少嚴格要求時，例如液晶顯示器時，半導體主體 -9- 1241718 (6) 4 Ο 8可以爲多結晶膜。絕緣層4 Ο 6將半導體主體4 Ο 8與單晶 矽基材4 0 2絕緣開。於本發明之一實施例中，半導體主體 4 0 8由單一結晶砂膜所形成。 半導體主體4 0 8具有一對側向相對之側壁4 1 0及側壁 412，其分開爲定義半導體主體寬度（Wsi)414之距離。另 外，半導體主體4 0 8具有一頂面416，與形成在基材40 2上 之底面4 1 8相對。於頂面4 1 6與底面底面4 1 8間之距離定義 一主體高度（Tsi)420。於本發明之一實施例中，主體高度 42 0係實質等於主體寬度（Wsi)414。於本發明一實施例中 ，半導體主體408具有較30奈米爲少之寬度414及高度 (Tsi)420，理想上係低於20奈米。於本發明一實施例中， 主體高度420係於主體寬度414之1/2到主體寬度4 Μ之兩倍 之間。 非平坦裝置400具有一閘極介電層422。閘極介電層 4 22係形成在半導體主體40 8之通道區45 0三個側之上及旁 邊，及在半導體主體408之通道區域450之底面418的至少 一部份上或旁，如第4 A - 4 C圖所示。於本發明之部份重疊 實施例中，如第4 B圖所示，閘極介電層4 2 2係形成在側壁 4 1 2上或接近側壁4 1 2、在頂面4 1 6上、在側壁4 1 0上或鄰近 側壁410上並形成在半導體主體408之底面41 8的一部份上 ，其由側壁4 1 2向底面之中心並覆蓋一第二部份，該部份 由側壁4 1 0向底面4 1 8中心延伸。於如第4B圖所示之幾乎 包圍實施例中，閘極介電層422覆蓋半導體主體4〇8之下角 落4 2 3並且在另一實施例中，則在每側上延伸半導體主體 -10- 1241718 (7) 4 0 8之寬度的約W3。於第4C圖所示之全包圍實施例中， 閘極介電層422係形成在側壁4]2上或附近、在頂面416上 、在側壁4 1 0上或附近、及在半導體主體4 〇 8之通道區域的 整個底面41 8上。閘極介電層422可以爲任何已知之閘極介 電層。於本發明之一實施例中，閘極介電層爲二氧化矽 (Si〇2)、氧氮化矽（SiOxNy)、或氮化矽（si3N4)介電層。於 本發明之一貫施例中，閘極介電層422爲一形成有厚度於 約5至2 0埃之氧氮化矽膜。於本發明之一實施例中，閘極 介電層4 2 2係爲一高K閘極介電層，例如一金屬氧化物介 電層，例如但並不限定於五氧化鉅（Ta205)、氧化鈦（Ti02) 、氧化飴（Hf02)、HfSiOxNy、氧化鉻（Zr02)及氧化鑭 (La02)。閘極介電層422可以爲其他高 K介電質，例如但 並不限定於PZT。 非平坦裝置400具有一閘極電極424。閘極電極424被 形成在閘極介電層422上及附近，如第4A-4C圖所示。於 第4 B圖所示之本發明之部份重疊實施例中，閘極電極4 2 4 係形成在形成有在半導體主體40 8之通道區域45 0之側壁 412上之閘極介電層422上或附近、並形成在形成在半導體 主體408之通道區域之頂面416上之閘極介電層422上、並 形成在形成在半導體主體408之通道區域之410上閘極介電 層422上或附近，並形成在形成在半導體主體4〇8之通道區 域之底面418下之閘極介電層422之下或其接附近。於本發 明之幾乎整個包圍閘極電極電晶體的一實施例中’聞極電 極4 2 4延伸於底面4 1 8下約在半導體主體之4 0 5之母一側上 -11- 1241718 (8) 之半導體主體40 8的寬度的1/3。該目標爲令閘極電極足夠 包圍裝置的角落42 3，以提供良好之角落控制。於幾乎整 個包圍的實施例中，底面之剩餘部份被形成在埋入絕緣層 4 〇 6上。於第4 C圖所示之整個包圍實施例中，閘極電極 424係形成在形成在半導體主體4 0 8之通道區之側壁412上 之閘極介電層422上或附近、形成在形成在半導體主體408 之通道區之頂面416上之閘極介電層422上或附近、並形成 在形成在半導體主體40 8之通道區之側壁410上之閘極介電 層422上或附近，、並形成在形成在半導體主體408之通道 區域上之閘極介電層422下或直接接近。閘極電極424具有 一對側向相對側壁42 6及42 8，其係爲定義電晶體400之閘 極長度（L g )之距離所分隔。於本發明之一實施例中，閘極 電極424之側向相對側壁426及428行進於半導體主體408之 側向相對4 1 0及側壁4 1 2垂直的方向。 閘極電極4 2 4可以由任意適當閘極電極材料所形成。 於本發明之對閘極電極4 2 4之一實施例中，閘極電極4 2 4包 含被摻雜至濃度密度於lxl〇19原子/公分3至lxl〇2】原子/公 分之間。於本發明之一實施例中，閘極電極可以爲一金 屬閘極電極，其例如但並不限定於鎢、鉅、鈦、及其氮化 物。於本發明之一實施例中，閘極電極係由具有功函數相 容於通道材料（例如對於Si爲4.0至4.5eV)之材料所形成。 可以了解的是，閘極電極424並不需要爲單一材料也可以 是薄膜之複合堆疊，例如但並不限定於多晶矽/金屬電極 或金屬/多晶砂電極。 -12- 1241718 (9) 非平坦1400具有一源極區430及一汲極區432。源極區 4 3 0及汲極區4 3 2係形成於半導體主體4 0 8中，在閘極電極 4 2 4的兩相對側上，如第4 A圖所示。源極區4 3 0及汲極區 4 3 2係由相同導電類型所形成，例如N型或P型導電性。 於本發明之一實施例中，源極區43 0及汲極區43 2具有於 lxl 〇19及1 χΙΟ21原子每立方公分之摻雜濃度。源極區43 0及 汲極區4 3 2可以由均勻濃度所形成，或者，可以包含不同 濃度或摻雜分佈之次區域，例如尖端區（例如源極/汲極延 伸）。於本發明之一實施例中，當電晶體400爲對稱電晶體 時，源極區4 3 0及汲極區4 3 2具有相同摻雜濃度與分佈。於 本發明之另一實施例中，當非平坦電晶體4 0 0被形成爲非 對稱電晶體時，源極區430及汲極區43 2之摻雜濃度與分佈 可以加以變化，以取得一特定電氣特徵。源極及汲極區也 可以包含一磊晶矽再成長及/或矽化物，以改良裝置效能 〇 位於源極區4 3 0及汲極區4 3 2間之半導體主體4 0 8的部 份定義電晶體400之通道區域450。通道區域450也可以定 義爲閘極電極42 4所包圍之半導體主體4 0 8之區域。然而， 經常源極/汲極區可以例如經由擴散略微延伸於閘極電極 下，以定義一略小於閘極電極長度（L g)之通道區。於本發 明之一實施例中，通道區域45〇爲一本質或未摻雜單晶砂 。於本發明之一實施例中，通道區域4 5 0爲被摻雜之單晶 5夕。當通道區域4 5 0爲被摻雑，則其典型被摻雜至於約 1 X ] 0 16至]X ] 0 19原子每立方公分之濃度位準。於本發明之 - 13- 1241718 (10) 一實施例中’當通道區被摻雜時，典型被摻雜與源極區 4 3 0及汲極區4 3 2導電類型相反者。例如，當源極及汲極區 爲N型導電型，則通道區4 5 〇將被摻雜至p型導電率。同 樣地’當源極及汲極區爲P導電類型時，通道區將爲N 導電型。以此方式，一非平坦電晶體40 0可以分別被形成 爲一 NMOS電晶體或pm〇S電晶體。通道區域4 5 0可以均 勻地摻雜或可以非均勻地摻雜或摻雜以不同濃度，提供特 定之電氣及效能特徵。例如，若想要的話，通道區域4 5 0 可以包含已知之”日暈”區。當電晶體被”導通”時，電流經 由閘極通道區域4 5 0流動於源極區4 3 0及汲極區間於平行於 基材4 0 2面之方向。 藉由提供一閘極介電層及閘極電極，其在所有側上包 圍半導體主體，該非平坦電晶體可以特徵於具有四通道及 四閘極，一閘極（gl)及延伸於源極及汲極區間在半導體主 體408之側41 2上之通道，、一閘極（g2)及延伸於源極及汲 極區間在半導體主體408之頂面416上之通道、一第三閘極 (g3)及延伸於源極及汲極區間在半導體主體4〇8之側壁410 上之通道、及一第四通道及閘極（g4)在源極及汲極區間在 半導體主體408之底面418上。電晶體400之閘極”寬度 ，，（Gw)係爲四個閘極寬度的總和。即，電晶體400之閘極寬 度等於在側壁410之半導體主體4〇8之主體局度420加上在 頂面416之半導體主體4〇8之寬度、加上在側壁412之半導 體主體408的主體高度420’加上在閘極^電極4 2 4上之半導 ρ主體408之底面量。較大”寬度”電晶體可以錯由使用多 -14 - 1241718 (11) 數綿接在一起（例如爲單閘極電極4 2 4所包圍之多數半導體 主體4 0 8 )加以取得。 如上所述，電晶體4〇〇之閘極”寬度”係等於由電晶體 4 00之半導體主體408所建立之閘極寬度之總和。爲了製造 較大閘極寬度之電晶體，電晶體4 0 0可以包含一額外或多 數半導體主體或指部408，如第5圖所示。每一半導體主體 4 0 8具有一閘極介電層4 2 2形成在其頂面及側壁及底面或底 面的一部份，如第5圖所示。閘極電極4 2 4係形成在每一半 導體主體408上之每一閘極介電層422上及其附近。每一半 導體主體408同時也包含一源極區430及一汲極區432，形 成在半導體主體4 0 8上’在鬧極電極4 2 4的相對側上，如第 5圖所示。於本發明之一實施例中，每一半導體主體408係 形成有與其半導體主體4〇8相同之寬度與高度（厚度）。於 本發明之另一實施例中，半導體主體408之每一源極區430 及汲極區4 3 2係如第5圖所示，爲源極著地墊5 6 0及一汲極 著地墊580所電氣耦合在一起。或者，源極區430及汲極區 4 3 2可以爲較高金屬化層（例如金屬1、金屬2、金屬3、…） 耦接在一起，用以電氣連接各電晶體400作成各功能電路 。如第5圖所示之電晶體4 0 〇的閘極寬度係等於由每一半導 體主體4 0 8所建立之閘極寬度的總和。以此方式，一三閘 極電晶體4 0 0可以任想要閘極寬度加以形成。 因爲通道區域4 5 0係爲閘極電極4 2 4及閘極介電層4 2 2 所包圍於所有側，所以，電晶體4 0 0可以以全空乏方式加 以操作，其中，當電晶體400”導通”時，通道區域4 5 0完全 -15- 1241718 (12) 地空乏，藉以提供一全空乏電晶體的有利電氣特徵與效能 。即，當電晶體電晶體4 0 0被”導通，，時，一空乏區被形成 在通道區域450中，及，在通道區域450之表面形成反轉層 (即一反轉層係形成在側面4 1 0及側壁4 1 2上並在半導體主 體的頂面4 1 6及底面4 1 8上）。反轉層具有與源極及汲極區 相同之導電性並在源極區及汲極區間形成一導電通道，以 允許電流流經其間。空乏區由反轉層下空乏自由載子。除 了反轉層外’整個通道區域450係被空乏出載子，因此， 電晶體可以認爲是”全空乏”電晶體。全空乏電晶體具有優 V 於非全空乏或部份空乏型電晶體的改良電氣特徵。例如， 以全空乏方式操作電晶體4 0 0，電晶體4 0 0會有理想或很陡 次臨限斜率。非平坦電晶體可以以低於80mV/decade及理 想上約60mV/decade之很陡次臨限斜率加以製造，即使當 以低於3 0奈米之半導體主體厚度製造時。另外，以全空乏 方式操作之電晶體4 00，電晶體400具有一改良汲極感應阻 障（DIB L)降低效應，其提供較佳”關閉”狀態洩漏，其造成 較低洩漏，藉以較少之功率消耗。於本發明之一實施例中 ，該三閘極電晶體400具有一較1 00mV/V爲少，理想上更 低於40m V/V之DIBL效應。 第9圖爲兩曲線圖9 0 2及9 0 4之例示，其說明以生產具 有30奈米（902)閘極長度及20奈米（904)閘極長度之全空乏 (FD)及部份空乏（PD)非平坦電晶體的主體高度及主體寬度 。於本發明之一實施例中，主體高度、主體寬度及閘極長 度係被選擇’以具有尺寸，其中可以形成一全空乏電晶體 -16- 1241718 (13) 。於其他實施例中，該非平坦電晶體具有一主體高度、主 體寬度及閘極長度，使得可以形成一部份空乏之電晶體。 本發明之非平坦電晶體可以被認爲是一非平坦電晶體 ’因爲通道區域450之反轉層被形成在半導體主體408之水 平及垂直方向中。本發明之半導體裝置也可以被認爲是一 非平坦裝置，因爲來自閘極電極424之電場被由水平（g2及 g4)及垂直側（gl及g3)施加。 依據本發明實施例之製造有多數全包圍閘極電極之非 平坦電晶體的方法被例示於第6A-6G圖中。第6A-6G圖之 方法可以被稱爲一減去製程。一非平坦電晶體的製造以一 絕緣基材6 0 2開始。一矽或半導體膜6 0 8被形成在絕緣基材 6 0 2上，如第6 A圖所示。於本發明之一實施例中，絕緣基 材6 0 2包含一下單晶矽基材6 0 4及一上絕緣層6 0 6，例如一 二氧化矽膜或氮化矽膜。絕緣層6 0 6將半導體膜6 0 8與基材 6〇4分隔’及於實施例中係形成至於約200至2000埃之厚度 。絕緣層6 0 6.有時被稱爲”埋入氧化物”層。當一矽或半導 體膜608被形成在一絕緣基材602上時，建立了一矽或半導 體上有絕緣層（SOI)基材。 雖然，半導體膜60 8理想上爲一矽膜，但於其他實施 例中也可以是其他類型之半導體膜，例如但並不限定於鍺 (Ge)’ 一 ϊ夕鍺合金（SixGey)、砷化鎵（GaAs)、InSb、GaP、 GaSb及奈米碳管。於本發明之一實施例中，半導體膜608 被摻雜爲一 P型或η型導電性，具有於1 X 1 〇 1 6 - 1 X 1 0 1 9原子 每立方公分之濃度位準。半導體膜6 0 8可以爲內部摻雜（即 -17- 1241718 (14) 於其沉積時加以摻雜）或者在其形成在基材6 〇 2後，例如藉 由離子佈植加以摻雜。在形成後之摻雜使得PMOS及 NMOS非平坦裝置更容易製造於同一絕緣基材上。於此點 之半導體主體的摻雜位準決定裝置的通道區的摻雜位準。 半導體膜6 0 8係形成至約等於隨後形成於用於製造非 平坦電晶體的半導體主體之想要高度的厚度。於本發明之 一實施例中，半導體膜6 0 8具有低於3 0奈米理想上低於2 0 奈米的厚度或高度609。於本發明之一實施例中，半導體 膜6 0 8被形成大約等於製造非平坦電晶體的閘極，，長度，，的 厚度。於本發明之一實施例中，半導體膜6 0 8係被形成較 裝置的想要閘極長度爲厚。於本發明之一實施例中，半導 體膜6 0 8係形成爲使得所製造之非平坦電晶體，能以所設 計之閘極長度（L g)之全空乏方式加以操作之厚度。 半導體膜608可以以已知方法形成在絕緣基材602上。 —稱爲S IΜ Ο X技術，以於絕緣基材上形成一砂的方法中 ，氧原子被以高劑量被佈植入單一結晶矽基材，然後，回 到以形成埋入之氧化物6 0 6於基材內。單一結晶砍基材在 埋入氧化物上之部份變成矽膜6 0 8。另一常用以形成S Ο I 基材的技術爲嘉晶砂膜轉移技術，其係大致被稱爲結合 S 0 I。於此技術中，一第一砂晶圓具有~薄氧化物成長在 其表面上，其隨後將作爲在S Ο I結構中之埋入氧化物6 0 6 。再者，一高劑量氫佈植物被引入第一砂晶圓中，以形成 在第一晶圓之矽表面下之高應變區。第一晶圓然後翻面並 黏結至一第二砂晶圓的表面。該第一晶圓然後沿著爲氫佈 -18- 1241718 (15) 植物所建立之高應變平面被切割。這形成一 S 0 I結構，其 頂面具有一薄矽層，而埋入氧化物則在該單結晶矽基材的 頂面之下。已知平滑技術，例如HCI平滑或化學機械硏磨 (CMP)均可以用以平滑該半導體膜60 8之頂面至其想要厚 度。 於此時，若想要，阻絕區（未顯示）可以形成在SOI半 導體膜6 0 8內，以將形成於其中之各個電晶體隔絕開。隔 絕區可以以例如已知之光微影及融刻技術，來鈾刻去包圍 一非平坦電晶體之基材膜6 0 8之部份，然後，以一絕緣膜 ’例如Si 02回塡被蝕刻之區域。 再者，標準光微影及蝕刻技術係用以定在用於該如 第6 B圖所示之三閘極電晶體之半導體膜6 〇 8中之半體主體 或 620。於本發明之一實施例中，鰭或主體620被作出圖 案，以具有一寬度6 1 8，其係等於或大於所製造電晶體的 想要閘極長度（Lg)之寬度。以此方式，用以製造該電晶體 的最嚴格光微影侷限爲有關於閘極電極圖案，而不是半導 體主體或鰭定義。於本發明之一實施例中，半導體主體或 鰭將具有一寬度6 1 8，其係少於或等於3 〇奈米，理想上係 低於或等於2 0奈米。於本發明之一實施例中，半導體主體 或鰭部具有一寬度6 1 8，其係大致等於矽主體高度6 〇 9。於 本發明之一實施例中，鰭或主體620具有一寬度6]8，其係 於半導體主體高度609之1/2至兩倍之間。 另外，光微影及蝕刻步驟可以用以形成多數半導體主 體或鰭部，用於如第5圖所示之單一電晶體。以此方式， -19- 1241718 (16) 具有不同閘極寬度（Gw)之電晶體可以製造在整個晶圓上。 光微影及蝕刻步驟可以用以由半導體膜形成源著地墊622 及汲極著地墊624，以提供用於該電晶體的接觸區域。另 外，當多數半導體主體用於非平坦電晶體時，著地墊可以 用以與各種源極區連接在一起，以連接各種汲極區在一起 〇 半導體膜6 0 8可以以已知光微影及蝕刻技術，來作出 圖案爲鰭及著地墊，該等技術大致包含以遮罩形成一光罩 '曝光、及顯影一全面沉積光阻膜、然後，蝕刻半導體膜 ’以對準光阻罩，以分別形成一或多數矽主體或鰭620及 源極及汲極著地墊6 2 2及6 2 4。半導體膜6 0 8被蝕刻，直到 曝露出下層之埋入絕緣層606爲止。已知半導體蝕刻技術 ’例如非等向電漿蝕刻或反應離子蝕刻可以用以蝕刻半導 體膜608，以對準光罩。在半導體膜608被蝕刻，以形成一 半導體主體或鰭620後（及源/汲極著地墊622及624，若想 要的話），則光阻爲已知技術，例如化學剝離及〇2去灰所 去除，以產生如第6B圖所示之基材。 再者，如第6C圖所示，形成在半導體主體620下之埋 入氧化物層6 06之一部份被去除。一短等向氧化物蝕刻可 以被執行以，，底切”半導體主體620並去除在半導體主體620 下之埋入氧化物層606之一部份或全部。於製造幾乎全包 圍閘極電極時，絕緣蝕刻（底切蝕刻）移除在半導體主體 62 0下之一部份絕緣膜。於本發明之一實施例中，蝕刻由 半導體主體620之每一側下，去除絕緣膜606之主體寬度的 -20- 1241718 (17) 約1 / 3。當形成具有全包圍閘極電極之電晶體時，埋入絕 緣層6 0 6之整個部份被由半導體主體6 2 0去除。於此時，半 導體主體6 2 0可以爲形成在埋入絕緣層之剩餘部份上之源 極及汲極著地墊6 2 2及6 2 4所支撐。已知等向氧化物蝕刻可 以利用，其係選擇半導體材料（即一蝕刻可以較優先蝕刻 絕緣膜6 0 6，而不顯著蝕刻半導體膜6 〇 8)。吾人想要具有 至少1 0 ·· 1之選擇性的蝕刻。當半導體膜6 0 8爲矽及絕緣膜 6 0 6爲氧化矽時，可以使用一包含氟化氫（H F)之緩衝氧化 物蝕刻劑（ΒΟΕ)。· 再者，一閘極介電層62 6係形成在每一半導體主體620 之上及旁邊。即，一閘極介電層626係形成在半導體主體 6 2 0之頂面6 2 7上，及在每一 _導體主體6 2 0之側向相對側 壁6 2 8及6 2 9上。當形成一部份包閘極電極時，閘極介電層 6 2 6係形成在半導體主體6 2 0之下側之曝露部份6 3 1上。當 形成一完全包圍閘極電極時，閘極介電層係形成在曝露半 導體主體的整個底面上。閘極介電層可以爲沉積介電質或 成長之介電質。閘極介電層6 2 6應爲一保角製程所形成， 該製程完成在半導體主體620之下側上，形成介電層626。 於本發明之一實施例中，閘極介電層6 2 6爲以乾/濕氧化製 程加以成長之二氧化砂介電質膜。於本發明之一實施例中 ，氧化矽膜被成長至於約5至1 5埃的厚度。於本發明之一 實施例中，閘極介電膜6 2 6爲一沉積介電質，例如但並不 限定於高介電常數膜，例如金屬氧化物介電質，例如五氧 化鉅（Ta2 0 5 )、氧化鈦（Ti〇2)、氧化飴（Hf02)、HfSiOxNy、 -21 - 1241718 (18) 氧化鉻（Zr02)及氧化鑭（La02)，或其他高K介電質，例如 由化學氣相沉積（CVD)或原子層沉積（AlD)所形成之ΡΖΤ 及 BST。 再者，如於第6 D圖所不，一聞極電極材料6 3 0爲全面 沉積在基材上。閘極電極630被形成在半導體主體620之頂 面627上之介電層622上；形成在半導體主體620之側壁628 及629上及附近之閘極介電層626上或附近；及形成在主體 6 2 0之底面上之閘極介電質附近或下方。閘極電極材料6 3 0 被以一保角製程加以形成，例如CVD或ALD，以確保閘 極電極材料可以塡充在半導體主體的底切部份，使得閘極 電極可以部份或整個地包圍住半導體主體6 0 8。閘極電極 材料6 3 0可以沉積至約.2 0 0至3 0 0 0埃之厚度。於一實施例中 ，閘極電極材料被沉積至足夠形成閘極電極的厚度或高度 ，具有至少三倍於半導體主體620之高度6 09的高度。於本 發明之一實施例中，閘極電極材料包含多結晶矽。於本發 明之另一實施例中，閘極電極材料包含一多結晶矽鍺合金 。於本發明之另一實施例中，閘極電極材料可以包含一金 屬膜、例如鎢、鉅、及其氮化物。 再者，如第6D圖所示，一硬罩材料被沉積並定義爲 一有圖案硬罩6 3 2，其定義閘極電極所予以形成之位置。 硬罩材料可以以任意材料形成，其並不會在後續蝕刻閘極 電極材料至一閘極電極時，不會被大量蝕刻者。於本發明 之一實施例中，硬罩材料爲形成有厚度2 0至1 0 0奈米的氮 化矽。硬罩材料可以使用傳統光微影及蝕刻技術，被形成 -22 - 1241718 (19) 以成爲一有圖案硬罩6 3 4。有圖案硬罩6 3 4被形成至一寬度 ’其係想要用於該裝置的電極閘極長度。 再者’鬧極電極材料被蝕刻以對準硬罩63 4，以形成 一閘極電極63 6。於本發明之一實施例中，閘極電極係首 先被非等向蝕刻，以對準硬罩，以形成如第6E圖所示之 一對側向相對之側壁6 3 9及6 4 1。於本發明之—實施例中， 非等向蝕刻被持續，直到幾乎所有未遮住閘極電極材料 63 0被移除’及埋入絕緣層6〇 6被露出前爲止。於本發明之 另一實施例中，非等向蝕刻被持續，直到所有未遮住閘極 電極材料被移除及露出埋入絕緣層6 0 6爲止。於本發明之 一實施例中，非等向蝕刻被以一適當蝕刻形成，其在閘極 電極之側壁6 3 9及641上形成鈍化聚合物，以協助確保垂直 側壁對準硬罩634。任何不會大量蝕刻硬罩及半導體膜608 並可非等向蝕刻閘極電極材料之適當非等向蝕刻技術及蝕 刻劑均可以使用。當半導體膜及閘極電極由同一材料作成 ’例如矽作成時，例如氮化矽之硬罩可以用以對半導體膜 作成圖案成爲主體，並於閘極圖案化蝕刻時留下硬罩，以 保護半導體主體於閘極蝕刻時不受蝕刻。於側向相對側壁 6 3 9及641間之距離定義裝置之閘極長度（Lg)。當硬罩材料 爲氮化矽時，及閘極電極材料爲矽或多晶矽時，閘極電極 可以被非等向蝕刻及一鈍化聚合物膜可以利用HBr/Cl2/〇2 化學品，以電漿餓刻加以形成。 再者，如第6 F圖所示，在非等向蝕刻後，蝕刻被切 換爲等向蝕刻。等向蝕刻由在半導體主體下之未形成閘極 ►23- 1241718 (20) 電極之區域移除閘極電極。重要的是，由半導體主體620 之下’去除閘極電極材料之不想要部份，使得”細絲線，，不 會殘留，而不會將源極及汲極區短路至閘極電極。被用以 去除”細絲線”之等向蝕刻可以在非等向蝕刻完全向下蝕刻 至下層絕緣層後加以完成，或可以在非等向蝕刻幾乎到達 下層絕緣層時加以完成。一在閘極電極上之聚合物側壁鈍 化層保護閘極電極，於非等向蝕刻步驟時，受到側向蝕刻 。閘極電極63 4之部份側向底切6 3 5可能在接近閘極電極之 底部造成，但閘極電極之鈍化頂部應保持其原始分佈。底 切的程度可以藉由修改絕緣層底切的量及凹槽進入絕緣層 的深度加以控制。閘極電極6 3 4被蝕刻，直到閘極電極被 完全地隔猶開半導體膜6 0 8爲止，該半導體膜60 8係用以形 成主體62 0及源極及汲極區著地墊。於本發明之一實施例 中，該等向蝕刻係利用一熱磷酸蝕刻法加以進行。於本發 明之一實施例中，用以界定硬罩及閘極電極63 6之光微影 製程利用用來製造非平坦電晶體的最小尺寸微影製程。（ 即，於本發明之一實施例中，閘極電極6 3 6之閘極長度 (Lg)具有由光微影術所定義之最小特性尺寸）。於本發明 之一實施例中，閘極長度係低於或等於3 〇奈米，理想上， 係低於或等於2 0奈米。 再者，用於電晶體的源極640及汲極642區係形成在半 導體主體6 2 0之閘極電極6 3 0之兩相對側上’如第6 G圖所 示。源極及汲極區6 4 0及6 4 2可以分別藉由放置摻雜物6 4 4 在半導體主體62 0之兩側63 9、641加以形成’以形成如第 -24- 1241718 (21) 6G圖所示之區域640及642。若源極及汲極墊622及624被 利用，則它們也同時加以摻雜。對於一 PMOS三閘極電晶 體，在閘極電極之相對側上之半導體鰭或主體62 0被摻雜 至P型導電性及至1χΐ〇2ί)-1χ1()21原子每立方公分之濃度， 以形成源極及汲極區。對於Ν Μ 0 S二閘極電晶體，在閘極 電極之相對側上之半導體鰭或主體620被摻雜至η型導電 性及至lx 1〇2()-1 xlO21原子每立方公分之濃度，以形成源極 及汲極區。於本發明一實施例中，主體被以離子佈植法加 以摻雜。於本發明之一實施例中，離子佈植發生於垂直方 向（即垂直於基材600的方向），如第6G圖所示。當閘極電 極63 0爲一多晶矽閘極電極時，其可以首先移除硬罩6 3 4在 離子佈植時加以摻雜。一多晶矽閘極電極6 3 0將作動爲一 遮罩，以防止離子佈植步驟摻雜非平坦電晶體的通道區 648。通道區648係爲位在閘極電極636之下及爲其所包圍 之半導體主體620的部份。若閘極電極6 3 6爲一金屬電極， 則介電硬罩63 4可以用以在離子佈植時阻擋摻雜。於其他 實施例中，其他方法，例如固體源擴散法，可以用以摻雜 半導體主體，以形成源極及汲極延伸部。於此點，完成了 具有部份或完整包圍閘電極之非平坦電晶體的製造。 於本發明之實施例中，也可以在形成源極/汲極區或 源極/汲極延伸區之前，”日暈”區可以形成在矽主體中。 曰暈區係形成在裝置之通道區648中之摻雜區，並具有相 同導電性，但較裝置之通道區之摻雜濃度略高。日暉區可 以利用大角度離子佈植技術，藉由離子佈植摻雜物在閘極 -25- 1241718 (22) 電極下加以形成。 另外，若想要的話，示於第6 G圖中之基材可以進一 步被處理，以形成其他已知之特性，例如，重摻雜源極/ 汲極接觸區，在源極及汲極區上之沉積矽，以及，閘極電 極，及在源極/汲極接觸區上形成矽化物，及在閘極電極 上。 第7 A-7D圖例示形成具有幾乎包圍或完全包圍閘極電 極之非平坦電晶體的替換閘極方法。該替換閘極技術，當 想要一金屬閘極電極時，係理想的。該替換閘極方法以相 同於上述第6A及6 B圖減成法之基材與處理開始。在半導 體膜圖案化成半導體主體或鰭6 2 0及形成源極及汲極著地 墊後，一介電膜702被全面地沉積在半導體主體及著地墊 上及在埋入絕緣層6 0 8之曝露部份上。絕緣層被形成至想 要閘極高度的厚度。絕緣層702可以爲任意適當絕緣層， 例如氮化矽或二氧化矽。介電膜7 0 2係由相對於手導體膜 6 0 8可以選擇之材料所形成。另外，介電膜理想上可以相 對於下層埋入絕緣層606加以選擇地蝕刻。當理入絕緣層 爲二氧化矽及半導體層6 0 8爲矽時，則絕緣層7 0 2可以爲氮 化矽。全面沉積絕緣膜702然後可以以已知光微影及蝕刻 技術加以圖案化，以在介電膜702中，形成開口或溝渠704 ’其定義予以形成閘極電極的位置。有圖案絕緣膜7 0 2形 成一藉由嵌入圖案法所形成用於形成閘極電極之定義罩。 介電膜7 02係被以適當蝕刻劑蝕刻，其可以非等向地蝕刻 介電膜7 0 2，而不必蝕刻半導體主體6 2 0。絕緣膜7 0 2被蝕 -26- 1241718 (23) 刻’直到下層埋入絕緣層6 06露出爲止及提供裝置之通道 區，如第7 A圖所示。開口 7 0 4係形成有一寬度7 〇 6，其係 爲非平坦電晶體的閘極長度（Lg)。 再者’埋入絕緣層6 06被由下層之半導體主體620下蝕 刻去，以形成一開口 705，其係在半導體主體620之主動通 道區形成底切，如第7B圖所示。當形成一具有幾乎包圍 閘極電極之非平坦電晶體時，絕緣層底切蝕刻由半導體主 體的每一側下去除絕緣層的一部份。於本發明之一實施例 中，底切蝕刻切入半導體主體一數量，使得後續形成之閘 極電極包圍至少半導體主體620之至少下角落，藉以控制 在角落中之電流流動。於本發明之一實施例中，當形成具 有幾乎包圍閘極電極之非平坦電晶體時，底切蝕刻幾乎移 除半導體主體620之每一側628及629下之絕緣體層的約1/3 。當形成具有完整包圍閘極電極之非平坦電晶體時，埋入 絕緣層底切蝕刻係持續，直到在半導體主體620之曝露部 份（即通道區）下之整個絕緣層被完全去除爲止。可以蝕刻 埋入絕緣層而不會太鈾刻半導體主體的已知等向鈾刻也可 以使用。當埋入絕緣層爲氧化矽及半導體爲矽時，一包含 緩衝HF之濕蝕刻劑可以用以形成底切開口 705。另外， 如第7B圖所示，底切蝕刻將略微切入有圖案之絕緣層704 內，造成較大長口 7 05及溝渠704。 再者，一閘極介電層624係如上所述形成在半導體主 體6 2 0之曝露部份（即通道區）上及附近。即，該閘極介電 層被形成在半導體主體620之頂面上、在半導體主體620之 -27- 1241718 (24) 側壁62 8及62 9上，及在半導體主體之底切631之曝露部份 之下或附近。於全包圍閘極電極之例子中，閘極介電層 624係形成在半導體主體的通道區的整個底切部631上。如 上所述，閘極介電層可以爲任意適當材料並應被形成有保 角沉積製程，例如原子層沉積（ALD)或化學氣相沉積 (CVD)，以確保在半導體主體62 0之底側631上，形成足夠 之閘極介電層。 再者，一閘極電極材料被全面沉積在基材上，其包含 在介電層7 02之頂面及在形成在半導體主體608之上及附近 之閘極介電質頂面或附近上，並沉積入絕緣層60 8。閘極 電極材料被沉積至足夠完全塡滿開口 7 05及7 06之厚度。閘 極電極材料可以爲任意如上所述之適當以形成閘極電極之 材料。於本發明之一實施例中，閘極電極材料爲一金屬膜 ，例如但並不限定於鎢（W)、氮化鈦（TiN)及矽化鈷（CoSi2) 。閘極電極材料應藉由沉積技術，例如化學氣相沉積 (CVD)或原子層沉積（ALD)加以形成，以形成一保角膜， 使得整個溝渠開口 706被塡滿，及在半導體主體62 0及介電 質罩702下之底切區705被塡滿。 再者，一平坦化技術被用以由介電層7 0 2之頂面移除 過量之閘極材料，使得被平坦化之頂面可以形成爲如第7 C 圖所示。任何已知及適當平坦化技術，例如化學機械硏磨 或電漿回蝕均可以用以由介電膜7 0 2之頂面移除過量之閘 極材料。 再者，如第7D圖所示，介電膜7 02被去除。於此時， -28- 1241718 (25) 源極及汲極可以藉由如上所述摻雜半導體主體6 2 0之部份 加以形成。這完成了利用替換閘極製程，以製造具有部份 或完全包圍閘極電極的非平坦裝置的方法。若想要的話， 已知其他特性，例如側壁間隔層、重摻雜源極/汲極接觸 區、及砂化物均可以於此時加入。 第8A-8G圖描述一種形成具有包圍或完全包圍鬧極電 極之非平坦裝置的方法，藉以在形成其他特性，例如尖端 區、間隔層、用於源極/汲極區之其他半導體及在源極/汲 極區上之矽化物後，使用一替換閘極處理。 該製程以相同於第6Α及6Β圖所示之基材及製程開始 。在半導體膜6 08圖案化，以形成半導體主體620或主體 62 0及源極/汲極著地墊622及.624後，犧牲閘極氧化物層 8 〇 2及一犧牲閘極電極8 0 4係被形成在矽主體6 2 0之頂面及 側壁上，如第8 Α圖所示。爲了形成犧牲閘極介電層及電 極，首先，一犧牲閘極介電層材料被全面沉積於基材之上 ，其包含絕緣層606之曝露面、半導體主體620及半導體著 地墊622及624之頂面與側壁。再者，一犧牲閘極電極材料 被全面沉積在一基材閘極介電層上。該犧牲閘極電極材料 係丨几積至爲用於非平坦裝置之後繪形成之閘極電極的高度 8 05之厚度。犧牲閘極電極材料及犧牲閘極介電材料然後 以已知技術加以圖案化，例如，以光微影及蝕刻法，以形 成如第8 A圖所示之犧牲閘極電極8 0 4及犧牲閘極介電層 8 〇 2。該犧牲閘極電極及犧牲閘極介電層係被圖案化成爲 相同形狀與後續形成閘極電極及閘極介電質所予以形成之 -29- 1241718 (26) 相同位置。於本發明一實施例中，犧牲閘極電極材料係由 例如氮化矽或多晶矽之材料所形成。 再者，若想要的話，尖端或源極/汲極延伸部可以藉 由在犧牲閘極電極8 04之相對側上以相同以形成源極/汲極 區之導電性類型的摻雜物加以摻雜。尖端區可以以已知技 術，例如離子佈植加以形成，該技術將摻雜物8 0 6佈植入 半導體主體62 0內，如第8A圖所示。犧牲閘極8 04防止半 導體主體620之通道區域在尖端形成步驟時被摻雜。於本 發明之一實施例中，形成具有摻雜濃度1 X 1 〇 1 9 -1 X 1 〇 2 1原子 每立方公分之尖端區。 再者，若想要的話，介電側壁間隔層8 0 8可以沿著犧 牲閘極電極804之相對側壁形成，如第8B圖所示。側壁間 隔層可以以任意已知技術形成，例如藉由全面沉積一保角 側壁間隔介電層在基材上，其包含犧牲閘極電極8 0 4之頂 面與側壁，及在半導體主體620及著地墊622及624的頂面 與側壁上，及至絕緣基材6 0 2之曝露面上。介電間隔材料 係沉積至一厚度，其係大約等於間隔層8 〇 8的寬度。於本 發明一實施例中，介電間隔材料係沉積至20- 1 00奈米的厚 度。間隔材料可以爲氮化矽、氧化矽、氧氮化矽或其組合 。介電間隔材料然後被非等向地回蝕，以由所有之水平面 (例如犧牲閘極電極8 0 4之頂面及半導體主體6 2 0及絕緣層 6 〇 6之頂面）移除介電間隔材料，同時，在垂直面上留下間 隔材料（例如犧牲閘極電極804之側壁），以形成如第8B圖 所示之側壁間隔層8 0 8。藉由使得犧牲閘極電極8 〇4之高度 -30- 1241718 (27) 8 〇5足夠高（例如3倍）於半導體主體62 0之厚度或高度，則 〜非等向回蝕之”過度蝕刻”可以用以由半導體主體62 0及 著地墊622及624的側壁去除間隔材料，同時，留下足夠間 隔材料，以在犧牲閘極電極8 04之側壁上，提供間隔層808 〇 再者，如第8C圖所示，其他矽810及/或矽化物812可 以被形成在半導體主體620及著地墊622及624之曝露頂面 與側壁上。其他矽也可以藉由利用一選擇沉積製程，形成 在半導體主體620之曝露面上。一選擇矽沉積製程沉積例 如磊晶矽之矽至含矽區，例如半導體主體620及著地墊622 及6 2 4，並且，不會將矽沉積在未含矽之區域上，例如犧 牲閘極電極804、介電間隔08及絕緣層606上。任意已知選 擇沉積製程均可以用以提供額外之磊晶矽。於本發明之一 實施例中，於50至5 00埃厚之額外磊晶矽被選擇地沉積至 半導體主體62 0及著地墊62 2及624上，以形成上升之源極/ 汲極區。 再者，若想要的話，重源極/汲極區可以形成在半導 體主體（及若有的話之額外矽）中，在閘極電極的相對側上 及進入著地墊6 2 2及6 2 4。側壁間隔層7 8 0 8防止下層之先前 形成之尖端區及半導體主體620被重源極/汲極佈植物81 1 所摻雜。另外，如同先前所述，犧牲閘極電極8 04遮蔽通 道區，於重源極/汲極形成步驟中，不受到摻雜。 若外，若想要的話，矽化物，例如但並不限定於矽化 鈷、矽化鎳、及矽化鈦可以被形成在半導體主體的曝露表 -31 - 1241718 (28) 上或至額外加入之矽膜上，如第8 C圖所示。矽化物可以 藉由利用一自行對準或” salicide”製程，形成在曝露半導 體主體或其他矽之頂面及側面上。於自行對準或 ” s a 1 i c i d e ”製程中，一耐火金屬膜，例如但並不限定於鈦 、鎳、及鈷可以用以全面沉積在基材上，包含矽區及介電 層區。基材然後被回火至一足夠溫度，以造成該全面沉積 之金屬層與含矽區反應，以形成一矽化物。例如側壁間隔 層8 0 8之區域，及絕緣層606將不會與金屬反應，及金屬將 在這些區域內保持不反應。再者，一選擇濕蝕刻可以用以 移除未反應金屬，而留下金屬矽化物8 1 2。以此方式，矽 化物可以選擇地形成在基材之矽或半導體區上，如第8 C 圖所示。 1 再者，如第8D圖所示，一介電層81 4被全面沉積於基 材上。該介電層係被形成至足以完全覆蓋包含犧牲閘極電 極804之基材的厚度。介電層814被由一可以相對於犧牲閘 極材及半導體主體620作選擇蝕刻之材料形成。即，介電 材料係由一材料形成，藉以該犧牲閘極電極8 04可以被移 除，而不必大量地蝕刻去介電層8 I 4。在全面沉積介電層 後，介電層被平坦化，例如，化學機械硏磨平坦化，直到 介電膜之頂面與犧牲閘極電極同平面及犧牲閘極電極之頂 面曝露如第8D圖所示爲止。 再者，如第8E圖所示，犧牲閘極804及閘極介電層 8 02係被蝕刻出，以形成一開口 8 1 6，其中予以形成閘極電 極。去除犧牲閘極808及犧牲閘極介電層8 02露出了非平坦 -32- 1241718 (29) 裝置之半導體主體620之通道區，如第8E圖所示。犧牲閘 極電極之移除形成一開口 8 1 6，其中將予以形成閘極電極 〇 再者，如第8 F圖所示，基材被曝露至一底切蝕刻， 以形成如上所述之底切開口 8 1 8。底切蝕刻自半導體主體 620之通道區下，移除絕緣層6 06之一部份’如第8F圖所 示。底切蝕刻可以用以由半導體主體620之通道下，完全 地移除絕緣層606，以曝露出半導體主體620之通道區的整 個下側，以形成一全包圍閘極電極。或者，底切蝕刻也可 以只由半導體主體620之通道區的每一側移除一部份之絕 緣層606，使得可以製造如上所述之部份包圍閘極電極。 再者’當閘極介電層8 2 0及閘極電極824被形成於開口 8 16及8 18中，如第8G圖所示時。首先，——閘極介電膜820 被全面沉積在基材上。如上所述，該閘極介電材料覆蓋半 導體主體620之通道區的頂面與側壁，及半導體主體620之 曝露下表面。閘極介電材料可以由一保角製程形成，例如 CVD或ALD，以確保閘極介電材料之形成在半導體主體 6 2 0之通道區的曝露下側上。再者，一閘極電極材料被全 面沉積在閘極介電層上。該閘極電極材料可以爲如上所述 之任意已知閘極電極材。聞極電極材料及閘極介電質然後 可以化學機械平坦化，直到介電層8 1 4之頂面係如第8 G圖 所不地錯出爲止。一·旦’聞極電極材料及閘極介電材料被 回硏磨或由頂介電材料814移除，則形成一閘極電極824及 閘極介電層8 2 0。閘極介電及閘極電極可如上所述地部份 -33- 1241718 (30) 或完全地包圍半導體主體620之通道區。介電層814可以如 第8 G圖所示地留在非平坦裝置上並變成，，後端”或層間介 電（ILD)及金屬化系統的一部份，其可以電氣耦接各種非 平坦裝置成爲功能電路。或者，介電層8 1 4可以於此時移 除並爲另一用於”後端”之另一類型之層間介電層所替代。 這完成了形成一非平坦裝置的方法，其具有部份包圍或完 整包圍之閘極電極。 因此，具有部份或完整包圍閘極電極之非平坦電晶體 及其製法已經加以描述。 【圖式簡單說明】 第1圖爲空乏型基材電晶體之剖面示意圖。 弟2A及2B圖爲一雙閘極空乏基材電晶體的示意圖。 第3圖爲柱形MOSFET示意圖。 第4A-4C圖爲一非平坦電晶體，具有全包圍或幾乎全包 圍之閘極電極。 第5圖爲一非平坦電晶體，具有多數半導體主體，具有全 包圍或部份包圍閘極電極。 第6A-6G圖爲一種利用減去製程，以製造具有全包圍 或幾乎全包圔閘極電極之非平坦電晶體的製造方法。 第7 A - 7 D圖爲一種利用替換閘極製程，以製造具有全 包圍或幾乎全包圍閘極電極之非平坦電晶體的形成方法。 第8A-8G圖爲利用替換閘極製程，以製造具有全包圍 或幾乎包圍閘極電極之非平坦電晶體的形成方法。 >34- 1241718 (31) 第9圖爲一曲線圖，例示可以用以取得具有閘極長度 (Lg)20奈米及30奈米之部份空乏及全空乏非平坦電晶體之 主體高度及主體寬度。 [圖號說明] 1 00 絕 緣 層 上 覆 矽 電晶體 1 02 單 結 晶 矽 基 材 1 04 絕 緣 層 1 06 單 一 結 晶 矽 主 體 1 08 閘 極 介 電 層 110 閘 極 電 極 112 源 極 114 汲 極 200 雙 閘 極 裝 置 202 矽 主 體 204 絕 緣 基 材 206 閘 極 介 電 層 208 閘 極 電 極 209 絕 緣 層 300 MOSFET 3 02 汲 極 區 303 矽 柱 3 04 閘 極 電 極 306 閘 極 介 電 層 -35- 源極區 非平坦電晶體 絕緣基材 單結晶矽基材 絕緣層 半導體主體 側壁
半導體主體寬度 頂面 底面 主體高度 閘極介電層 下角落 閘極電極
側壁 源極區 汲極區 通道區 源極著地墊 汲極著地墊 絕緣基材 單結晶矽基材 -36- 頂絕緣層 半導體膜 局度 寬度 半導體主體 源極著地墊 汲極著地墊
側壁 側壁 閘極電極 曝露部份 有圖案硬罩 閘極電極 側壁
側向底切 源極區 汲極區 摻雜物 介電膜 開口 開口 犧牲閘極氧化物層 -37- 犧牲閘極電極 摻雜物 側壁間隔層 矽 佈植物 矽化物 介電層
開口 底切開口 閘極介電層 閘極電極 曲線圖 曲線圖
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Claims (1)

1241718 ⑴ 拾、申請專利範圍 1.一種非平坦半導體裝置，包含： 一半導體主體，具有一頂面，與相對之底面形成在一 糸色緣基材上，其中該半導體主體具有一對側向相對之側壁 ， . * • \ 一閘極介電層，形成在該半導體主體的頂面上、在該 半導體主體的底面上、及在該半導體主體側向相對之側壁 上； 一閘極電極，形成在該閘禪介電層上、在該半導體主 體的頂面上，並接近該在半導體主體的，側向相對側壁上之 閘極介電層、及在該半導體主體的底面上之閘極介電層下 •，及 、 一對源極/汲極區，形成在該半導體主體中，在該閘 極電極的相對側上。 2 .如申請專利範圍第1項所述之半導體裝置，其中該 半導體主體爲一結晶矽膜。 3 ·如申請專利範圍第1項所述之半導體裝置，其中該 半導體主體爲由鍺、矽鍺、砷化鎵、I n S b、G a P、G a S b、 及奈米碳管所構成之群組中所選出。 4 ·如申請專利範圍第1項所述之半導體裝置，其中該 閘極電極包含由多晶矽、鎢、鉬、鈦、及金屬氮化物所構 成之群組中所選出之材料。 5 .如申請專利範圍第]項所述之半導體裝置，其中該 絕緣基材包含一形成在單結晶矽基材上之氧化物膜。 -39- 1241718 (2) 6 .如申請專利範圍第]項所述之半導體裝置 半導體裝置更包含至少一額外半導體主體，其具 及一底面、及一對側向相對側壁，其中一閘極介 成在該頂面、在底面及至少另一半導體主體的側 其中該閘極電極係形成在該閘極介電層上在，該 半導體主體的頂面上，及鄰近該閘極介電層，在 一半導體主體的側向相對側壁上、及在該至少另 主體的底面上之閘極介電層下。 7.—種非平坦半導體裝置，包含： 一半導體主體，具有一頂面與一底面相對， 份形成在一絕緣基材上，該半導體主體具有側向 ，形成在該絕緣基材上； 一閘極介電層，形成在該半導體主體的頂面 半導體主體的側向相對側壁上、及在半導體主體 一部份上，而不在該絕緣基材上； 一閘極電極，形成在該半導體主體的頂面上 電層上並接近該在半導體主體側向相對側壁上之 、並在該半導體主體的底面上之閘極介電層下；< 一對源極/汲極區，形成在該閘極電極之相 矽主體中。 8 ·如申請專利範圍第7項所述之半導體裝置 半導體主體爲一單一結晶矽膜。 9.如申請專利範圍第7項所述之半導體裝置 半導體主體爲由鍺、矽鍺、砷化鎵、InSb、GaP、 ，其中該 有一頂面 電層被形 壁上，及 至少另一 該至少另 一半導體 具有一部 相對側壁 上、在該 的底面的 之閘極介 閘極電極 及 對側上之 ，其中該 ，其中該 GaSb 及 -40- 1241718 (3) 奈米碳管所構成之群組中所選出。 1 〇 .如申請專利範圍第7項所述之半導體裝置，其中該 閘極電極包含由多結晶矽、鎢、鉅、鈦、及金屬氮化物所 構成之群組中所選出之材料。 1 1 ·如申請專利範圍第7項所述之半導體裝置，其中該 絕緣基材包含一形成在單結晶矽基材上之氧化物膜。 1 2 ·如申請專利範圍第】項所述之半導體裝置，其中該 半導體裝置更包含至少一額外半導體主體，其具有一頂面 及一底面，及一對側向相對側壁，其中，一閘極介電層係 形成在該至少另一半導體主體的頂面、底面及側壁上，及 其中該閘極電極係形成在該至少另一半導體主體的頂面上 之閘極介電層上，並鄰近該至少另一半導體主體的側向相 對側壁上之閘極介電層、並在該至少另一半導體主體的底 面上之閘極介電層下。 1 3 · —種形成一非平坦半導體裝置的方法，包含： 形成一半導體主體，具有一頂面，相對於一底面、及 一對側向相對之側壁在一絕緣基材上； 形成一閘極介電層，在該半導體主體的頂面上、在半 導體主體的側向相對側壁上、及在半導體主體底面之至少 一部份上； 形成一閘極電極，在該半導體主體頂面上之閘極介電 層上並鄰近該半導體主體側向相對側壁上之閘極介電質， 並鄰近形成在該半導體主體的底面之至少一部份上之閘極 介電層；及 -41 - 1241718 (4) 形成一對源極/汲極區，在該閘極電極之相對側上， 在半導體主體中。 1 4 .如申請專利範圍第1 3項所述之方法，其中該閘極 介電層及閘極電極係形成在該半導體主體的整個通道區下 〇 1 5 .如申請專利範圍第1 3項所述之方法，其中該半導 體主體的底面的一部份係形成在該絕緣基材上，及其中該 在絕緣基材上之部份係位在半導體主體的頂面上之閘極電 極下。 1 6 .如申請專利範圍第〗3項所述之方法，其中該半導 體主體爲單一結晶砂膜。 1 7 .如申請專利範圍第丨3項所述之方法，其中該半導 體主體係由鍺、矽鍺、砷化鎵、InSb、GaP、GaSb、及奈 米碳管所構成之群組中所選出。 1 8 ·如申請專利範圍第1 3項所述之方法，其中該閘極 電極包含由多結晶矽、鎢、鉅、鈦、及金屬氮化物所構成 之群組中所選出之材料。 Ϊ 9 ·如申請專利範圍第1 3項所述之方法，其中該絕緣 基材包含一形成在單結晶矽基材上之氧化物膜。 2 0.如申請專利範圍第13項所述之方法，更包含形成 至少一額外半導體主體，其具有一頂面及一底面，及一對 側向相封側壁，以及’形成一閘極介電層在該至少另一半 導體主體的頂面、底面及側壁上，及其中該閘極電極係形 成在該至少另一半導體主體的頂面上之閘極介電層上，並 ‘42- 1241718 (5) 鄰近該至少另一半導體主體的側向相對側壁上之閘極介電 層 ' 並在該至少另一半導體主體的底面上之閘極介電層下 〇 2 1 . —種形成非平坦電晶體的方法，包含： 形成一半導體主體，具有一對側向相對側壁及一頂面 及一底面，在一絕緣基材上； 由+導體主體下，移除該絕緣基材之一部份，以底切 該半導體主體並曝露該半導體主體底面的一部份； 形成一閘極介電層，在該半導體主體的頂面上、在該 半導體主體的側壁上、在該半導體主體的曝露底面上； 沉積一閘極材料，在該半導體主體上並在其旁邊，及 在半導體主體的曝露部份下； 利用一第一非等向蝕刻，隨後，一等向蝕刻，以蝕刻 閘極電極材料進入閘極電極，以形成一閘極電極，其係形 成在該半導體主體的頂面上之閘極介電層上、並形成在形 成於半導體主體底面之曝露部份上之閘極介電層下；及 將摻雜物放入半導體主體內，並在該閘極電極之相對 側上，以形成一對源極/汲極區。 2 2 ·如申請專利範圍第2 1項所述之方法，其中該半導 體主體係由單一結晶矽加以形成。 2 3 .如申請專利範圍第2 2項所述之方法，其中該絕緣 基材包含一下單結晶矽基材及一頂矽氧化物。 24·—種形成一非平坦電晶體的方法，包含： 形成一半導體主體，具有一頂面及一底面及一對側向 -43- 1241718 (6) 相對側壁，在一絕緣基材上； 在半導體主體上及附近，形成一介電層，其中該介電 膜具有一開口，其曝露出該半導體主體的通道區； 移除在半導體主體下之上述開口中之絕緣基材的一部 份，以曝露出該半導體主體底面之至少一部份； 形成一閘極介電層在該半導體主體的頂面及側壁上在 開口中，並在該半導體主體的底面之曝露部份上； 全面沉積一閘極電極材料在該介電膜上並進入該開口 ，並在該半導體主體的頂面上之閘極介電層上、鄰近該半 導體主體側壁上之閘極介電層並在該半導體主體的曝露部 份上之閘極介電層下； 由介電膜之頂面移除閘極電極材料，以形成一閘極電 極； 移除該介電膜；及 將該摻雜物放入該半導體主體在該電極之兩相對側上 ，以形成一對源極/汲極區。 2 5.如申請專利範圍第24項所述之方法，其中該半導 體主體爲單一結晶矽。 2 6 .如申請專利範圍第2 5項所述之方法，其中該絕緣 基材包含一下單結晶矽基材及一頂矽氧化物絕緣膜。 2 7 . —種形成一非平坦電晶體的方法，包含： 形成一半導體主體，具有一頂面及一底面及一對側向 相對之側壁在一絕緣基材上； 形成一犧牲閘極電極在該半導體主體的頂面上並鄰近 -44 *- 1241718 (7) 該半導體主體的側向相對側壁，該犧牲閘極電極具有一對 側向相對之側壁； 將摻雜物放入在犧牲閘極電極之相對側上之半導體主 體內，以在該閘極電極相對側上，形成一對源極/汲極延 伸部； 沿者該犧牲閘極電極之側向相對側壁，形成一*對側壁 間隔層； 鄰近該側壁間隔層，在半導體主體上，形成矽； 將摻雜物放入矽內並進入與側壁間隔層相對準之半導 體主體內； 在形成於半導體主體上之矽上，形成一鄰近該側壁間 隔層之矽化物； 在該矽化物上、該犧牲閘極電極上及該等側壁間隔間 上，形成一介電層； 平坦化該介電層，直到該介電層之頂面與犧牲閘極電 極之頂面同一平面及露出該犧牲閘極電極爲止； 移除該犧牲閘極電極，以曝露出該半導體主體的通道 區及該絕緣基材； 移除在該開口中之半導體主體下之絕緣基材的一部份 ，以曝露該半導體主體的底面的至少一部份； 形成一閘極介電層，在該半導體主體的頂面及側壁上 ，在該開口中及在半導體主體之曝露底面之該部份上； 全面沉積一閘極電極材料在該閘極介電層並進入該開 口並在該半導體主體的頂面上之該閘極介電層上、並接近 -45- 1241718 (8) 該半導體主體側壁上之閘極介電層、及半導體主體的底面 之曝露部份上之閘極介電層下；及 由該介電膜之頂面上，移除該閘極電極材料，以形成 一閘極電極。 2 8 .如申請專利範圍第2 7項所述之方法，其中該半導 體主體係由單一結晶矽所形成。 2 9 .如申請專利範圍第2 8項所述之方法，其中該絕緣 基材包含一下單結晶矽基材及一頂矽絕緣膜。 - 46-
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US20090061572A1 (en) 2009-03-05
WO2005010994A1 (en) 2005-02-03
DE60335301D1 (de) 2011-01-20
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EP1639649B1 (en) 2010-12-08
US7456476B2 (en) 2008-11-25
CN100541797C (zh) 2009-09-16
AU2003301042A1 (en) 2005-02-14
EP2270868B1 (en) 2015-05-20
US8273626B2 (en) 2012-09-25
US7820513B2 (en) 2010-10-26
TW200501424A (en) 2005-01-01
EP2270868A1 (en) 2011-01-05
US20060172497A1 (en) 2006-08-03
CN1577850A (zh) 2005-02-09
ATE491229T1 (de) 2010-12-15
US20110020987A1 (en) 2011-01-27

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