JP4865197B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP4865197B2
JP4865197B2 JP2004194690A JP2004194690A JP4865197B2 JP 4865197 B2 JP4865197 B2 JP 4865197B2 JP 2004194690 A JP2004194690 A JP 2004194690A JP 2004194690 A JP2004194690 A JP 2004194690A JP 4865197 B2 JP4865197 B2 JP 4865197B2
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Japan
Prior art keywords
semiconductor device
semiconductor element
semiconductor
wiring
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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JP2004194690A
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English (en)
Japanese (ja)
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JP2006019433A (ja
JP2006019433A5 (enExample
Inventor
洋一郎 栗田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
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Renesas Electronics Corp
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Priority to JP2004194690A priority Critical patent/JP4865197B2/ja
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to US11/159,157 priority patent/US7795721B2/en
Publication of JP2006019433A publication Critical patent/JP2006019433A/ja
Publication of JP2006019433A5 publication Critical patent/JP2006019433A5/ja
Priority to US12/169,930 priority patent/US8193033B2/en
Priority to US12/850,232 priority patent/US8207605B2/en
Application granted granted Critical
Publication of JP4865197B2 publication Critical patent/JP4865197B2/ja
Priority to US13/495,494 priority patent/US8541874B2/en
Priority to US13/972,162 priority patent/US8890305B2/en
Priority to US14/524,718 priority patent/US9324699B2/en
Priority to US15/072,803 priority patent/US20160204092A1/en
Priority to US16/375,282 priority patent/US10672750B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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US11/159,157 US7795721B2 (en) 2004-06-30 2005-06-23 Semiconductor device and method for manufacturing the same
US12/169,930 US8193033B2 (en) 2004-06-30 2008-07-09 Semiconductor device having a sealing resin and method of manufacturing the same
US12/850,232 US8207605B2 (en) 2004-06-30 2010-08-04 Semiconductor device having a sealing resin and method of manufacturing the same
US13/495,494 US8541874B2 (en) 2004-06-30 2012-06-13 Semiconductor device
US13/972,162 US8890305B2 (en) 2004-06-30 2013-08-21 Semiconductor device
US14/524,718 US9324699B2 (en) 2004-06-30 2014-10-27 Semiconductor device
US15/072,803 US20160204092A1 (en) 2004-06-30 2016-03-17 Semiconductor device
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KR20200031322A (ko) 2018-09-14 2020-03-24 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
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Families Citing this family (172)

* Cited by examiner, † Cited by third party
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US20070252260A1 (en) * 2006-04-28 2007-11-01 Micron Technology, Inc. Stacked die packages
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JP4897451B2 (ja) * 2006-12-04 2012-03-14 ルネサスエレクトロニクス株式会社 半導体装置
JP5183949B2 (ja) 2007-03-30 2013-04-17 日本電気株式会社 半導体装置の製造方法
JP5125185B2 (ja) * 2007-04-03 2013-01-23 株式会社ニコン 半導体装置
JP2008294423A (ja) * 2007-04-24 2008-12-04 Nec Electronics Corp 半導体装置
KR100909322B1 (ko) * 2007-07-02 2009-07-24 주식회사 네패스 초박형 반도체 패키지 및 그 제조방법
JP5068133B2 (ja) * 2007-10-17 2012-11-07 新光電気工業株式会社 半導体チップ積層構造体及び半導体装置
KR20090056044A (ko) * 2007-11-29 2009-06-03 삼성전자주식회사 반도체 소자 패키지 및 이를 제조하는 방법
KR100925665B1 (ko) * 2007-12-10 2009-11-06 주식회사 네패스 시스템 인 패키지 및 그 제조 방법
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US8456002B2 (en) 2007-12-14 2013-06-04 Stats Chippac Ltd. Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief
US9318441B2 (en) 2007-12-14 2016-04-19 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial adhesive over contact pads of semiconductor die
US8183095B2 (en) 2010-03-12 2012-05-22 Stats Chippac, Ltd. Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
US8343809B2 (en) * 2010-03-15 2013-01-01 Stats Chippac, Ltd. Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die
US7867819B2 (en) 2007-12-27 2011-01-11 Sandisk Corporation Semiconductor package including flip chip controller at bottom of die stack
CN101632169B (zh) 2007-12-28 2012-05-23 揖斐电株式会社 中介层以及中介层的制造方法
JP5484058B2 (ja) 2007-12-28 2014-05-07 イビデン株式会社 インターポーザー及びインターポーザーの製造方法
US8017451B2 (en) 2008-04-04 2011-09-13 The Charles Stark Draper Laboratory, Inc. Electronic modules and methods for forming the same
US8273603B2 (en) * 2008-04-04 2012-09-25 The Charles Stark Draper Laboratory, Inc. Interposers, electronic modules, and methods for forming the same
JP2009295740A (ja) * 2008-06-04 2009-12-17 Elpida Memory Inc メモリチップ及び半導体装置
JP5078808B2 (ja) * 2008-09-03 2012-11-21 ラピスセミコンダクタ株式会社 半導体装置の製造方法
US8063475B2 (en) * 2008-09-26 2011-11-22 Stats Chippac Ltd. Semiconductor package system with through silicon via interposer
US8314499B2 (en) * 2008-11-14 2012-11-20 Fairchild Semiconductor Corporation Flexible and stackable semiconductor die packages having thin patterned conductive layers
US8129824B1 (en) * 2008-12-03 2012-03-06 Amkor Technology, Inc. Shielding for a semiconductor package
US8354304B2 (en) * 2008-12-05 2013-01-15 Stats Chippac, Ltd. Semiconductor device and method of forming conductive posts embedded in photosensitive encapsulant
US7993941B2 (en) 2008-12-05 2011-08-09 Stats Chippac, Ltd. Semiconductor package and method of forming Z-direction conductive posts embedded in structurally protective encapsulant
US8399983B1 (en) * 2008-12-11 2013-03-19 Xilinx, Inc. Semiconductor assembly with integrated circuit and companion device
JP5058144B2 (ja) * 2008-12-25 2012-10-24 新光電気工業株式会社 半導体素子の樹脂封止方法
KR101004684B1 (ko) * 2008-12-26 2011-01-04 주식회사 하이닉스반도체 적층형 반도체 패키지
US9735136B2 (en) * 2009-03-09 2017-08-15 Micron Technology, Inc. Method for embedding silicon die into a stacked package
JP2010245107A (ja) * 2009-04-01 2010-10-28 Shinko Electric Ind Co Ltd 半導体装置及びその製造方法
JP2010245383A (ja) * 2009-04-08 2010-10-28 Elpida Memory Inc 半導体装置および半導体装置の製造方法
US20100314730A1 (en) * 2009-06-16 2010-12-16 Broadcom Corporation Stacked hybrid interposer through silicon via (TSV) package
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US8378230B2 (en) 2009-07-23 2013-02-19 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US8039304B2 (en) * 2009-08-12 2011-10-18 Stats Chippac, Ltd. Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structures
US8410376B2 (en) 2009-08-28 2013-04-02 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US20110050334A1 (en) * 2009-09-02 2011-03-03 Qualcomm Incorporated Integrated Voltage Regulator with Embedded Passive Device(s)
JP5715334B2 (ja) 2009-10-15 2015-05-07 ルネサスエレクトロニクス株式会社 半導体装置
US8008121B2 (en) 2009-11-04 2011-08-30 Stats Chippac, Ltd. Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate
US9999129B2 (en) * 2009-11-12 2018-06-12 Intel Corporation Microelectronic device and method of manufacturing same
FR2953064B1 (fr) * 2009-11-20 2011-12-16 St Microelectronics Tours Sas Procede d'encapsulation de composants electroniques sur tranche
EP2330618A1 (en) 2009-12-04 2011-06-08 STMicroelectronics (Grenoble 2) SAS Rebuilt wafer assembly
US20110186960A1 (en) * 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
US9385095B2 (en) 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8519537B2 (en) * 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US9548240B2 (en) 2010-03-15 2017-01-17 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming repassivation layer for robust low cost fan-out semiconductor package
US8618654B2 (en) * 2010-07-20 2013-12-31 Marvell World Trade Ltd. Structures embedded within core material and methods of manufacturing thereof
US8742603B2 (en) * 2010-05-20 2014-06-03 Qualcomm Incorporated Process for improving package warpage and connection reliability through use of a backside mold configuration (BSMC)
US9735113B2 (en) 2010-05-24 2017-08-15 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming ultra thin multi-die face-to-face WLCSP
US10159154B2 (en) * 2010-06-03 2018-12-18 Hsio Technologies, Llc Fusion bonded liquid crystal polymer circuit structure
US9048112B2 (en) 2010-06-29 2015-06-02 Qualcomm Incorporated Integrated voltage regulator with embedded passive device(s) for a stacked IC
KR101710178B1 (ko) * 2010-06-29 2017-02-24 삼성전자 주식회사 임베디이드 칩 온 칩 패키지 및 이를 포함하는 패키지 온 패키지
KR101123805B1 (ko) * 2010-07-26 2012-03-12 주식회사 하이닉스반도체 스택 패키지 및 그 제조방법
US8435835B2 (en) * 2010-09-02 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming base leads from base substrate as standoff for stacking semiconductor die
KR101207273B1 (ko) * 2010-09-03 2012-12-03 에스케이하이닉스 주식회사 임베디드 패키지 및 그 형성방법
JP2012114173A (ja) * 2010-11-23 2012-06-14 Shinko Electric Ind Co Ltd 半導体装置の製造方法及び半導体装置
US8619431B2 (en) * 2010-12-22 2013-12-31 ADL Engineering Inc. Three-dimensional system-in-package package-on-package structure
JP2012169440A (ja) * 2011-02-14 2012-09-06 Fujitsu Semiconductor Ltd 半導体装置及びその製造方法
US8841765B2 (en) * 2011-04-22 2014-09-23 Tessera, Inc. Multi-chip module with stacked face-down connected dies
US8642382B2 (en) * 2011-06-20 2014-02-04 Stats Chippac Ltd. Integrated circuit packaging system with support structure and method of manufacture thereof
US8502390B2 (en) 2011-07-12 2013-08-06 Tessera, Inc. De-skewed multi-die packages
US8823165B2 (en) 2011-07-12 2014-09-02 Invensas Corporation Memory module in a package
US8513817B2 (en) 2011-07-12 2013-08-20 Invensas Corporation Memory module in a package
US8552567B2 (en) 2011-07-27 2013-10-08 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
US8937309B2 (en) 2011-08-08 2015-01-20 Micron Technology, Inc. Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication
JPWO2013035655A1 (ja) * 2011-09-09 2015-03-23 株式会社村田製作所 モジュール基板
US8461676B2 (en) 2011-09-09 2013-06-11 Qualcomm Incorporated Soldering relief method and semiconductor device employing same
US20130075923A1 (en) * 2011-09-23 2013-03-28 YeongIm Park Integrated circuit packaging system with encapsulation and method of manufacture thereof
US8436457B2 (en) 2011-10-03 2013-05-07 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
US8917532B2 (en) 2011-10-03 2014-12-23 Invensas Corporation Stub minimization with terminal grids offset from center of package
KR101894823B1 (ko) 2011-10-03 2018-09-04 인벤사스 코포레이션 평행한 윈도우를 갖는 다중-다이 와이어 본드 어셈블리를 위한 스터브 최소화
US8610260B2 (en) 2011-10-03 2013-12-17 Invensas Corporation Stub minimization for assemblies without wirebonds to package substrate
US8441111B2 (en) 2011-10-03 2013-05-14 Invensas Corporation Stub minimization for multi-die wirebond assemblies with parallel windows
KR20140085497A (ko) 2011-10-03 2014-07-07 인벤사스 코포레이션 직교 윈도가 있는 멀티-다이 와이어본드 어셈블리를 위한 스터브 최소화
US8513813B2 (en) 2011-10-03 2013-08-20 Invensas Corporation Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US8659142B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization for wirebond assemblies without windows
US8659139B2 (en) 2011-10-03 2014-02-25 Invensas Corporation Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
JP2013110264A (ja) * 2011-11-21 2013-06-06 Fujitsu Semiconductor Ltd 半導体装置及び半導体装置の製造方法
WO2013084384A1 (ja) * 2011-12-08 2013-06-13 パナソニック株式会社 半導体装置及びその製造方法
US8860222B2 (en) 2011-12-27 2014-10-14 Maxim Integrated Products, Inc. Techniques for wafer-level processing of QFN packages
EP2613349B1 (en) * 2012-01-05 2019-11-20 Nxp B.V. Semiconductor package with improved thermal properties
US9691706B2 (en) 2012-01-23 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip fan out package and methods of forming the same
JP2013197387A (ja) * 2012-03-21 2013-09-30 Elpida Memory Inc 半導体装置
US9006004B2 (en) * 2012-03-23 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Probing chips during package formation
US9613917B2 (en) 2012-03-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package (PoP) device with integrated passive device in a via
US9287249B2 (en) * 2012-04-11 2016-03-15 Panasonic Intellectual Property Management Co., Ltd. Semiconductor device
US8901730B2 (en) 2012-05-03 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices
TWI485826B (zh) * 2012-05-25 2015-05-21 財團法人工業技術研究院 晶片堆疊結構以及晶片堆疊結構的製作方法
JP5607692B2 (ja) * 2012-08-22 2014-10-15 ルネサスエレクトロニクス株式会社 電子装置
US8787034B2 (en) 2012-08-27 2014-07-22 Invensas Corporation Co-support system and microelectronic assembly
US8848391B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support component and microelectronic assembly
US8848392B2 (en) 2012-08-27 2014-09-30 Invensas Corporation Co-support module and microelectronic assembly
US9368477B2 (en) 2012-08-27 2016-06-14 Invensas Corporation Co-support circuit panel and microelectronic packages
US9165887B2 (en) 2012-09-10 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with discrete blocks
US9391041B2 (en) 2012-10-19 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out wafer level package structure
JP6290534B2 (ja) * 2012-12-20 2018-03-07 新光電気工業株式会社 半導体パッケージ及び半導体パッケージの製造方法
US9087779B2 (en) * 2013-01-02 2015-07-21 Maxim Integrated Products, Inc. Multi-die, high current wafer level package
JP6409575B2 (ja) * 2013-01-30 2018-10-24 パナソニック株式会社 積層型半導体装置
US8970023B2 (en) 2013-02-04 2015-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and methods of forming same
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package
USD707332S1 (en) 2013-03-15 2014-06-17 S.P.M. Flow Control, Inc. Seal assembly
US9177925B2 (en) * 2013-04-18 2015-11-03 Fairfchild Semiconductor Corporation Apparatus related to an improved package including a semiconductor die
WO2014175133A1 (ja) * 2013-04-23 2014-10-30 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
CN103268875B (zh) * 2013-05-30 2015-06-03 山东华芯微电子科技有限公司 一种多晶片封装结构
US9070423B2 (en) 2013-06-11 2015-06-30 Invensas Corporation Single package dual channel memory with co-support
US10667410B2 (en) 2013-07-11 2020-05-26 Hsio Technologies, Llc Method of making a fusion bonded circuit structure
KR101548801B1 (ko) * 2013-08-28 2015-08-31 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
US9123555B2 (en) 2013-10-25 2015-09-01 Invensas Corporation Co-support for XFD packaging
US9373527B2 (en) 2013-10-30 2016-06-21 Taiwan Semiconductor Manufacturing Company, Ltd. Chip on package structure and method
US9184128B2 (en) * 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
US9653442B2 (en) 2014-01-17 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and methods of forming same
US10026671B2 (en) * 2014-02-14 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US9935090B2 (en) * 2014-02-14 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9768090B2 (en) 2014-02-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
TWI616979B (zh) * 2014-03-14 2018-03-01 Toshiba Memory Corporation 半導體裝置及其製造方法
JP6259737B2 (ja) * 2014-03-14 2018-01-10 東芝メモリ株式会社 半導体装置及びその製造方法
JP2015195263A (ja) * 2014-03-31 2015-11-05 マイクロン テクノロジー, インク. 半導体装置及びその製造方法
TWI474417B (zh) * 2014-06-16 2015-02-21 恆勁科技股份有限公司 封裝方法
KR20150144416A (ko) * 2014-06-16 2015-12-28 한국전자통신연구원 적층 모듈 패키지 및 그 제조 방법
US9281296B2 (en) 2014-07-31 2016-03-08 Invensas Corporation Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design
US9691437B2 (en) 2014-09-25 2017-06-27 Invensas Corporation Compact microelectronic assembly having reduced spacing between controller and memory packages
WO2016099523A1 (en) * 2014-12-19 2016-06-23 Intel IP Corporation Stacked semiconductor device package with improved interconnect bandwidth
KR102309463B1 (ko) * 2015-01-23 2021-10-07 엘지이노텍 주식회사 시스템 인 패키지 모듈
KR101672622B1 (ko) * 2015-02-09 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
KR101684787B1 (ko) * 2015-02-13 2016-12-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 반도체 패키지 디바이스 및 그 형성 방법
US9564416B2 (en) 2015-02-13 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US9711488B2 (en) * 2015-03-13 2017-07-18 Mediatek Inc. Semiconductor package assembly
US9595482B2 (en) 2015-03-16 2017-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure for die probing
US9484080B1 (en) 2015-11-09 2016-11-01 Invensas Corporation High-bandwidth memory application with controlled impedance loading
DE102016203453A1 (de) * 2016-03-02 2017-09-07 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung eines Halbleiterbauelements und Halbleiterbauelement
KR101787886B1 (ko) * 2016-04-12 2017-10-19 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 이의 제조 방법
US9679613B1 (en) 2016-05-06 2017-06-13 Invensas Corporation TFD I/O partition for high-speed, high-density applications
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10483237B2 (en) 2016-11-11 2019-11-19 Semiconductor Components Industries, Llc Vertically stacked multichip modules
CN106816421B (zh) * 2017-03-22 2019-11-15 中芯长电半导体(江阴)有限公司 集成有功率传输芯片的封装结构的封装方法
US10304800B2 (en) * 2017-06-23 2019-05-28 Taiwan Semiconductor Manufacturing Company Ltd. Packaging with substrates connected by conductive bumps
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
JP2018050077A (ja) * 2017-12-14 2018-03-29 ルネサスエレクトロニクス株式会社 電子装置
JP2019110201A (ja) 2017-12-18 2019-07-04 ルネサスエレクトロニクス株式会社 電子装置および電子機器
CN111788675B (zh) 2018-03-20 2023-11-07 株式会社村田制作所 高频模块
JP2018137474A (ja) * 2018-04-16 2018-08-30 ルネサスエレクトロニクス株式会社 電子装置
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
WO2020100849A1 (ja) 2018-11-12 2020-05-22 株式会社村田製作所 実装型電子部品、および、電子回路モジュール
JP7163224B2 (ja) 2019-03-15 2022-10-31 ルネサスエレクトロニクス株式会社 電子装置
US10985151B2 (en) * 2019-04-19 2021-04-20 Nanya Technology Corporation Semiconductor package and method for preparing the same
US11387177B2 (en) * 2019-06-17 2022-07-12 Taiwan Semiconductor Manufacturing Company Ltd. Package structure and method for forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11362010B2 (en) * 2019-10-16 2022-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out feature
US11587918B2 (en) * 2019-12-17 2023-02-21 Micron Technology, Inc. Semiconductor devices, semiconductor device packages, electronic systems including same, and related methods
KR20210155455A (ko) * 2020-06-16 2021-12-23 삼성전자주식회사 반도체 패키지
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
JP6985477B1 (ja) * 2020-09-25 2021-12-22 アオイ電子株式会社 半導体装置および半導体装置の製造方法
KR102883598B1 (ko) * 2020-10-21 2025-11-07 삼성전자주식회사 반도체 패키지
CN112908869A (zh) * 2021-01-19 2021-06-04 上海先方半导体有限公司 一种封装结构及其制备方法
US11978729B2 (en) * 2021-07-08 2024-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package having warpage control and method of forming the same
JP2023045675A (ja) 2021-09-22 2023-04-03 キオクシア株式会社 半導体装置及び半導体装置の製造方法
FR3132977A1 (fr) * 2022-02-22 2023-08-25 Stmicroelectronics (Grenoble 2) Sas Dispositif électronique
CN115101519A (zh) * 2022-08-29 2022-09-23 盛合晶微半导体(江阴)有限公司 一种三维堆叠的扇出型封装结构及其制备方法
US20240249988A1 (en) * 2023-01-19 2024-07-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

Family Cites Families (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2734684B2 (ja) * 1989-10-03 1998-04-02 松下電器産業株式会社 半導体素子パッケージ
JPH04370958A (ja) * 1991-06-20 1992-12-24 Hitachi Ltd 半導体基板、これを用いた半導体集積回路装置および半導体基板の製造方法
JPH0548001A (ja) * 1991-08-19 1993-02-26 Fujitsu Ltd 半導体集積回路の実装方法
JPH07176684A (ja) 1993-12-17 1995-07-14 Interu Japan Kk 半導体装置
US5751015A (en) * 1995-11-17 1998-05-12 Micron Technology, Inc. Semiconductor reliability test chip
EP0791960A3 (en) * 1996-02-23 1998-02-18 Matsushita Electric Industrial Co., Ltd. Semiconductor devices having protruding contacts and method for making the same
JP3380151B2 (ja) 1997-12-22 2003-02-24 新光電気工業株式会社 多層回路基板
US6137164A (en) * 1998-03-16 2000-10-24 Texas Instruments Incorporated Thin stacked integrated circuit device
JP3648053B2 (ja) * 1998-04-30 2005-05-18 沖電気工業株式会社 半導体装置
GB2338827B (en) * 1998-06-27 2002-12-31 Motorola Gmbh Electronic package assembly
JP3563604B2 (ja) * 1998-07-29 2004-09-08 株式会社東芝 マルチチップ半導体装置及びメモリカード
US6281042B1 (en) * 1998-08-31 2001-08-28 Micron Technology, Inc. Structure and method for a high performance electronic packaging assembly
US6424034B1 (en) 1998-08-31 2002-07-23 Micron Technology, Inc. High performance packaging for microprocessors and DRAM chips which minimizes timing skews
JP3856967B2 (ja) 1998-10-28 2006-12-13 アルゼ株式会社 遊技機
US6175160B1 (en) * 1999-01-08 2001-01-16 Intel Corporation Flip-chip having an on-chip cache memory
US6274937B1 (en) * 1999-02-01 2001-08-14 Micron Technology, Inc. Silicon multi-chip module packaging with integrated passive components and method of making
US7349223B2 (en) * 2000-05-23 2008-03-25 Nanonexus, Inc. Enhanced compliant probe card systems having improved planarity
US6617681B1 (en) * 1999-06-28 2003-09-09 Intel Corporation Interposer and method of making same
JP2001077301A (ja) * 1999-08-24 2001-03-23 Amkor Technology Korea Inc 半導体パッケージ及びその製造方法
US6255899B1 (en) * 1999-09-01 2001-07-03 International Business Machines Corporation Method and apparatus for increasing interchip communications rates
TW473950B (en) * 1999-10-01 2002-01-21 Seiko Epson Corp Semiconductor device and its manufacturing method, manufacturing apparatus, circuit base board and electronic machine
JP2001203318A (ja) * 1999-12-17 2001-07-27 Texas Instr Inc <Ti> 複数のフリップチップを備えた半導体アセンブリ
JP2001177049A (ja) * 1999-12-20 2001-06-29 Toshiba Corp 半導体装置及びicカード
GB0005088D0 (en) * 2000-03-01 2000-04-26 Unilever Plc Composition and method for bleaching laundry fabrics
JP3597754B2 (ja) * 2000-04-24 2004-12-08 Necエレクトロニクス株式会社 半導体装置及びその製造方法
JP2001345418A (ja) 2000-06-02 2001-12-14 Matsushita Electric Ind Co Ltd 両面実装構造体の製造方法及びその両面実装構造体
JP4701506B2 (ja) 2000-09-14 2011-06-15 ソニー株式会社 回路ブロック体の製造方法、配線回路装置の製造方法並びに半導体装置の製造方法
JP2002176137A (ja) * 2000-09-28 2002-06-21 Toshiba Corp 積層型半導体デバイス
US20020074637A1 (en) * 2000-12-19 2002-06-20 Intel Corporation Stacked flip chip assemblies
JP2002221801A (ja) * 2001-01-29 2002-08-09 Hitachi Ltd 配線基板の製造方法
US6673653B2 (en) * 2001-02-23 2004-01-06 Eaglestone Partners I, Llc Wafer-interposer using a ceramic substrate
US20020121707A1 (en) * 2001-02-27 2002-09-05 Chippac, Inc. Super-thin high speed flip chip package
JP2002314031A (ja) 2001-04-13 2002-10-25 Fujitsu Ltd マルチチップモジュール
SG106054A1 (en) * 2001-04-17 2004-09-30 Micron Technology Inc Method and apparatus for package reduction in stacked chip and board assemblies
JP4831885B2 (ja) * 2001-04-27 2011-12-07 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2002343904A (ja) * 2001-05-21 2002-11-29 Matsushita Electric Ind Co Ltd 半導体装置
US7189595B2 (en) * 2001-05-31 2007-03-13 International Business Machines Corporation Method of manufacture of silicon based package and devices manufactured thereby
JP2003007910A (ja) * 2001-06-19 2003-01-10 Matsushita Electric Ind Co Ltd 半導体装置
JP4746770B2 (ja) * 2001-06-19 2011-08-10 ルネサスエレクトロニクス株式会社 半導体装置
JP4122143B2 (ja) * 2001-07-26 2008-07-23 太陽誘電株式会社 半導体装置及びその製造方法
US7176506B2 (en) * 2001-08-28 2007-02-13 Tessera, Inc. High frequency chip packages with connecting elements
US6787916B2 (en) * 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
JP3959264B2 (ja) * 2001-09-29 2007-08-15 株式会社東芝 積層型半導体装置
JP3861669B2 (ja) * 2001-11-22 2006-12-20 ソニー株式会社 マルチチップ回路モジュールの製造方法
JP4044769B2 (ja) * 2002-02-22 2008-02-06 富士通株式会社 半導体装置用基板及びその製造方法及び半導体パッケージ
JP2003273317A (ja) * 2002-03-19 2003-09-26 Nec Electronics Corp 半導体装置及びその製造方法
JP2003318361A (ja) * 2002-04-19 2003-11-07 Fujitsu Ltd 半導体装置及びその製造方法
JP2004039867A (ja) 2002-07-03 2004-02-05 Sony Corp 多層配線回路モジュール及びその製造方法
US7087988B2 (en) * 2002-07-30 2006-08-08 Kabushiki Kaisha Toshiba Semiconductor packaging apparatus
JP2004079756A (ja) 2002-08-16 2004-03-11 Fujitsu Ltd 薄膜多層配線基板、電子部品パッケージ、及び、電子部品パッケージの製造方法
US20040046248A1 (en) * 2002-09-05 2004-03-11 Corning Intellisense Corporation Microsystem packaging and associated methods
US7049691B2 (en) * 2002-10-08 2006-05-23 Chippac, Inc. Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package
AU2003279215A1 (en) * 2002-10-11 2004-05-04 Tessera, Inc. Components, methods and assemblies for multi-chip packages
JP3908146B2 (ja) * 2002-10-28 2007-04-25 シャープ株式会社 半導体装置及び積層型半導体装置
JP3910907B2 (ja) 2002-10-29 2007-04-25 新光電気工業株式会社 キャパシタ素子及びこの製造方法、半導体装置用基板、並びに半導体装置
US6798057B2 (en) * 2002-11-05 2004-09-28 Micron Technology, Inc. Thin stacked ball-grid array package
JPWO2004047167A1 (ja) * 2002-11-21 2006-03-23 日本電気株式会社 半導体装置、配線基板および配線基板製造方法
US20040155358A1 (en) * 2003-02-07 2004-08-12 Toshitsune Iijima First and second level packaging assemblies and method of assembling package
JP3917946B2 (ja) * 2003-03-11 2007-05-23 富士通株式会社 積層型半導体装置
JP2004288815A (ja) * 2003-03-20 2004-10-14 Seiko Epson Corp 半導体装置及びその製造方法
JP2004296963A (ja) * 2003-03-28 2004-10-21 Semiconductor Energy Lab Co Ltd 半導体装置及び半導体装置の作製方法
JP4419049B2 (ja) * 2003-04-21 2010-02-24 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
WO2004102653A1 (ja) * 2003-05-15 2004-11-25 Shinko Electric Industries Co., Ltd. 半導体装置およびインターポーザー
TWI245381B (en) * 2003-08-14 2005-12-11 Via Tech Inc Electrical package and process thereof
US6864165B1 (en) * 2003-09-15 2005-03-08 International Business Machines Corporation Method of fabricating integrated electronic chip with an interconnect device
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
JP4865197B2 (ja) * 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10991673B2 (en) 2018-01-04 2021-04-27 Kabushiki Kaisha Toshiba Electronic device
US11791311B2 (en) 2018-01-04 2023-10-17 Nagase & Co., Ltd. Electronic device
US12249593B2 (en) 2018-01-04 2025-03-11 Nagase & Co., Ltd. Electronic device
KR20200031322A (ko) 2018-09-14 2020-03-24 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
US10820456B2 (en) 2018-09-14 2020-10-27 Samsung EIectro-Mechanics Co., Ltd. Electronic component module and manufacturing method thereof
US11337346B2 (en) 2018-09-14 2022-05-17 Samsung Electro-Mechanics Co., Ltd. Electronic component module and manufacturing method thereof

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US20080265434A1 (en) 2008-10-30
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US7795721B2 (en) 2010-09-14
US20190229104A1 (en) 2019-07-25
US20120248620A1 (en) 2012-10-04
US20150041978A1 (en) 2015-02-12
US8890305B2 (en) 2014-11-18
US8193033B2 (en) 2012-06-05
US20160204092A1 (en) 2016-07-14

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