CN102122675B - 光电装置及其制造方法 - Google Patents
光电装置及其制造方法 Download PDFInfo
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- CN102122675B CN102122675B CN2010102295095A CN201010229509A CN102122675B CN 102122675 B CN102122675 B CN 102122675B CN 2010102295095 A CN2010102295095 A CN 2010102295095A CN 201010229509 A CN201010229509 A CN 201010229509A CN 102122675 B CN102122675 B CN 102122675B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 claims abstract description 147
- 239000000758 substrate Substances 0.000 claims abstract description 142
- 239000000463 material Substances 0.000 claims abstract description 114
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 82
- 239000010703 silicon Substances 0.000 claims abstract description 82
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 80
- 239000003989 dielectric material Substances 0.000 claims abstract description 75
- 150000001875 compounds Chemical class 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims description 67
- 230000002950 deficient Effects 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 229910052735 hafnium Inorganic materials 0.000 claims description 5
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910052726 zirconium Inorganic materials 0.000 claims description 4
- 235000012431 wafers Nutrition 0.000 abstract description 99
- 230000009467 reduction Effects 0.000 abstract description 4
- 229910002601 GaN Inorganic materials 0.000 description 47
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 38
- 238000005516 engineering process Methods 0.000 description 34
- 239000010408 film Substances 0.000 description 27
- 239000010410 layer Substances 0.000 description 27
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 20
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 16
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 12
- 230000007547 defect Effects 0.000 description 12
- 238000000151 deposition Methods 0.000 description 12
- 230000008021 deposition Effects 0.000 description 10
- 229910010271 silicon carbide Inorganic materials 0.000 description 10
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 9
- 229910052594 sapphire Inorganic materials 0.000 description 9
- 239000010980 sapphire Substances 0.000 description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 8
- 239000000203 mixture Substances 0.000 description 8
- 229910017083 AlN Inorganic materials 0.000 description 7
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000013078 crystal Substances 0.000 description 7
- 238000002425 crystallisation Methods 0.000 description 7
- 230000008025 crystallization Effects 0.000 description 7
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 6
- YZCKVEUIGOORGS-NJFSPNSNSA-N Tritium Chemical compound [3H] YZCKVEUIGOORGS-NJFSPNSNSA-N 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 6
- 229910002704 AlGaN Inorganic materials 0.000 description 5
- 229910000070 arsenic hydride Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000001257 hydrogen Substances 0.000 description 5
- 229910052739 hydrogen Inorganic materials 0.000 description 5
- 230000035882 stress Effects 0.000 description 5
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 5
- 229910021529 ammonia Inorganic materials 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000013011 mating Effects 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- -1 InN Inorganic materials 0.000 description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 238000010561 standard procedure Methods 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011701 zinc Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000000875 corresponding effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000008393 encapsulating agent Substances 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000004992 fission Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 238000002156 mixing Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 230000001902 propagating effect Effects 0.000 description 2
- 150000003376 silicon Chemical class 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000002269 spontaneous effect Effects 0.000 description 2
- 238000005496 tempering Methods 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 239000005864 Sulphur Substances 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000011066 ex-situ storage Methods 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical class [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical group [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 229910052714 tellurium Inorganic materials 0.000 description 1
- PORWMNRCUJJQNO-UHFFFAOYSA-N tellurium atom Chemical compound [Te] PORWMNRCUJJQNO-UHFFFAOYSA-N 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
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- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
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- H01L21/02367—Substrates
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- H01L21/02387—Group 13/15 materials
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- H01L21/02538—Group 13/15 materials
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
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- H01L21/02538—Group 13/15 materials
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- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H01L21/185—Joining of semiconductor bodies for junction formation
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/861—Diodes
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- H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
- H01L31/1852—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising a growth substrate not being an AIIIBV compound
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- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
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Abstract
本发明提供一种光电装置及其制造方法,该光电装置包括一基板以及具有露出该基板的一部分的两个或两个以上的开口的一介电材料,所述两个或两个以上的开口分别具有至少为1的一深宽比。包括晶格不相称于该基板的一化合物半导体材料的一底部二极管材料占据了所述两个或两个以上的开口并于所述两个或两个以上的开口之上接合以形成一底部二极管区域。上述装置更包括一顶部二极管材料以及位于该顶部二极管材料与该底部二极管材料之间的一有源二极管区。本发明借由于高品质、大区域、低成本的硅晶片上制作太阳能电池、发光二极管、共振穿隧二极管、半导体激光与其他化合物半导体装置,借以降低成本。
Description
技术领域
本发明涉及由位于硅晶片之上由化合物半导体(compoundsemiconductors)或其他的晶格不相称半导体材料(lattice-mismatchedsemiconductors)所制成的半导体二极管及其制造方法,且尤其涉及如发光二极管(light emitting diode)、激光、光电压(photovoltaics)及其他光电子(optoelectronic)用途的光电应用。
背景技术
于下文中将主张2007年4月9日申请的第60/922,533号美国临时专利申请案的优先权的第60/922,533号美国专利申请案(申请日为2008年4月9号)以提及方式并入于本文中。
本节中提供了背景资料并介绍了于下文中所描述和/或所主张的权利范围所相关的不同观点的相关信息。这些背景资料的陈述并非承认其为公知技术。
大部分的芯片制作皆应用了具有高品质、大区域、低成本等优点的硅晶片的硅制造工艺。采用如砷化镓(gallium arsenide)与磷化铟(indium phosphide)等化合物半导体的装置的商业制作则通常无法具有前述的硅制造工艺的优点。其通常于由如蓝宝石(sapphire)、锗(germanium)、砷化镓(gallium arsenide)或碳化硅(silicon carbide)等材料所制成的小且昂贵的晶片上进行如发光二极管(light emitting diode,LED)、多结太阳能电池(multi-junction solar cell)及其他化合物半导体装置的制作。
于便宜的基板上制造半导体化合物装置的挑战牵涉到极大的经济因素。由于可发射与检测光线,化合物半导体于通信基础建设中为重要的元件。其为适用于如透过光纤传输信号的激光中、用于接受上述信号的感测器、移动电话内的放大器(amplifier)、移动电话基地台内的放大器、以及与传输与接收微波信号的电路等应用中的材料。
发光二极管通常由设置于蓝宝石(sapphire)或碳化硅(silicon carbide)材质的晶片上的多个氮化镓(gallium nitride)膜层所组成。这些独特基板造成了发光二极管的高成本。直径4英寸的蓝宝石晶片的通常价值约130美元,而两英寸的碳化硅晶片则价值约2000美元。作为比较之用,具有四倍于四英寸晶片的使用面积或16倍于两英寸晶片的使用面积的八英寸硅晶片的成本则通常低于100美元。
高效多结太阳能电池(high-efficiency multi-junction solar cells)通常包括设置于锗晶片上的如锗、砷化镓及磷化铟的膜层。于发光二极管所用的晶片中,所使用的锗晶片通常较硅晶片为较小且明显为较昂贵。
于硅晶片上制作化合物半导体装置的能力有助于加速其于多种主要工业中的市场成长。
目前限制了半导体晶片上的化合物半导体装置的实际制作的两种主要技术障碍分别为晶格常数的不匹配(mismatch of lattice constants)与热膨胀系数的不匹配(mismatch ofthermal expansion coefficients)的情形。
晶格不匹配:于结晶物中,原子依照规则性周期阵列物而设置(即公知的晶格)。介于原子之间的距离,即公知的晶格常数,通常约为数埃(1埃=10-10米)。硅具有较化合物半导体为小的晶格常数。当于硅上成长化合物半导体时,于界面处出现了如公知的错配差排(misfit dislocation)的结晶瑕疵(crystallineimperfections)。如此的错配差排造成了如公知贯穿差排(threading dislocation)的其他结晶缺陷,其自界面处向上传播。贯穿差排缩减了如激光、太阳能电池、发光二极管等化合物半导体装置的表现与可靠度。
热收缩的不匹配:化合物半导体通常于如超过1000℃的高温下成长。当晶片冷却之后,化合物半导体的薄膜较硅晶片的收缩程度为大。其结果为,晶片将弯曲成为内凹状,且施加应力与最终地使得薄膜产生破裂。
直到最近,发展出了包括下述三种方法的于硅基板上成长高品质的化合物半导体的最稳固的现有技术,例如渐变缓冲层(graded buffer layers)法、晶片连结(wafer bonding)法或于岛状物上的选择性成长(selective growth onmesas)法等技术。然而,上述技术则尚未达成商业上的成功。
于渐变缓冲层法中,材料的组成由大体纯硅(pure silicon)逐渐地变化成化合物半导体。由于晶格常数也逐渐地随着变化,故晶格缺陷较少形成于界面处。不幸地,这些渐变缓冲层具有相对厚的厚度(每4%的晶格不相称情形具有约10微米)。如此厚的缓冲层增加了工艺成本及破裂的可能性。
晶片连结法则牵涉到于昂贵基板上成长一装置、接着剥离上述装置并将的接合(bonding)于硅晶片上。上述方法并不考虑采用当今硅制造工艺以作为降低成本的方法。此外,接合通常需要高于300℃的温度。当材料冷却之后,由于相较硅晶片具有更大的收缩情形,故化合物半导体可能破裂。
岛状物上的选择性成长法则利用了特定差排的迁移率。此方法于小区域(长度约为10-100微米)内沉积化合物半导体材料,进而形成了一短沟道,其可供位于此处的移动差排(mobile dislocation)可滑动至此区域的边缘并自此装置处而移除。然而,借由上述技术所形成的结构通常具有高密度的贯穿差排(高于1亿/每平方公分)。上述技术并无法移除固定差排(immobiledislocation),于当晶格不匹配超过了2%时其将成为占大多数。
近年来已发展出了深宽比捕捉(aspect ratio trapping)技术(由Park等人于APL 90,0521113(2007)所揭示,于此以提及方式并入于本文中),其可于硅晶片上沉积高品质的化合物半导体材料、锗或其他的晶格不匹配材料。图1显示了此深宽比捕捉技术的原理。于一硅晶片10之上沉积如二氧化硅(SiO2)或氮化硅(SiNx)的一介电材料20的薄膜层。本领域技术人员也可选择如SiOxNy及如铪(Hf)与锆(Zr)的硅化物或氧化物等的多种介电材料。
于上述介电材料内蚀刻形成一沟槽,接着沉积如锗或化合物半导体的晶格不匹配半导体30于沟槽内。如虚线所表示的贯穿差排40将向上传播,其通常依照相对于界面呈大体45度的一角度向上传播。贯穿差排40并不会朝沟槽长度方向而向下传播,其依照垂直于结晶的成长晶面(faceted growth face)的一方向而传播,这些晶面引导了差排朝向侧壁,并于这些侧壁处终止。位于沟槽内其侧壁捕捉了贯穿差排的区域可称之为“捕捉区”50。晶格不相称半导体30之上方区域,且高于捕捉区50的一区域则为一相对无缺陷区60。
深宽比捕捉技术基于下述原因而解决了起因于热膨胀系数的不匹配所造成的破裂问题:(1)由于外延膜层为薄,故应力为小;(2)由于深宽比捕捉开口的尺寸为小,故材料可为弹性地调和起因于热膨胀不匹配所造成的应力;以及(3)较半导体材料为佳的二氧化硅基座可产生形变以调和上述应力。
请继续参照图2,显示了采用深宽比捕捉技术于硅晶片上所形成的连续的高品质III-V族半导体或其他晶格不匹配材料的高品质薄膜。上述技术相似于如图1所示的技术,除了持续地成长晶格不匹配半导体直到相邻的沟槽内的成长结合成为了一单一连续膜层70。其他的缺陷,即所谓的接合缺陷80,则形成于相接合成长处的部分的接合区域。然而,此缺陷密度仍远少于直接于硅晶片上成长晶格不匹配半导体的缺陷密度。
发明内容
为克服上述现有技术的缺陷,本发明提供了一种光电装置及其制造方法。
依据一实施例,本发明提供了一种光电装置,包括:
一基板;一介电材料,包括露出该基板的一部分的两个或两个以上的开口,所述两个或两个以上的开口分别具有至少为1的一深宽比;一底部二极管材料,包括晶格不相称于该基板的一化合物半导体材料,且其中该化合物半导体材料占据了所述两个或两个以上的开口并于所述两个或两个以上的开口之上接合成一底二极管区域;一顶部二极管材料;以及一有源二极管区,位于该顶部二极管材料与该底部二极管材料之间。
依据另一实施例,本发明提供了一种光电装置,包括:
一基板;以及包括一第一区,邻近该基板的一第一顶面、一第二区,邻近该第一区、及一有源区,介于该第一区与该第二区之间的一光电二极管,其中该第二区包括邻近于该有源区的一表面,该表面大体平行于该基板的该顶面;以及该第二区包括与该有源区相分隔的至少一缺陷捕捉区,该缺陷捕捉区包括延伸自该基板的该顶面的一表面。
依据又一实施例,本发明提供了一种光电装置的制造方法,包括:
沉积一第一介电材料层于一基板之上;图案化该第一介电材料层以于其内形成两个或两个以上的开口,已露出该基板的该表面的部分,所述两个或两个以上的开口具有至少为1的深宽比;借由成长晶格不相称于该基板的一化合物半导体材料于所述两个或两个以上的开口内,使得该化合物半导体材料填满所述两个或两个以上的开口并于所述两个或两个以上开口之上接合成一连续膜层,以形成一底二极管区;形成一有源二极管区于该底部二极管区之上;以及形成一顶二极管区于该有源二极管区之上。
本发明借由于高品质、大区域、低成本的硅晶片上而非于又小又较贵的基板上制作太阳能电池、发光二极管、共振穿隧二极管、半导体激光与其他化合物半导体装置,借以降低太阳能电池、发光二极管、共振穿隧二极管、半导体激光与其他化合物半导体装置的成本。
为让本发明的上述目的、特征及优点能更明显易懂,下文特举一较佳实施例,并配合附图,作详细说明如下:
附图说明
图1显示了深宽比捕捉技术的原理,以及于硅晶片上沉积高品质化合物半导体或其他的晶格不相称半导体的方法;
图2显示了借由深宽比捕捉技术以于硅晶片上成长高品质的化合物半导体或其他晶格不相称半导体的薄膜的技术;
图3显示了半导体二极管的一结构;
图4显示了依据本发明一第一实施例的一半导体二极管;
图5与图6显示了用于制造第一实施例的半导体二极管的连续阶段;
图7为一流程图,显示了依据本发明的第一实施例的一制造方法;
图8、图9、图10显示了如图7所示的制造方法的变化;
图11显示了依据本发明的一第二实施例的一施体晶片;
图12为一流程图,显示依据本发明的第二实施例的一施体晶片的一制造方法;
图13与图14显示了图12内的制造方法的变化;
图15-图17显示了于利用一施体晶片以形成一氮化镓基板的一方法中的不同步骤;
图18为一流程图,显示了如图15-图17所示的方法;
图19-图20显示了如图18所示方法的变化情形;
图21显示了可能发生于外延成长膜层内的破裂情形;
图22显示了借由深宽比捕捉而降低位于成长于一硅基板上的半导体材料的一结合膜层内的热应力的方法;
图23为一流程图,显示了如图22内所示方法;
图23A显示了一发光二极管制造工艺内的中间情形;
图23B显示了依据本发明另一实施例的一发光二极管的二极管结构;
图24-图28显示了依据本发明的一第三实施例内包括多个二极管装置的一单芯片的制造步骤;
图29显示了依据本发明的第三实施例所制造出的一结构;以及
图30A及图30B为一流程图,显示了依据本发明的第三实施例的制造方法。
其中,附图标记说明如下:
10~硅晶片;
20~介电材料;
30~晶格不匹配半导体;
40~贯穿差排;
50~捕捉区;
60~无缺陷区;
70~单一连续膜层;
80~接合缺陷;
101、1000~基板;
105、106~导电接触物;
1010~介电材料;
1020~沟槽;
102、1030、1170、1210、1250、1502~底二极管区;
1040~贯穿差排;
1050~捕捉区;
103、1060、1180、1220、1260、1512~有源二极管区;
104、1070、1190、1230、1270、1514~顶二极管区;
1080~握持晶片;
1090~第一电性接触物;
1100~第二电性接触物;
1110~半导体材料;
1120~分裂平面;
1130~握持基板;
1140~破裂;
1150~凹洞;
1160~沟槽;
1195、1240、1280~二极管装置;
1200~第二介电材料;
1290~接触物;
1300~底电性接触物;
1500~硅基板;
1504~缺陷捕捉区;
1506~AlGaN阻挡区;
1508~InGaN发射区;
1510~AlGaN阻挡区。
具体实施方式
本发明的实施例提供了适用于半导体二极管的新颖与有用的结构,其采用由深宽比捕捉(Aspect Ratio Trapping)技术于硅晶片上沉积的化合物半导体或其他晶格的不匹配半导体所形成的接合薄膜(coalesce film)。半导体二极管为太阳能电池(solar cells)、发光二极管(light-emitting diodes)、共振穿隧二极管(resonant tunneling diodes)、半导体激光(semiconductor lasers)与其他装置的基础构件。
本发明的目的包括借由于高品质、大区域、低成本的硅晶片上而非于又小又较贵的基板上制作太阳能电池、发光二极管、共振穿隧二极管、半导体激光与其他化合物半导体装置,借以降低太阳能电池、发光二极管、共振穿隧二极管、半导体激光与其他化合物半导体装置的成本。
本发明的其他目的则为于基板会劣化如发光二极管的表现的情形下,自用于装置的一半导体二极管处移除了硅晶片基板。
本发明的其他目的则提供了制造氮化镓基板的一种较经济方法,例如为于如多晶硅氮化铝的一热匹配基板上形成的氮化镓的高品质薄膜。
本发明的其他目的则提供了用于形成氮化镓薄膜的较便宜的施体晶片(donor wafer),所形成的氮化镓薄膜可被转移至如氮化铝基板的其他基板处。
本发明的其他目的则可缓和借由深宽比捕捉形成的接合膜层内的由热引起的破裂情形。
本发明的其他目的提供了制作包括由不同半导体材料所制成的数个二极管装置的单芯片的较经济方法。
于以下描述中,通常采用单一的二极管方式以讨论示范的二极管结构,半导体工程师及其他本领域技术人员当能理解于多数应用中需使用多个二极管,且其通常整合于单一芯片之上。
一般来说,于下文中讨论的半导体二极管具有如图3所示的一般结构,其包括:一基板101、一底二极管区102、一有源二极管区103、一顶二极管区104、位于装置的顶部的导电接触物105以及位于装置底部的一导电接触物106。上述二极管区102、103与104内则分别由多重膜层所制成。
底二极管区102与顶二极管区104具有相反的掺杂类型(doping types)。举例来说,当底二极管区102显著地为n型掺杂时(具有如磷、砷或锑的电子施体),而顶二极管区104将显著地为p型掺杂(具有如硼或铝的电子受体),反之亦然。于底二极管区102与顶二极管104内的重度掺杂形成了适用于电流进入与离开装置的低电阻值沟道。此顶部区与底部区的一般掺杂程度约介于1017-1020cm-3。而有源区的一般掺杂程度则低于1017cm-3。值得注意的是,为了描述方便而采用了“顶(top)”与“底(bottom)”以指定区域,而于某些情况中顶区可位于底区之上。举例来说,考虑到形成于基板上的二极管,其具有高于其底部区的一顶部区。当此二极管经倒装芯片接合(flip-chip bonded)于一握持晶片后并于移除上述基板之后,上述用于检视二极管的情形通常也随之相反。于此例中,顶区通常将视为位于底区的下方。
基底101通常为一硅晶片,虽然于不同实施例中,包括蓝宝石与碳化硅的其他基板也适用。至少于基板101的部分中通常具有相同的掺杂种类(为n型或p型),而底二极管区102有助于底二极管区102与基板101之间的良好电性接触关系。
有源二极管区103的详细结构可依照包括期望应用的多种参数而决定,于一情形中,有源二极管区103由顶二极管区102与底二极管区104的结(junction)所形成。于此情形中,较佳地改变接近结的顶部区与底部区的掺杂浓度。于发光二极管(LED)内,有源区103则可包括经掺杂的膜层与可使得电子与空穴再结合并产生光子的未经掺杂量子阱(undoped quantum wells)的多个膜层。于太阳能电池的另一范例中,有源二极管区103可包括适度的n型掺杂或适度的p型掺杂的半导体材料,以吸收入射光子并产生电子-空穴对。
对于本领域技术人员而言,形成二极管区的材料为公知的。典型的有用半导体材料为:如硅、碳或锗的IV族材料,或其合金,如碳化硅或硅锗;II-VI族化合物(包括二元、三元与四元形态),例如由锌、镁、铍或镉的II族材料与如碲、硒或硫的VI族材料所形成的化合物,例如为ZnSe、ZnSTe或ZnMgSTe;以及III-V族化合物(包括二元、三元与四元形态),如由如铟、铝或镓的III族材料与如砷、磷、锑或氮的V族材料所组成的化合物,例如InP、GaAs、GaN、InAlAs、AlGaN、InAlGaAs等。本领域技术人员可以了解,可参照如能隙、晶格常数、掺质程度等期望条件而适度选择与处理这些材料。
图4显示了一半导体二极管的实施例。此二极管的结构适用于其内基板将劣化表现的装置。于一发光二极管中,其包括如一硅基板的会吸收装置内所产生的光线。于如图4所示的实施例中,则可移除此硅基板。
图5显示了制造过程中的初步阶段的结果。基础结构为如硅晶片的一基板1000,其表面较佳地具有(111)结晶方向,虽然也可使用其他方向,例如可选择(100)的其他结晶方向。基板1000可依照二极管基装置(diode-baseddevice)的形态而经过n型掺杂或p型掺杂。第一步骤为借由化学气相沉积或其他适当技术沉积如二氧化硅(SiO2)或氮化硅(SiNx)的一层介电材料于硅晶片1000之上。于来自介电层的光线反射会形成问题的装置中,则较佳地使用氮化硅,基由其折射率较为接近于常用的半导体材料。介电层的厚度通常为200-400纳米,但其可为更厚或更薄。
接着于介电材料1010的膜层内图案化形成用于深宽比捕捉的开口,例如具有大体垂直侧壁的沟槽1020,进而于沟槽内露出了硅晶片1000的表面。借由公知光刻技术或借由反应性离子蚀刻的两种示范方法可图案化形成一沟槽1020。为本领域技术人员所了解,基于此处的揭示情形,沟槽可为另一形状的开口,例如为一孔洞、一凹口或环状物。沟槽1020的宽度可相同或少于介电材料的厚度。如此条件是基于深宽比捕捉技术的原理,即沟槽1020的高度与沟槽1020的宽度的比例可大体大于或等于1以捕捉贯穿差排。关于上述技术的细节则揭示于申请中的第11/436,198号US专利申请案于第11/852,078号US专利申请案中,在此以提及方式将的并入于本文中。以及揭示于Park等人于Appl.Phys.Lett.90,052113(2007)的文献中,在此以提及方式将之并入于本文中。
于某些范例中,较佳地洁净于沟槽1020的底部的硅基板1000的表面,以准备用于底二极管区的外延成长。一种适用于洁净程序的范例则包括氧气等离子体蚀刻,请参照Park等人于Appl.Phys.Lett.90,052113(2007)的文献内的揭示。
图6显示了后续几个步骤的结果。首先成长底二极管区1030。用于底二极管区1030的半导体材料则依照元件形态而定。当用于太阳能电池时,底二极管区1030可为如InGaP。而当用于发光二极管时,底二极管区1030可为如GaN。也可使得底二极管区采用包括化合物半导体材料的其他多种半导体材料,其具有用于如激光或共振穿隧二极管的特性的有用特性。半导体材料的范例则如前所述。
于本发明,可以于外延成长时临场地(in-situ)掺杂或借由一离子注入而离场地(ex-situ)掺杂底二极管区1030(较佳地掺杂底二极管区、有源二极管区与顶二极管区,且可于外延成长时临场地掺杂的或借由离子注入而离场地掺杂之)。
于沟槽1020内的底部二极管区1030可称为捕捉区1050,由于其捕捉了如贯穿差排1040的差排,贯穿差排1040产生于底二极管区1030与基板1000间的界面且向上朝向侧壁传播。图6内采用虚线显示了贯穿差排1040。位于捕捉区1050上方的部分底二极管区1030则相对没有缺陷。如此的低缺陷区域使得可于高品质、大区域、低成本的硅晶片上制造出高品质化合物半导体装置。对于某些材料而言,例如GaN、InN、AlN或上述材料的三元或四元组成物,差排密度需少于或等于108/cm2以用于装置应用。对于如GaAs与InP的其他材料,通常需要更低的差排密度以用于装置,例如少于或等于106/cm2。
继续成长此底二极管区1030直到(a)材料溢出于沟槽以及(b)来自于相邻沟槽的此材料接合成了一单一连续薄膜。通常较佳地可于进一步的制作中借由化学机械研磨程序或依其他适当技术以平坦化底二极管区1030。后续步骤则为沉积有源二极管区1060以及底二极管区1070。于大多的实施例中,有源二极管区1060与顶二极管区1070具有相同或相似的晶格常数,此晶格常数相同于底二极管区1030。
图4显示了最终步骤的结果。接合一握持基板1080至顶二极管区1070。于部分实施例中,较佳地平坦化顶部二极管1070以附着一高品质接合物至握持基板1080。于其他实施例中,则较佳地包括位于顶二极管区1070与握持晶片1080间的一中间层以改善附着情形,最小化热不匹配或相似特性。握持基板1080可为一发光二极管封装固定物的一部分。接合技术为公知技术,包括倒装芯片接合,其发光二极管的顶部连结于发光二极管封装物的一表面。握持基板1080可为导电的,或其可包含导电元件以作为用于顶部二极管区1070的接触物。接着借由如研磨、化学回蚀刻、激光剥离或上述方法的组合标准技术以移除硅基板1000。
最后,于底二极管区1030上形成一第一导电接触物1090,以及于握持基板1080处形成一第二导电接触物1100。于不同实施例中,导电接触物的材料可为如铜、银或铝的导电金属的条状物,或为如氧化铟锡的相对透明导电氧化物的膜层。于发光二极管的应用中,位于底部的导电接触物1100较佳地为如银的一高反射性导电材料,其可反射内部产生的光线并使的自另一表面离开发光二极管。
熟悉半导体二极管制作技术的技术人员可知悉许多材料与方法可形成导电接触物。图4中仅示了用于形成第一导电接触物1090的一种方案,借由移除介电层1010以露出底二极管区1030。在此,介电材料1010借由如蚀刻的标准技术移除。于一发光二极管中,如图4所示的捕捉区1050可有效地粗糙化其表面,以降低光线的内部反射,以使得捕捉区1050的尺寸与间隔为正确的。
以下为依据本发明的实施例的适用于形成底、有源与顶二极管区的工艺参数的范例。首先,形成基板与图案化的介电层。采用依据本发明的下述实施例的示范性的工艺参数以形成底、有源与顶二极管区,作为GaAs或AlGaAs基的二极管。
(A)底部二极管区(如1030)(如100-500nm厚的GaAs膜层)
压力:0.1atm
前驱物:稀释于氢气中的三甲基镓(trimethylgallium,TMG)与20%的砷化氢(arsine AsH3),
温度:720℃
N型:掺杂有硅
(B)有源二极管区(如1060)(如用于载流子限制的15nm厚的AlGaAs膜层)
压力:0.1atm
前驱物:稀释于氢气中的三甲基镓(trimethylgallium,TMG)、三甲基铝(trimethylaluminium,TMA)与20%的砷化氢(arsineAsH3)
温度:850℃
N型:掺杂有硅
用于发光的GaAs量子阱(10nm厚)
压力:0.1atm
前驱物:稀释于氢气中的三甲基镓(trimethylgallium,TMG)与20%的砷化氢(arsine AsH3)
温度:720℃
未经掺杂
用于载流子限制的AlGaAs层(15nm厚)
压力:0.1atm
前驱物:稀释于氢气中的三甲基镓(trimethylgallium,TMG)、三甲基铝(trimethylaluminium,TMA)与20%的砷化氢(arsine AsH3)
温度:850℃
P型:掺杂有锌
(C)顶二极管区(如1070)(如100-500nm厚的GaAs膜层)
压力:0.1atm
前驱物:稀释于氢气中的三甲基镓(trimethylgallium,TMG)与20%的砷化氢(arsine AsH3)
温度:720℃
P型:掺杂有锌
依据本发明的第一实施例的用于GaN与InGaN基二极管的底、有源与顶二极管的示范性的预知工艺步骤的成长条件(如化学气相沉积),如下:
(A)底二极管区(如1030)
GaN低温缓冲物(如30nm厚)
压力:100Torr
前驱物:稀释于氢气中的三甲基镓(trimethylgallium,TMG)与氨气(NH3)温度:530℃
N型:掺杂有硅
GaN高温缓冲物(如500nm厚)
压力:100Torr
前驱物:稀释于氢气中的三甲基镓(trimethylgallium,TMG)与氨气(NH3)
温度:1030℃
N型:掺杂有硅
(B)有源二极管区(如1060)
用于发光的InGaN量子阱层(如2nm厚)
压力:100Torr
前驱物:稀释于氢气中的三甲基镓(trimethylgallium,TMG)、三甲基铝(trimethyindium,TMI)、氨气
温度:740℃
未经掺杂
用于载流子限制的GaN阻挡层(如15nm厚)
压力:100Torr
前驱物:稀释于氢气中的三甲基镓(trimethylgallium,TMG)、NH3
温度:860℃
N型,掺杂有硅
(C)顶二极管区(如1070):GaN的p-接触层(如100nm厚)
压力:100Torr
前驱物:稀释于氢气中的三甲基镓(trimethylgallium,TMG)与氨气
温度:950℃
P型:掺杂有镁
如图4所示的包括了位于硅晶片之上的半导体二极管由化合物半导体或其他晶格不匹配材料的第一实施例中,包括了下述元件:一底二极管区1030、一有源二极管区1060、一顶二极管区1070、一握持基板1080、一第一导电接触物1090、一第二导电接触物1100与一捕捉区1050,于其处可终止贯穿差排。
上述底二极管区1030、有源二极管区1060与顶二极管区1070可具有低缺陷密度(通常少于或等于5x 107/每平方公分),其结果为可借由深宽比捕捉而成长底二极管区1030而成为一接合膜层(coalesced film)。
请参照图7,显示了依据上述第一实施例的装置的制造方法。此方法包括:沉积一介电材料1010的膜层于一硅晶片1000的表面;形成沟槽1020于介电材料1010的膜层内,以露出硅晶片1000的表面,各沟槽1020具有大体垂直侧壁,而各沟槽1020的高与宽的比例可大于或等于1;成长一半导体材料以形成一底二极管区1030,其填满了沟槽1020并接合成一单一连续薄膜;成长一半导体材料于底二极管区1030上,以形成一有源二极管区1060;成长一半导体材料于有源二极管区1060上以形成一顶二极管区1070;结合一握持基板1080与顶部二极管区1070;移除硅基板1000;移除介电材料1010,以形成一第一导电接触物1090于底二极管区1030的表面上;以及形成一第二导电接触物1100于握持基板1080的表面上。
图8则总结了如图7所示方法的一变化情形,其中于沉积底二极管区之前,洁净了于沟槽的底部的硅晶片的表面。图9则总结了另一变化情形,其中于成长有源二极管区之前,先平坦化了底二极管区的表面。图10则总结了另一变化情形,其中于结合顶二极管区与握持基板之前,先平坦化了顶二极管区的表面。
其他实施例中则允许了采用由深宽比捕捉以形成接合膜层以形成氮化镓基板。于本文中,例如于发光二极管工业中,“氮化镓基板”的描述指如公知的成长或结合于由非氮化镓材质所形成的一基板上的一氮化镓薄膜。发光二极管的制作通常自材料供应商处购入氮化镓基板,并接着沉积额外的氮化镓膜层及其他的材料,以制作发光二极管。典型的氮化镓基板包括了沉积于一蓝宝石或碳化硅基板上的一氮化镓膜层。目前使用氮化镓基板的世界性市场约每年300万美元。
材料供应商通常沉积氮化镓于氧化铝(A12O3)之上,由于此两种材料具有一适当且良好的晶格匹配情形。然而,氮化镓与氧化铝具有不同热膨胀系数。当发光二极管制造商于加热氮化镓/氧化铝结构以沉积其他膜层时,上述的热膨胀系数差异将造成了其结构的弯曲(bowing)。如此的弯曲造成了氧化铝晶片的部分没有接触到支撑座(suspector),即位于沉积腔体内的基板加热器。其结果为,氧化铝晶片的温度随着其位置而改变。不均匀的氧化铝晶片温度造成了膜层的组成与厚度的变化。其实际后果为商造商对于最终得到的发光二极管的发射波长的不易控制情形。
目前见有一种可解决或至少改善上述问题的氮化镓基板的制造技术。此技术的出现使得可取得来自于一施体晶片(donor wafer)的一氮化镓薄膜,并将的结合于具有一热膨胀系数相似于氮化镓的一氧化铝基板。施体晶片通常为具有单晶氮化镓的一晶片。公知方法用于自施体晶片取得氮化镓薄膜涉及离子注入与分离。制造商注入氢离子进入施体晶片,以制造出一分裂平面(cleave plane),接着分割施体晶片借由回火的或借由施加机械压力。上述技术使得其可能分离多重薄膜自一施体晶片处。
图11显示了一第二实施例,其提供了一新颖的施体晶片,适用于较单晶氮化镓的一施体晶片为低成本的制造。此方法起使于采用如具有(111)结晶方向的硅晶片的一基板1000。然而,于部分实施例中,也可采用如(100)的结晶方向的其他方向。基板1000可经过n掺杂或p掺杂。于基板1000之上沉积有介电材料1010的膜层。接着,形成具有大体垂直侧壁的沟槽于介电材料1010的膜层内,进而露出硅晶片1010的表面。于如图11所示的制造阶段中,这些沟槽大体为下述的半导体材料1100所填满。如前所述,为了促进贯穿差排的捕捉,各沟槽的宽度需少于或等于介电材料的厚度。也可借由前述技术而选择性地洁净位于沟槽底部内的硅基板1000的表面。
次一步骤为成长半导体材料1110(例如氮化镓)的一膜层直至此材料溢出于沟槽,而来自于相邻沟槽的此材料接合成了一单一连续薄膜。半导体材料的实施情形则如前所述。半导体材料1110填入于沟槽内的该部作为缺陷捕捉区1050,其捕捉了贯穿差排1040。高于捕捉区1050的半导体材料1110于成长时大体不具有贯穿差排。然而于其成长时位于相邻沟槽接合处可能于部分的位置处形成有接合缺陷,但是其接合缺陷的密度极低(通常少于或等于5x107/cm2)以使得此结构适用于实际制作。
图11显示了一新颖施体晶片,其可自膜层处产生多个半导体材料1110的薄膜。举例来说,图示的实施例可借由离子注入与剥落而作为提供多重氮化镓膜层的来源,并接着将的接合至氮化铝晶片上。深宽比捕捉技术使得可于一较不昂贵的硅基板的施体晶片上制造高品质的氮化镓薄膜。
如图11所示的实施例中,施体晶片主要包括下述元件:一半导体晶片基板1000、包覆了硅晶片基板1000的一介电材料1010的膜层、沟槽介电材料1010的膜层包括了露出了硅晶片基板1000的表面的沟槽、这些沟槽具有大体垂直侧壁、以及这些沟槽的高与宽的比例大于或等于1、半导体材料1110填入于沟槽内并溢出于沟槽以形成一单一连续膜层,以及位于沟槽内的捕捉区,其可使得贯穿差排1040为介电材料的侧壁所拦截并于该处终止。
图12显示了如图11所示的施体晶片的一制造方法。包括以下步骤:
沉积一介电材料1010的膜层于一硅晶片1000的表面上,形成沟槽于介电材料1010的膜层内,以露出硅晶片1000的表面,各沟槽具有大体垂直侧壁,以及各沟槽的高度与宽度的比例大于或等于1;以及成长如氮化镓的一半导体材料1110的膜层以填入沟槽并接合成一单一连续膜层。
图13则总结了如图12所示的制造方法的一变化情形,其中于成长半导体材料1110之前,先洁净了位于沟槽底部的硅晶片基板1000的表面。图14则总结了如图12所示制造方法的另一变化情形,其包括了平坦化了半导体材料1110的表面。
接着描述如前所述的用于分离施体晶片概念的一方法,以形成一氮化镓基板,例如为结合于一氮化铝晶片的一高品质氮化镓薄膜。其较佳地为形成接合于一基板材料的半导体材料的制造方法。
于制造出施体晶片(如图11所示)后,图15显示了后续的制造步骤:
使用如氢离子或氢离子与氦离子的组合,以离子注入半导体材料1110的膜层以形成一分裂平面1120。接着采用公知技术结合半导体材料1110的膜层与握持基板1130,如图16所示。当半导体材料1110为氮化镓时,通常用于握持基板1130的较佳材料为具有相似热膨胀系数的一材料,例如为氮化铝。
最终步骤为借由回火或施加机械压力自分裂平面1120分裂半导体材料1110的膜层,所得到的结果为如图17所示:
接合于一握持基板1130一半导体材料1110的膜层。当半导体材料1110的缺陷密度为低时(例如少于或等于5x107/cm2)时、或当于半导体材料1110与握持基板1130之间具有不匹配的晶格常数,且/或具有于半导体1110与握持晶片1130之间似有接近的匹配热膨胀时,上述结构特别有用。再次地,对于部分材料,如GaN、InN、AlN或上述材料的三元或四元组成物,当差排密度少于108/cm2才适用于装置的应用。对于某些材料言而,如GaAs或InP,则需要更低的差排密度以适用于装置,例如少于106/cm2。
图18总结了用于制造由半导体材料的膜层结合于一基板之前述方:
沉积一介电材料1010的膜层于硅晶片1000的表面;形成沟槽于介电材料1010的内,以露出硅晶片1000的表面,各沟槽具有大体垂直侧壁,而各沟槽的高与宽的比例大于或等于1;成长半导体材料1110的一膜层于沟槽内并接合成一连续膜层;使用离子注入半导体材料1110的膜层以制作出一分裂平面1120;接合握持基板1130与半导体材料1110的膜层;以及自分裂平面1120分裂半导体材料1110的膜层。
图19总结了如图18所示方法的一变化情形,其中于半导体材料1010沉积之前,先洁净了位于沟槽底部的半导体晶片1000的表面。第20图则总结了如图18所示方法的又一变化情形,其中于注入离子之前,先平坦化了半导体材料1110的表面。
于部分实施例中,由于相较于硅晶片基板外延材料通常具有较大的热膨胀系数,故借由深宽比捕捉技术所成长的接合薄膜可能遭遇破裂的疑虑。当自成长温度冷却之后,形成的结构内的薄膜较基板更为收缩。如图21所示,于薄膜内的拉伸应变(tensile strain)导致了破裂1140。破裂1140将冲击了如发光二极管或太阳能电池的装置的表现与可靠度。
图22显示了一新颖的解决方法:
制造凹洞(divot)1150于半导体材料的膜层内。可采用标准技术以形成这些凹洞,例如为光刻、蚀刻或激光剥离术。这些凹洞1150有效地限制了接合膜层的区域。其结果为,降低了于半导体材料内的热导应变。当这些凹洞具有适当尺寸与间距时,其可允许半导体材料弹性地调和热应力,且极大地降低或减少晶片的弯曲情形。图23总结了借由深宽比捕捉技术于一硅基板之上成长半导体材料的一接合膜层,以降低热导应力的方法,包括:
沉积一介电材料1010的膜层于一硅晶片1000的表面上;形成沟槽于介电材料1010的膜层内,以露出硅晶片1000的表面,各沟槽具有大体垂直侧壁,而各沟槽的高度与宽度的比例可大于或等于1;成长半导体材料1030的膜层以填入于沟槽内并接合成一单一连续薄膜;以及于半导体材料内形成凹洞1150。
于一实施例中,示范性的第一凹洞可沿着平行于如介于约0.1-1.0微米的一规则、不规则、规定的、周期的或间歇的间距的一第一方向而延伸。于此方法中,半导体材料可参照数个条状物或片段而形成。相似于第一凹洞,一示范性的第二凹洞则可延伸于有别于(例如是垂直于)第一方向的一第二方向。于此情形中,半导体材料可制作成为数个岛状物。当第一凹洞与第二凹洞的图案为规则且相等的,其所得到的岛状物可为正方形,然而也可使用适用于此岛状物的其他已知形状。于一实施例中,半导体材料可包括一底二极管区、一有源二极管区与一顶二极管区。
降低成长于一硅基板上借由深宽比捕捉技术所形成的用于发光二极管的接合膜层内的热导应变的一示范方法,包括:
沉积一介电材料1010的膜层于一硅晶片1000的表面上;形成沟槽或孔洞于介电材料1010的膜层内,以露出具有未被图案化的线状物或片状物的硅晶片的表面,分别具有大体垂直侧壁,而各沟槽的高度与宽度可足够制作出的捕捉区;以及接着借由标准技术(如金属有机化学气相沉积法)成长一接合底二极管区、一有源二极管区与一顶二极管区于符合未经图案化的介电材料1010内的巷道内的图案化区域内,以于未经图案化的介电材料1010的巷道之上形成凹洞。
图23A显示了数个步骤的结果。对应于位于半导体材料内凹洞以分离(例如切割或剥离)形成单一发光二极管1600和/或施行相对于第一实施例的额外步骤,以形成发光二极管的另一实施例。
于一实施例中于对应的发光二极管的各巷弄中的凹洞可占据其长度或宽度尺寸的10-30%。示范的凹洞可具有相对于一邻近发光二极管的顶面约为45度角的一倾斜侧壁。或者,凹洞的侧壁可使用一更大或更小角度,例如为30度、60度等。
于一III-N系统中,可于松散(relaxed)氮化镓上成长用于发光二极管的有源区。举例来说,如此的经松散的氮化镓可为c平面(c plane)氮化镓晶片或为成长于蓝宝石或碳化硅的一基板上大体经松散的c平面氮化镓外延。然而,对于可见光发射情形而言,发射区域需维持铟的显著分量。因此,位于一III-N系统内用于可见光发光二极管的发射区具有一或多个InGaN合金膜层,InGaN膜层相较于氮化镓具有一较大晶格常数。为了避免或降低弄乱所伴随的放松应变外延层的离子,可使于下方的氮化镓层上的InGaN膜层仍维持应变(例如当其成长时,其具有大体相同如下方氮化镓层的晶格常数)。再者,上述c平面III-N半导体材料为极性物质(polar material),且于发射区的应变导致了显著的极化区域(例如压电极化,piezoelectric polarization),其会干扰装置表现。举例来说,其可劣化装置/发射效率或造成发射光的波长的偏移。
图23B显示了依据另一实施例的用于发光二极管的一示范性二极管结构。请参照图23B,至少邻近于基板的一底二极管区的一部分包括了InGaN(以取代GaN)。此底部二极管区内的InGaN可为采用深宽比捕捉技术形成的具有较低或经控制的缺陷密度的一松散层。如此底二极管区的InGaN可为具有显著降低应变的发射区域的一平台(如发光二极管的发光区)。举例来说,用于有源二极管区(例如具有低应变或没有应变的InGaN)与顶部二极管区之后续成长可导致了于发射区内的显著降低应变。如图23B所示,底二极管区1502为经松散的N型InGaN位于并部分地于一缺陷捕捉区1504内,一有源二极管区1512则包括了AlGaN阻挡区1506(例如具有等同底部二极管区晶格空间)、一降低应变InGaN发射区1508与一AlGaN阻挡区1510(例如具有等同于发射区的晶格空间)。于有源二极管区1512之上形成有一顶二极管区1514,其材质例如为经松散的P型InGaN。于图23B中,基板可为一硅基板1500,且可适度的增加接触了上部/顶部或下部/底部二极管区的导电接触物(如前所述结构)。
发光二极管的制作可借由于一单一封装物或模组内安装不同材料的半导体芯片以制作出单芯片方案。此技术使得其可结合不同色彩以形成白光。
研究者已发展出高效率太阳能电池的多芯片方案,其借由于一单一封装物或模组内安装由不同材料所制成的半导体芯片。其应用了“分离光谱(splitspectrum)”方法,其将太阳能光谱的一部分导向至芯片处,以最佳化于的该部的该光谱。
于前述的两实施例中,安装与封装多重芯片的成本可为极高。因此本发明提供了一种单芯片方案,其较为不昂贵。基于图示的目的,在此仅描述了具有三个不同的单一二极管的单一芯片。
图24显示了第一部分的步骤。沉积一第一介电材料1010的膜层于一硅基板1000上。接着形成沟槽1160于第一介电材料1010的膜层的第一区内,其具有大体垂直侧壁。各沟槽露出该硅晶片1000的表面。各沟槽的宽度可相同于或少于介电材料的厚度,以使得沟槽可捕捉差排缺陷。
接着可借由前述方法而选择性地洁净位于沟槽1160的底部的硅基板1000的表面。
接着遮蔽于所有位置的结构的顶面,除了二极管装置1195的区域。可成长底二极管区1170,于沟槽填入半导体材料并接合成单一连续薄膜,如第25图所示,示范性半导体材料则如前所示。贯穿差排形成于底二极管区1170与硅基板1000之间的界面处。贯穿差排向上朝向一45度角传播,而为沟槽的侧壁所拦截并终止于此捕捉区内。
此时,可平坦化底二极管区1170。
接着成长一半导体材料膜层,以形成有源二极管区1180,以及成长另一半导体材料以形成顶二极管区1190。同时,底二极管区1170、有源二极管区1180与顶二极管区1190组成了第一(#1)二极管装置1195。
接着沉积一第二介电材料1200的膜层。举例来说,当第一介电材料为SiO2时,第二介电材料可为SiNx。借由湿蚀刻或干蚀刻选择性地自所有区域移除第二介电材料1200除了,包括二极管装置元件1的区域,留下如第26图所示结构。
接着遮蔽所有位置处的结构,除了第二(#2)二极管装置(1240)处的结构。于后续步骤中,借由形成#1二极管装置的相同步骤以形成第二(#2)二极管装置(1240),进而得到了如第27图所示的结构。如第27图所示,一底二极管区1210、一有源二极管区1220与一顶二极管区1230组成了#2二极管装置(1240)。
沉积另一第二介电材料1200的膜层,以覆盖二极管装置构件2(1240)。接着借由湿蚀刻或干蚀刻选择性地移除包括了第三(#3)二极管装置(1280)的区域的第二介电材料1200的膜层。
接着遮蔽所有区域,除了#3二极管装置(1280)的区域,并借由相同用于形成#1二极管装置(1195)与#2二极管装置(1240)的步骤制作#3二极管装置(1280)。如此形成了如图28所示的结构。如图28所示,底二极管区1250、有源二极管区1260与顶二极管区1270形成了#3二极管装置构件。
最后,采用第二介电材料1200覆盖#3二极管装置,并图案化形成通过第二介电材料1200的接触介层物(contact vias,未显示),并沉积各别的导电接触物1290于各二极管装置的顶部。以及形成一底导电接触物(1300)于支撑基板1000之上,其较佳地但非必要地为各装置所共用。
图29显示了最终结果。不同二极管装置可包括用于形成顶、有源与底二极管区等构件的不同组的半导体材料。于各二极管装置中,材料的能隙经过设计以发射出所期望的光线(于单一的二极管中)或吸收期望频率的光线(于太阳能电池中)。这些实施例代表了于单一芯片之上采用相对不昂贵方式而形成了多个二极管装置。
总而言之,包括多个二极管装置的单芯片,包括下述元件:
一硅晶片基板1000、覆盖硅晶片基板1000的一第一介电材料1010的膜层、第一介电材料1010的膜层露出了硅晶片基板1000的表面包括了沟槽1160,这些沟槽1160具有大体垂直侧壁,而这些沟槽1160的高与宽的比例大于或等于1、数个二极管装置(至少为三个装置1995、1240、1280)分别包括填入于沟槽1160且位于第一介电材料1010的膜层一部分内的一半导体材料,其溢出于沟槽1160以形成一底二极管区(1170、1210、1250),用于捕捉贯穿差排位于沟槽1160内的一捕捉区、一有源二极管区(1180、1220、1260)及一顶二极管区(1195、1240、1280)、顶部导电接触物(1290)与底部导电接触物(1300)。
图30总结了如图29所示结构的一制造方法。此方法可于单一芯片上制造数个二极管装置,包括下列步骤:
沉积一第一介电材料1010的膜层于一硅晶片1000的表面上;
形成沟槽1160于第一介电材料1010的膜层内,以露出硅晶片1000的表面,各沟槽1160具有大体垂直侧壁,而各沟槽1160的高与宽比例大于或等于1;
遮蔽#1二极管装置1(1195)以外所有位置处的结构;
采用以下步骤制作#1二极管装置:成长一半导体材料的膜层,其填入于沟槽内、溢出沟槽且接合成具有单一连续薄膜形态的一底二极管区1170;成长一半导体材料以形成一有源区1180;以及成长一半导体材料以形成一顶二极管区1190;
沉积一第二介电材料(1200)的膜层;
选择性地移除用于设置#1二极管装置(1195)以外所有区域除的第二介电材料(1200);
遮蔽#2二极管装置(1240)所有位置以外的所有位置的结构;
借由形成#1二极管装置(1195)的相同步骤形成#2二极管装置(1240);
沉积第二介电材料(1200)以覆盖#2二极管装置(1240);
选择性地移除用于设置#3二极管装置(1280)所在位置区域的第二介电材料(1200);
遮蔽设置#3二极管装置3(1280)所在位置以外所有位置的结构;
利用制作#1二极管装置(1195)与#2二极管装置(1240)的相同步骤制造#3二极管装置(1280);
沉积一第二介电材料(1200)以覆盖#3二极管装置(1280);
形成图案化的接触介层物,穿过第二介电材料1280;
形成顶导电接触物(1290)至#1二极管装置、#2二极管装置2与#3二极管装置;以及
形成为以上三个二极管所共用的一底导电接触物1300。
可以理解的是,可以的话,可于单一芯片之上形成任何数量的二极管,其唯一限制为所能使用的空间。
本发明的实施例中采用沟槽的描述以形成捕捉区,然而也可使用如凹口的具有可捕捉缺陷的足够剖面的其他结构,且于此处可称之为沟槽。
本发明的应用提供了可用于或借由外延成长或相似情形所形成的多个方法、结构或装置。举例来说示范的适当外延成长系统可为单一晶片或多晶片的批次反应器。也可使用不同化学气相沉积技术。于制造应用中的常用于体积外延(volume epitaxy)的适当的化学气相沉积系统包括如由德国Aixtron提供的Aixtron 2600多晶片系统;由应用材料所产制的EPI CENTURA单芯片外延反应器;或由荷兰ASM国际所产制的EPSILON单晶片多重腔体系统。
于说明书中关于“一实施例”、“一实施例”、“示范性的实施例”、“另一实施例”等描述意谓着于本发明的至少一实施例中所包括的一特定构件、结构或特性。于说明书内不同处之上述描述的出现并非指同一实施例。再者,当于任一实施例描述了相关的一特殊构件、结构、特性时,可以理解的是本领域技术人员可了解如此的特征、结构或特性也可用于其他的实施例。再者,为了方便了解,特定方法步骤可采用分隔步骤表现,然而这些分隔步骤依照其表现并不会限制其顺序。此即为部分步骤可依照其他顺序、或同时的施行。此外,示范性图表显示了依据本发明的实施例不同方法。可于此描述如此的示范性方法的实施例并提供了对应的装置实施例,然而这些方法实施例并未用于限制本发明。
虽然本发明绘示了并描述了的部分实施例,可以理解的是本领域技术人员可依照本发明的精神与原则而针对这些实施例进行变更。前述的实施例便视为所有方面的图示情形而非于此用于限制本发明。本发明的范畴因此依照申请中专利范围所限定,而非前述的描述。于本说明书中,“较佳地”的描述意谓着“较佳地,但非用以加以限制”。权利要求内的描述依照本发明的概念而采用其最大解释范围。举例来说,“耦接于”及“连接”等描述采用以解说直接与非直接连接与耦合情形。于另一范例中,“具有”与“包括”,其相似描述可与“包括”相同(即上述描述皆视为开放性描述),仅“由...组成”与“实质上由...组成”可视为“封闭型”描述。
本发明的较佳实施例包括了一光电装置,包括:
一基板;一介电材料,包括两个或更多个开口露出基板的一部分,此两个或两个以上的开口分别具有至少为1的一深宽比;一底部二极管材料,包括晶格不相称于该基板的一化合物半导体材料,且其中该化合物半导体材料占据了所述两个或两个以上的开口并于所述两个或两个以上的开口之上接合成一底二极管区域;一顶二极管材料;以及一有源二极管区,位于该顶部二极管材料与该底部二极管材料之间。此基板择自由硅、蓝宝石与碳化硅所组成的族群。此基板为具有一结晶方向为(111)或(100)的一单晶硅晶片。此有源二极管区包括由该顶部二极管材料与该底部二极管材料的结所形成的一p-n结。此有源二极管区包括不同于该顶部二极管材料与该底部二极管材料的一材料,而该有源二极管材料构成了位于该顶部二极管材料与底部二极管材料间的一p-i-n结的一本征区。此有源二极管区包括多个多重量子阱,形成于该顶部二极管材料与该底部二极管材料之间。此介电材料包括实质上择自由二氧化硅、氮化硅、氮氧化硅、铪的氧化物、铪的硅化物、锆的氧化物、锆的硅化物及其组合的一材料。此开口为于两平行轴向上具有至少为1的一深宽比的一孔洞。此半导体材料择自由实质上包括一III-V族化合物、一II-VI族化合物、一IV族合金以及其组合物所组成的族群。此底部二极管材料包括一n型掺质,而该顶部二极管材料包括一p型掺质。上述装置更包括一接触物,形成于该顶部二极管区之上。及更包括一第二接触物形成并邻近于该基板。
本发明的其他较佳实施例可包括一种光电装置,包括:
一基板;以及一光电二极管,包括:一第一区,邻近该基板的一第一顶面;一第二区,邻近该第一区;以及一有源区,介于该第一区与该第二区之间,其中该第二区包括邻近于该有源区的一表面,该表面大体平行于该基板的该顶面;以及该第二区包括与该有源区相分隔的至少一缺陷捕捉区,该缺陷捕捉区包括延伸自该基板的该顶面的一表面。该第一区的一表面连结于一握持基板。该握持基板连结有一中间层,该中间层位于该第一区与该握持基板之间。该握持晶片包括电性连结于该第一区的一导体。上述装置更包括一接触物,连结于该握持基板并电性连结于该第一二极管区。
本发明的其他较佳实施例包括一种光电装置的制造方法。上述方法包括:沉积一第一介电材料层于一基板之上;图案化该第一介电材料层以于其内形成两个或两个以上的开口,露出该基板的该表面的部分,所述两个或两个以上的开口具有至少为1的深宽比;借由成长晶格不相称于该基板的一化合物半导体材料于所述两个或两个以上的开口内并使得该化合物半导体材料填满所述两个或两个以上的开口并于所述两个或两个以上开口之上结合成一连续膜层,以形成一底部二极管区;形成一有源二极管区于该底部二极管区之上;以及形成一顶部二极管区于该有源二极管区之上。上述方法更包括连结一握持晶片至该顶部二极管区;以及移除该基板。
本发明的另一较佳实施例可提供一光电装置,其具有一底二极管区,包括两个或两个以上的差排捕捉区且包括一化合物半导体材料、一有源二极管区、一顶二极管区、一握持基板、相连于握持基板的一第一导电接触物与相连于底二极管区的一第二导电接触物。
本发明的另一较佳实施例提供了一种光电装置的制造方法,包括沉积一介电材料的膜层于一基板上,形成两个或两个以上开口于介电材料内以露出基板的表面,此两个或两个以上开口具有至少为1的深宽比,形成一底部二极管区借由成长一化合物半导体材料晶格不匹配于基板于此两个或两个以上开口内并使得化合物半导体填入于两个或两个以上开口并相连于其上以形成一连续膜层,形成一有源二极管区位于底部二极管区之上,形成一顶二极管区位于有源二极管区之上,接合一握持晶片与顶二极管区,移除基板移除介电材料,接触第一导电接触物与该握持基板与接触一第二电性接触物与底部二极管区。
本发明另一较佳实施例包括了用于制造包括接合于一基板的一半导体材料的一制造方法。此方法可包括沉积一介电材料的膜层于一基板上,形成两个或更多开口于介电材料内以露出基板的表面的部分,此两个或更多开口具有至少为1的深宽比,成长一化合物半导体材料晶格不匹配于基板于两个或更多开口内并使得其填入于其中并接合成一连续膜层,注入离子进入半导体材料以形成一分裂平面,接合一握持基板与半导体材料以及自该分裂平面处分离半导体材料。
于某些方面,较佳实施例提供了包括了数个分离的光电装置形成于其上的一芯片。此芯片可包括一基板、覆盖该基板且具有数个具有深宽比至少为1的开口位于其内的一第一介电材料的膜层,多个分离的光电装置,各光电装置包括(i)不匹配于基板的一半导体材料膜层,占据两个开口且接合于开口之上以形成单一底二极管区;(ii)一有源二极管区;及(iii)一顶部二极管区,一第二介电材料层覆盖该些分离光电装置,至少一顶导电接触物与至少一底导电接触物。
用于制作包括多个分离的光电装置于其上的一芯片的另一较佳方法包括:
沉积一介电材料的膜层于一基板上,形成第一组开口于介电材料内以露出基板的表面,该第一组开口具有至少为1的深宽比,形成一第一底二极管区,其借由成长一半导体材料的膜层晶格不匹配于基板于第一组开口内并使得半导体材料填满第一组开口并于第一组开口之上接合成为一连续膜层,形成一第一有源二极管区于第一底二极管区上,形成第一顶二极管区于第一有源二极管区之上,成长一介电材料层以覆盖该第一底二极管区、该第一有源二极管区、与该第一顶二极管区,于该介电材料的膜层内图案化形成一第二组开口具有深宽比至少为1,形成一第二底部二极管区借由于第二开口内成长晶格不匹配于基板的一半导体材料的膜层并使得半导体材料填满第二组开口并于第二组开口之上接合成为一连续膜层,形成一第二有源二极管区于第一底部二极管区上,形成第二顶二极管区于第二有源二极管区之上,成长一介电材料层以覆盖该第二底二极管区、该第二有源二极管区、与该第二顶二极管区。此方法更包括接触一第一导电接触物与基板,接触一第二导电接触物与第一部分电极区、以及接触一第三导电接触物与一第二顶电极区。
虽然本发明已以较佳实施例揭示如上,然而其并非用以限定本发明,任何本领域技术人员,在不脱离本发明的精神和范围内,当可作更动与润饰,因此本发明的保护范围当视随附的权利要求所界定的范围为准。
Claims (15)
1.一种光电装置,包括:
一基板;
一介电材料,包括露出该基板的一部分的两个或两个以上的开口,所述两个或两个以上的开口分别具有至少为1的一深宽比;
一底部二极管材料,包括晶格不相称于该基板的一化合物半导体材料,且其中该化合物半导体材料占据了所述两个或两个以上的开口并于所述两个或两个以上的开口之上接合以形成一底二极管区;
一顶部二极管材料;以及
一有源二极管区,位于该顶部二极管材料与该底部二极管材料之间。
2.如权利要求1所述的光电装置,其中该有源二极管区包括不同于该顶部二极管材料与该底部二极管材料的一材料,而该有源二极管材料构成了位于该顶部二极管材料与底部二极管材料间的一p-i-n结的一本征区。
3.如权利要求1所述的光电装置,其中该有源二极管区包括多个多重量子阱,形成于该顶部二极管材料与该底部二极管材料之间。
4.如权利要求1所述的光电装置,其中该介电材料包括实质上择自二氧化硅、氮化硅、氮氧化硅、铪的氧化物、铪的硅化物、锆的氧化物、锆的硅化物及其组合所组成的族群中的一材料。
5.如权利要求1所述的光电装置,其中该开口为于两垂直轴向上具有至少为1的一深宽比的一孔洞。
6.如权利要求1所述的光电装置,其中该半导体材料择自实质上由一III-V族化合物、一II-VI族化合物、一IV族合金及其组合所组成族群的一材料。
7.如权利要求1所述的光电装置,其中该底部二极管材料包括一n型掺质,而该顶部二极管材料包括一p型掺质。
8.一种光电装置,包括:
一基板;以及
一光电二极管,包括:
一第一区,邻近该基板的一第一顶面;
一第二区,邻近该第一区;以及
一有源区,介于该第一区与该第二区之间,
其中该第二区包括邻近于该有源区的一表面,该表面平行于该基板的该顶面;以及
该第二区包括与该有源区相分隔的至少一缺陷捕捉区,该缺陷捕捉区包括延伸自该基板的该顶面的一表面。
9.如权利要求8所述的光电装置,其中该第一区的一表面接合于一握持基板。
10.如权利要求8所述的光电装置,其中该握持基板接合有一中间层,该中间层位于该第一区与该握持基板之间。
11.如权利要求9所述的光电装置,其中该握持晶片包括电性连结于该第一区的一导电物。
12.如权利要求8所述的光电装置,更包括一接触物,连结于该握持基板并电性连结于该第一二极管区。
13.一种光电装置的制造方法,包括:
沉积一第一介电材料层于一基板之上;
图案化该第一介电材料层以于其内形成两个或两个以上的开口,以露出该基板的该表面的部分,所述两个或两个以上的开口具有至少为1的深宽比;
借由成长晶格不相称于该基板的一化合物半导体材料于所述两个或两个以上的开口内,使得该化合物半导体材料填满所述两个或两个以上的开口以及于所述两个或两个以上开口之上接合成一连续膜层,以形成一底二极管区;
形成一有源二极管区于该底部二极管区之上;以及
形成一顶二极管区于该有源二极管区之上。
14.如权利要求13所述的光电装置的制造方法,更包括:
接合一握持晶片至该顶部二极管区;以及
移除该基板。
15.如权利要求13所述的光电装置的制造方法,更包括:
注入离子进入该半导体材料以制造出一分裂平面;
接合一握持基板至该半导体材料;以及
自该分裂平面处分裂该半导体材料的膜层。
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JP2013048301A (ja) | 2013-03-07 |
JP2015130530A (ja) | 2015-07-16 |
TWI427830B (zh) | 2014-02-21 |
US20150221546A1 (en) | 2015-08-06 |
US20130034924A1 (en) | 2013-02-07 |
US8765510B2 (en) | 2014-07-01 |
TW201125162A (en) | 2011-07-16 |
CN102122675A (zh) | 2011-07-13 |
EP2343742A3 (en) | 2014-03-19 |
US20140264272A1 (en) | 2014-09-18 |
JP5829598B2 (ja) | 2015-12-09 |
JP2011142294A (ja) | 2011-07-21 |
US20100176371A1 (en) | 2010-07-15 |
EP2343742B1 (en) | 2019-03-13 |
JP6484076B2 (ja) | 2019-03-13 |
JP5399335B2 (ja) | 2014-01-29 |
SG173245A1 (en) | 2011-08-29 |
KR20110081742A (ko) | 2011-07-14 |
EP2343742A2 (en) | 2011-07-13 |
US8304805B2 (en) | 2012-11-06 |
US9029908B2 (en) | 2015-05-12 |
US9449868B2 (en) | 2016-09-20 |
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