TWI427830B - 光電裝置之製造方法 - Google Patents
光電裝置之製造方法 Download PDFInfo
- Publication number
- TWI427830B TWI427830B TW99122432A TW99122432A TWI427830B TW I427830 B TWI427830 B TW I427830B TW 99122432 A TW99122432 A TW 99122432A TW 99122432 A TW99122432 A TW 99122432A TW I427830 B TWI427830 B TW I427830B
- Authority
- TW
- Taiwan
- Prior art keywords
- diode
- substrate
- region
- diode region
- wafer
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 39
- 239000000463 material Substances 0.000 claims description 150
- 239000004065 semiconductor Substances 0.000 claims description 141
- 239000000758 substrate Substances 0.000 claims description 137
- 239000003989 dielectric material Substances 0.000 claims description 72
- 150000001875 compounds Chemical class 0.000 claims description 44
- 238000000151 deposition Methods 0.000 claims description 18
- 230000005693 optoelectronics Effects 0.000 claims description 12
- 239000013078 crystal Substances 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 6
- 210000000746 body region Anatomy 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 102
- 235000012431 wafers Nutrition 0.000 description 82
- 238000000034 method Methods 0.000 description 72
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 46
- 229910002601 GaN Inorganic materials 0.000 description 44
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 35
- 230000007547 defect Effects 0.000 description 23
- XCZXGTMEAKBVPV-UHFFFAOYSA-N trimethylgallium Chemical compound C[Ga](C)C XCZXGTMEAKBVPV-UHFFFAOYSA-N 0.000 description 20
- 229910052732 germanium Inorganic materials 0.000 description 14
- 239000001257 hydrogen Substances 0.000 description 13
- 229910052739 hydrogen Inorganic materials 0.000 description 13
- -1 binary Chemical class 0.000 description 11
- 210000004027 cell Anatomy 0.000 description 11
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 10
- 239000002243 precursor Substances 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 8
- 229910052787 antimony Inorganic materials 0.000 description 7
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 7
- 229910052594 sapphire Inorganic materials 0.000 description 7
- 239000010980 sapphire Substances 0.000 description 7
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 6
- 229910002704 AlGaN Inorganic materials 0.000 description 5
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 5
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000005336 cracking Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 230000035882 stress Effects 0.000 description 5
- 229910003468 tantalcarbide Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 4
- 229910000420 cerium oxide Inorganic materials 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010561 standard procedure Methods 0.000 description 4
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 description 4
- 230000005641 tunneling Effects 0.000 description 4
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 3
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 210000004508 polar body Anatomy 0.000 description 3
- 229910052707 ruthenium Inorganic materials 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011701 zinc Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000004020 luminiscence type Methods 0.000 description 2
- 229910052749 magnesium Inorganic materials 0.000 description 2
- 239000011777 magnesium Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052758 niobium Inorganic materials 0.000 description 2
- 239000010955 niobium Substances 0.000 description 2
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000005496 tempering Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052684 Cerium Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- BUGBHKTXTAQXES-UHFFFAOYSA-N Selenium Chemical compound [Se] BUGBHKTXTAQXES-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 239000005864 Sulphur Substances 0.000 description 1
- KMYDRZUGLSMFOC-UHFFFAOYSA-N [Te].[Te].[Te].[Ce].[Ce] Chemical compound [Te].[Te].[Te].[Ce].[Ce] KMYDRZUGLSMFOC-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- BCZWPKDRLPGFFZ-UHFFFAOYSA-N azanylidynecerium Chemical compound [Ce]#N BCZWPKDRLPGFFZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- GWXLDORMOJMVQZ-UHFFFAOYSA-N cerium Chemical compound [Ce] GWXLDORMOJMVQZ-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- RKTYLMNFRDHKIL-UHFFFAOYSA-N copper;5,10,15,20-tetraphenylporphyrin-22,24-diide Chemical compound [Cu+2].C1=CC(C(=C2C=CC([N-]2)=C(C=2C=CC=CC=2)C=2C=CC(N=2)=C(C=2C=CC=CC=2)C2=CC=C3[N-]2)C=2C=CC=CC=2)=NC1=C3C1=CC=CC=C1 RKTYLMNFRDHKIL-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- BIXHRBFZLLFBFL-UHFFFAOYSA-N germanium nitride Chemical compound N#[Ge]N([Ge]#N)[Ge]#N BIXHRBFZLLFBFL-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 229910052747 lanthanoid Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- VSZWPYCFIRKVQL-UHFFFAOYSA-N selanylidenegallium;selenium Chemical compound [Se].[Se]=[Ga].[Se]=[Ga] VSZWPYCFIRKVQL-UHFFFAOYSA-N 0.000 description 1
- 229910052711 selenium Inorganic materials 0.000 description 1
- 239000011669 selenium Substances 0.000 description 1
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 description 1
- 238000004901 spalling Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- 150000004772 tellurides Chemical class 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02389—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
- H01L29/151—Compositional structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/184—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP
- H01L31/1852—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof the active layers comprising only AIIIBV compounds, e.g. GaAs, InP comprising a growth substrate not being an AIIIBV compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02458—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02543—Phosphides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02647—Lateral overgrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/88—Tunnel-effect diodes
- H01L29/882—Resonant tunneling diodes, i.e. RTD, RTBD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/005—Processes relating to semiconductor body packages relating to encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/543—Solar cells from Group II-VI materials
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/544—Solar cells from Group III-V materials
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Electromagnetism (AREA)
- Led Devices (AREA)
- Light Receiving Elements (AREA)
- Photovoltaic Devices (AREA)
- Recrystallisation Techniques (AREA)
Description
本發明係關於由位於矽晶圓之上由化合物半導體(compound semiconductors)或其他之晶格不相稱半導體材料(lattice-mismatched semiconductors)所製成之半導體二極體及其製造方法,且特別是關於如發光二極體(light emitting diode)、雷射、光電壓(photovoltaics)及其他光電子(optoelectronic)用途之光電應用。
於下文中將主張2007年4月9日申請之第60/922,533號美國臨時專利申請案之優先權的第60/922,533號美國專利申請案(申請日為2008年4月9號)以提及方式併入於本文中。
本節中提供了背景資料並介紹了於下文中所描述及/或所主張之權利範圍所相關之不同觀點的相關資訊。此些背景資料的陳述並非承認其為習知技術。
大部分的晶片製作皆應用了具有高品質、大區域、低成本等優點之矽晶圓的矽製程。採用如砷化鎵(gallium arsenide)與磷化銦(indium phosphide)等化合物半導體之裝置的商業製作則通常無法具有前述之矽製程的優點。其通常於由如藍寶石(sapphire)、鍺(germanium)、砷化鎵(gallium arsenide)或碳化矽(silicon carbide)等材料所製成之小且昂貴的晶圓上進行如發光二極體(light emitting diode,LED)、多接面太陽能電池(multi-junction solar cell)及其他化合物半導體裝置之製作。
於便宜之基板上製造半導體化合物裝置的挑戰牽涉到極大的經濟因素。由於可發射與偵測光線,化合物半導體於通訊基礎建設中係為重要的元件。其為適用於如透過光纖傳輸訊號之雷射中、用於接受上述訊號之感測器、行動電話內之放大器(amplifier)、行動電話基地台內之放大器、以及與傳輸與接收微波訊號之電路等應用中的材料。
發光二極體通常由設置於藍寶石(sapphire)或碳化矽(silicon carbide)材質之晶圓上的多個氮化鎵(gallium nitride)膜層所組成。此些獨特基板造成了發光二極體之高成本。直徑4英吋之藍寶石晶圓之通常價值約130美元,而兩英吋之碳化矽晶圓則價值約2000美元。作為比較之用,具有四倍於四英吋晶圓之使用面積或16倍於兩英吋晶圓之使用面積之八英吋矽晶圓的成本則通常低於100美元。
高效多接面太陽能電池(high-efficiency multi-juction solar cells)通常包括設置於鍺晶圓上之如鍺、砷化鎵及磷化銦之膜層。於發光二極體所用之晶圓中,所使用之鍺晶圓通常較矽晶圓為較小且明顯為較昂貴。
於矽晶圓上製作化合物半導體裝置之能力有助於加速其於多種主要工業中的市場成長。
目前限制了半導體晶圓上之化合物半導體裝置的實際製作之兩種主要技術障礙分別為晶格常數之不匹配(mismatch of lattice constants)與熱膨脹係數之不匹配(mismatch of thermal expansion coefficients)之情形。
晶格不匹配:於結晶物中,原子係依照規則性週期陣列物而設置(即習知之晶格)。介於原子之間的距離,即習知之晶格常數,通常約為數埃(1埃=10-10
米)。矽具有較化合物半導體為小之晶格常數。當於矽上成長化合物半導體時,於介面處出現了如習知之錯配差排(misfit dislocation)之結晶瑕疵(crystalline imperfections)。如此之錯配差排造成了如習知貫穿差排(threading dislocation)之其他結晶缺陷,其自介面處向上傳播。貫穿差排縮減了如雷射、太陽能電池、發光二極體等化合物半導體裝置之表現與可靠度。
熱收縮之不匹配:化合物半導體通常於如超過1000℃之高溫下成長。當晶圓冷卻之後,化合物半導體之薄膜較矽晶圓的收縮程度為大。其結果為,晶圓將彎曲成為內凹狀,且施加應力與最終地使得薄膜產生破裂。
直到最近,發展出了包括下述三種方法之於矽基板上成長高品質之化合物半導體之最穩固之先前技術,例如漸變緩衝層(graded buffer layers)法、晶圓連結(wafer bonding)法或於島狀物上之選擇性成長(selective growth on mesas)法等技術。然而,上述技術則尚未達成商業上之成功。
於漸變緩衝層法中,材料的組成由大體純矽(pure silicon)逐漸地變化成化合物半導體。由於晶格常數亦逐漸地隨著變化,故晶格缺陷較少形成於介面處。不幸地,此些漸變緩衝層具有相對厚之厚度(每4%之晶格不相稱情形具有約10微米)。如此厚之緩衝層增加了製程成本及破裂之可能性。
晶圓連結法則牽涉到於昂貴基板上成長一裝置、接著剝離上述裝置並將之接合(bonding)於矽晶圓上。上述方法並不考慮採用當今矽製程以作為降低成本之方法。此外,接合通常需要高於300℃之溫度。當材料冷卻之後,由於相較矽晶圓具有更大之收縮情形,故化合物半導體可能破裂。
島狀物上之選擇性成長法則利用了特定差排之遷移率。此方法係於小區域(長度約為10-100微米)內沈積化合物半導體材料,進而形成了一短通道,其之可供位於此處之移動差排(mobile dislocation)可滑動至此區域之邊緣並自此裝置處而移除。然而,藉由上述技術所形成之結構通常具有高密度之貫穿差排(高於1億/每平方公分)。上述技術並無法移除固定差排(immobile dislocation),於當晶格不匹配超過了2%時其將成為佔大多數。
近年來已發展出了深寬比捕捉(aspect ratio trapping)技術(由Park等人於APL 90,0521113(2007)所揭露,於此以提及方式併入於本文中),其可於矽晶圓上沈積高品質之化合物半導體材料、鍺或其他之晶格不匹配材料。第1圖顯示了此深寬比捕捉技術之原理。於一矽晶圓10之上沈積如二氧化矽(SiO2
)或氮化矽(SiNx
)之一介電材料20之薄膜層。熟悉此技藝者亦可選擇如SiOx
Ny
及如鉿(Hf)與鋯(Zr)之矽化物或氧化物等之多種介電材料。
於上述介電材料內蝕刻形成一溝槽,接著沈積如鍺或化合物半導體之晶格不匹配半導體30於溝槽內。如虛線所表示之貫穿差排40將向上傳播,其通常依照相對於介面呈大體45度之一角度向上傳播。貫穿差排40並不會朝溝槽長度方向而向下傳播,其係依照垂直於結晶之成長晶面(faceted growth face)之一方向而傳播,此些晶面引導了差排朝向側壁,並於此些側壁處終止。位於溝槽內其側壁捕捉了貫穿差排之區域可稱之為”捕捉區”50。晶格不相稱半導體30之上方區域,且高於捕捉區50之一區域則為一相對無缺陷區60。
深寬比捕捉技術基於下述原因而解決了起因於熱膨脹係數的不匹配所造成之破裂問題:(1)由於磊晶膜層為薄,故應力為小;(2)由於深寬比捕捉開口的尺寸為小,故材料可為彈性地調和起因於熱膨脹不匹配所造成之應力;以及(3)較半導體材料為佳之二氧化矽基座可產生形變以調和上述應力。
請繼續參照第2圖,顯示了採用深寬比捕捉技術於矽晶圓上所形成之連續之高品質III-V族半導體或其他晶格不匹配材料之高品質薄膜。上述技術相似於如第1圖所示之技術,除了持續地成長晶格不匹配半導體直到相鄰之溝槽內的成長結合成為了一單一連續膜層70。其他的缺陷,即所謂之接合缺陷80,則形成於相接合成長處之部分之接合區域。然而,此缺陷密度仍遠少於直接於矽晶圓上成長晶格不匹配半導體之缺陷密度。
本發明提供了一種光電裝置及其製造方法。
依據一實施例,本發明提供了一種光電裝置,包括:
一基板;一介電材料,包括露出該基板之一部之兩個或兩個以上之開口,該兩個或兩個以上之開口分別具有至少為1之一深寬比;一底部二極體材料,包括晶格不相稱於該基板之一化合物半導體材料,且其中該化合物半導體材料佔據了該兩個或兩個以上之開口並於該兩個或兩個以上之開口之上接合成一底二極體區域;一頂部二極體材料;以及一主動二極體區,位於該頂部二極體材料與該底部二極體材料之間。
依據另一實施例,本發明提供了一種光電裝置,包括:
一基板;以及包括一第一區,鄰近該基板之一第一頂面、一第二區,鄰近該第一區、及一主動區,介於該第一區與該第二區之間之一光電二極體,其中該第二區包括鄰近於該主動區之一表面,該表面大體平行於該基板之該頂面;以及該第二區包括與該主動區相分隔之至少一缺陷捕捉區,該缺陷捕捉區包括延伸自該基板之該頂面之一表面。
依據又一實施例,本發明提供了一種光電裝置之製造方法,包括:
沈積一第一介電材料層於一基板之上;圖案化該第一介電材料層以於其內形成兩個或兩個以上之開口,已露出該基板之該表面之部分,該兩個或兩個以上之開口具有至少為1之深寬比;藉由成長晶格不相稱於該基板之一化合物半導體材料於該兩個或兩個以上之開口內,使得該化合物半導體材料填滿該兩個或兩個以上之開口並於該兩個或兩個以上開口之上接合成一連續膜層,以形成一底二極體區;形成一主動二極體區於該底部二極體區之上;以及形成一頂二極體區於該主動二極體區之上。
為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特舉一較佳實施例,並配合所附的圖式,作詳細說明如下:
本發明之實施例提供了適用於半導體二極體之新穎與有用之結構,其採用由深寬比捕捉(Aspect Ratio Trapping)技術於矽晶圓上沈積之化合物半導體或其他晶格之不匹配半導體所形成之接合薄膜(coalesce film)。半導體二極體係為太陽能電池(solar cells)、發光二極體(light-emitting diodes)、共振穿隧二極體(resonant tunneling diodes)、半導體雷射(semiconductor lasers)與其他裝置之基礎構件。
本發明之目的包括藉由於高品質、大區域、低成本之矽晶圓上而非於又小又較貴之基板上製作太陽能電池、發光二極體、共振穿隧二極體、半導體雷射與其他化合物半導體裝置,藉以降低太陽能電池、發光二極體、共振穿隧二極體、半導體雷射與其他化合物半導體裝置之成本。
本發明之其他目的則為於基板會劣化如發光二極體的表現之情形下,自用於裝置之一半導體二極體處移除了矽晶圓基板。
本發明之其他目的則提供了製造氮化鎵基板之一種較經濟方法,例如為於如多晶矽氮化鋁之一熱匹配基板上形成之氮化鎵之高品質薄膜。
本發明之其他目的則提供了用於形成氮化鎵薄膜之較便宜的施體晶圓(donor wafer),所形成之氮化鎵薄膜可被轉移至如氮化鋁基板之其他基板處。
本發明之其他目的則可緩和藉由深寬比捕捉形成之接合膜層內之由熱引起之破裂情形。
本發明之其他目的提供了製作包括由不同半導體材料所製成之數個二極體裝置之單晶片之較經濟方法。
於以下描述中,通常採用單一之二極體方式以討論示範之二極體結構,半導體工程師及其他熟悉此技藝者當能理解於多數應用中需使用複數個二極體,且其通常整合於單一晶片之上。
一般來說,於下文中討論之半導體二極體具有如第3圖所示之一般結構,其包括:一基板101、一底二極體區102、一主動二極體區103、一頂二極體區104、位於裝置之頂部之導電接觸物105以及位於裝置底部之一導電接觸物106。上述二極體區102、103與104內則分別由多重膜層所製成。
底二極體區102與頂二極體區104具有相反之摻雜類型(doping types)。舉例來說,當底二極體區102係顯著地為n型摻雜時(具有如磷、砷或銻之電子施體),而頂二極體區104將顯著地為p型摻雜(具有如硼或鋁之電子受體),反之亦然。於底二極體區102與頂二極體104內之重度摻雜形成了適用於電流進入與離開裝置之低電阻值通道。此頂部區與底部區之一般摻雜程度約介於1017
-1020
cm-3
。而主動區之一般摻雜程度則低於1017
cm-3
。值得注意的是,為了描述方便而採用了”頂(top)”與”底(bottom)”以指定區域,而於某些情況中頂區可位於底區之上。舉例來說,考量到形成於基板上之二極體,其具有高於其底部區之一頂部區。當此二極體經覆晶接合(flip-chip bonded)於一握持晶圓後並於移除上述基板之後,上述用於檢視二極體之情形通常也隨之相反。於此例中,頂區通常將視為位於底區之下方。
基底101通常為一矽晶圓,雖然於不同實施例中,包括藍寶石與碳化矽之其他基板亦適用。至少於基板101之部份中通常具有相同之摻雜種類(為n型或p型),而底二極體區102有助於底二極體區102與基板101之間的良好電性接觸關係。
主動二極體區103之詳細結構可依照包括期望應用之多種參數而決定,於一情形中,主動二極體區103係由頂二極體區102與底二極體區104之接面(junction)所形成。於此情形中,較佳地改變接近接面之頂部區與底部區的摻雜濃度。於發光二極體(LED)內,主動區103則可包括經摻雜之膜層與可使得電子與電洞再結合並產生光子之未經摻雜量子井(undoped quantum wells)之多個膜層。於太陽能電池之另一範例中,主動二極體區103可包括適度之n型摻雜或適度之p型摻雜之半導體材料,以吸收入射光子並產生電子-電洞對。
對於熟悉此技藝者而言,形成二極體區之材料為習知的。典型的有用半導體材料係為:如矽、碳或鍺之IV族材料,或其合金,如碳化矽或矽鍺;II-VI族化合物(包括二元、三元與四元形態),例如由鋅、鎂、鈹或鎘之II族材料與如碲、硒或硫之VI族材料所形成之化合物,例如為ZnSe、ZnSTe或ZnMgSTe;以及III-V族化合物(包括二元、三元與四元形態),如由如銦、鋁或鎵之III族材料與如砷、磷、銻或氮之V族材料所組成之化合物,例如InP、GaAs、GaN、InAlAs、AlGaN、InAlGaAs等。熟悉此技藝者可以瞭解,可參照如能隙、晶格常數、摻質程度等期望條件而適度選擇與處理此些材料。
第4圖顯示了一半導體二極體之實施例。此二極體之結構適用於其內基板將劣化表現之裝置。於一發光二極體中,其包括如一矽基板之會吸收裝置內所產生之光線。於如第4圖所示之實施例中,則可移除此矽基板。
第5圖顯示了製造過程中之初步階段的結果。基礎結構為如矽晶圓之一基板1000,其表面較佳地具有(111)結晶方向,雖然亦可使用其他方向,例如可選擇(100)之其他結晶方向。基板1000可依照二極體基裝置(diode-based device)之形態而經過n型摻雜或p型摻雜。第一步驟為藉由化學氣相沈積或其他適當技術沈積如二氧化矽(SiO2
)或氮化矽(SiNx
)之一層介電材料於矽晶圓1000之上。於來自介電層之光線反射會形成問題之裝置中,則較佳地使用氮化矽,基由其折射率較為接近於常用之半導體材料。介電層之厚度通常為200-400奈米,但其可為更厚或更薄。
接著於介電材料1010之膜層內圖案化形成用於深寬比捕捉之開口,例如具有大體垂直側壁之溝槽1020,進而於溝槽內露出了矽晶圓1000之表面。藉由習知微影技術或藉由反應性離子蝕刻之兩種示範方法可圖案化形成一溝槽1020。為熟悉此技藝者所瞭解,基於此處的揭示情形,溝槽可為另一形狀之開口,例如為一孔洞、一凹口或環狀物。溝槽1020之寬度可相同或少於介電材料之厚度。如此條件係基於深寬比捕捉技術之原理,即溝槽1020之高度與溝槽1020之寬度之比例可大體大於或等於1以捕捉貫穿差排。關於上述技術之細節則揭露於申請中之第11/436,198號US專利申請案於於第11/852,078號US專利申請案中,在此以提及方式將之併入於本文中。以及揭露於於Park等人於Appl. Phys. Lett. 90,052113(2007)之文獻中,在此以提及方式將之併入於本文中。
於某些範例中,較佳地潔淨於溝槽1020之底部之矽基板1000的表面,以準備用於底二極體區的磊晶成長。一種適用於潔淨程序之範例則包括氧氣電漿蝕刻,請參照Park等人於Appl. Phys. Lett. 90,052113(2007)之文獻內的揭示。
第6圖顯示了後續幾個步驟之結果。首先成長底二極體區1030。用於底二極體區1030之半導體材料則依照元件形態而定。當用於太陽能電池時,底二極體區1030可為如InGaP。而當用於發光二極體時,底二極體區1030可為如GaN。亦可使得底二極體區採用包括化合物半導體材料之其他多種半導體材料,其具有用於如雷射或共振穿隧二極體之特性之有用特性。半導體材料的範例則如前所述。
於本發明,可以於磊晶成長時臨場地(in-situ)摻雜或藉由一離子佈植而離場地(ex-situ)摻雜底二極體區1030(較佳地摻雜底二極體區、主動二極體區與頂二極體區,且可於磊晶成長時臨場地摻雜之或藉由離子佈植而離場地摻雜之)。
於溝槽1020內之底部二極體區1030可稱為捕捉區1050,由於其捕捉了如貫穿差排1040之差排,貫穿差排1040產生於底二極體區1030與基板1000間之介面且向上朝向側壁傳播。第6圖內採用虛線顯示了貫穿差排1040。位於捕捉區1050上方之部分底二極體區1030則相對沒有缺陷。如此之低缺陷區域使得可於高品質、大區域、低成本之矽晶圓上製造出高品質化合物半導體裝置。對於某些材料而言,例如GaN、InN、AlN或上述材料之三元或四元組成物,差排密度需少於或等於108
/cm2
以用於裝置應用。對於如GaAs與InP之其他材料,通常需要更低的差排密度以用於裝置,例如少於或等於106
/cm2
。
繼續成長此底二極體區1030直到(a)材料溢出於溝槽以及(b)來自於相鄰溝槽之此材料接合成了一單一連續薄膜。通常較佳地可於進一步的製作中藉由化學機械研磨程序或依其他適當技術以平坦化底二極體區1030。後續步驟則為沈積主動二極體區1060以及底二極體區1070。於大多的實施例中,主動二極體區1060與頂二極體區1070具有相同或相似之晶格常數,此晶格常數相同於底二極體區1030。
第4圖顯示了最終步驟之結果。接合一握持基板1080至頂二極體區1070。於部分實施例中,較佳地平坦化頂部二極體1070以附著一高品質接合物至握持基板1080。於其他實施例中,則較佳地包括位於頂二極體區1070與握持晶圓1080間之一中間層以改善附著情形,最小化熱不匹配或相似特性。握持基板1080可為一發光二極體封裝固定物之一部。接合技術為習知技術,包括覆晶接合,其發光二極體之頂部連結於發光二極體封裝物之一表面。握持基板1080可為導電的,或其可包含導電元件以作為用於頂部二極體區1070之接觸物。接著藉由如研磨、化學回蝕刻、雷射剝離或上述方法之組合標準技術以移除矽基板1000。
最後,於底二極體區1030上形成一第一導電接觸物1090,以及於握持基板1080處形成一第二導電接觸物1100。於不同實施例中,導電接觸物之材料可為如銅、銀或鋁之導電金屬之條狀物,或為如氧化銦錫之相對透明導電氧化物之膜層。於發光二極體之應用中,位於底部之導電接觸物1100較佳地為如銀之一高反射性導電材料,其可反射內部產生之光線並使之自另一表面離開發光二極體。
熟悉半導體二極體製作技術之技藝者可知悉許多材料與方法可形成導電接觸物。第4圖中僅示了用於形成第一導電接觸物1090之一種方案,藉由移除介電層1010以露出底二極體區1030。在此,介電材料1010藉由如蝕刻之標準技術移除。於一發光二極體中,如第4圖所示之捕捉區1050可有效地粗糙化其表面,以降低光線之內部反射,以使得捕捉區1050的尺吋與間隔為正確的。
以下為依據本發明之實施例之適用於形成底、主動與頂二極體區之製程參數的範例。首先,形成基板與圖案化之介電層。採用依據本發明之下述實施例之示範性之製程參數以形成底、主動與頂二極體區,作為GaAs或AlGaAs基之二極體。
(A)底部二極體區(如1030)(如100-500 nm厚之GaAs膜層)
壓力:0.1 atm
前驅物:稀釋於氫氣中之三甲基鎵(trimethylgallium,TMG)與20%的砷化氫(arsine AsH3
),
溫度:720℃
N型:摻雜有矽
(B) 主動二極體區(如1060)(如用於載子限制之15 nm厚的AlGaAs膜層)
壓力:0.1 atm
前驅物:稀釋於氫氣中之三甲基鎵(trimethylgallium,TMG)、三甲基鋁(trimethylaluminium,TMA)與20%的砷化氫(arsineAsH3
)
溫度:850℃
N型:摻雜有矽
用於發光之GaAs量子井(10 nm厚)
壓力:0.1 atm
前驅物:稀釋於氫氣中之三甲基鎵(trimethylgallium,TMG)與20%的砷化氫(arsine AsH3
)
溫度:720℃
未經摻雜
用於載子限制之AlGaAs層(15 nm厚)
壓力:0.1 atm
前驅物:稀釋於氫氣中之三甲基鎵(trimethylgallium,TMG)、三甲基鋁(trimethylaluminium,TMA)與20%的砷化氫(arsine AsH3
)
溫度:850℃
P型:摻雜有鋅
(C) 頂二極體區(如1070)(如100-500 nm厚之GaAs膜層)
壓力:0.1 atm
前驅物:稀釋於氫氣中之三甲基鎵(trimethylgallium,TMG)與20%的砷化氫(arsine AsH3
)
溫度:720℃
P型:摻雜有鋅
依據本發明之第一實施例之用於GaN與InGaN基二極體之底、主動與頂二極體之示範性之預知製程步驟之成長條件(如化學氣相沈積),如下:
(A) 底二極體區(如1030)
GaN低溫緩衝物(如30 nm厚)
壓力:100 Torr
前驅物:稀釋於氫氣中之三甲基鎵(trimethylgallium,TMG)與氨氣(NH3
)溫度:530℃
N型:摻雜有矽
GaN高溫緩衝物(如500 nm厚)
壓力:100 Torr
前驅物:稀釋於氫氣中之三甲基鎵(trimethylgallium,TMG)與氨氣(NH3
)
溫度:1030℃
N型:摻雜有矽
(B) 主動二極體區(如1060)
用於發光之InGaN量子井層(如2 nm厚)
壓力:100 Torr
前驅物:稀釋於氫氣中之三甲基鎵(trimethylgallium,TMG)、三甲基鋁(trimethyindium,TMI)、氨氣
溫度:740℃
未經摻雜
用於載子限制之GaN阻障層(如15 nm厚)
壓力:100 Torr
前驅物:稀釋於氫氣中之三甲基鎵(trimethylgallium,TMG)、NH3
溫度:860℃
N型,摻雜有矽
(C) 頂二極體區(如1070): GaN之p-接觸層(如100nm厚)
壓力:100 Torr
前驅物:稀釋於氫氣中之三甲基鎵(trimethylgallium,TMG)與氨氣
溫度:950℃
P型:摻雜有鎂
如第4圖所示之包括了位於矽晶圓之上之半導體二極體由化合物半導體或其他晶格不匹配材料之第一實施例中,包括了下述元件:一底二極體區1030、一主動二極體區1060、一頂二極體區1070、一握持基板1080、一第一導電接觸物1090、一第二導電接觸物1100與一捕捉區1050,於其處可終止貫穿差排。
上述底二極體區1030、主動二極體區1060與頂二極體區1070可具有低缺陷密度(通常少於或等於5x 107
/每平方公分),其結果為可藉由深寬比捕捉而成長底二極體區1030而成為一接合膜層(coalesced film)。
請參照第7圖,顯示了依據上述第一實施例之裝置之製造方法。此方法包括:沈積一介電材料1010之膜層於一矽晶圓1000之表面;形成溝槽1020於介電材料1010之膜層內,以露出矽晶圓1000之表面,各溝槽1020具有大體垂直側壁,而各溝槽1020之高與寬之比例可大於或等於1;成長一半導體材料以形成一底二極體區1030,其填滿了溝槽1020並接合成一單一連續薄膜;成長一半導體材料於底二極體區1030上,以形成一主動二極體區1060;成長一半導體材料於主動二極體區1060上以形成一頂二極體區1070;結合一握持基板1080與頂部二極體區1070;移除矽基板1000;移除介電材料1010,以形成一第一導電接觸物1090於底二極體區1030之表面上;以及形成一第二導電接觸物1100於握持基板1080之表面上。
第8圖則總結了如第7圖所示方法之一變化情形,其中於沈積底二極體區之前,潔淨了於溝槽之底部之矽晶圓的表面。第9圖則總結了另一變化情形,其中於成長主動二極體區之前,先平坦化了底二極體區之表面。第10圖則總結了另一變化情形,其中於結合頂二極體區與握持基板之前,先平坦化了頂二極體區之表面。
其他實施例中則允許了採用由深寬比捕捉以形成接合膜層以形成氮化鎵基板。於本文中,例如於發光二極體工業中,”氮化鎵基板”之描述係指如習知之成長或結合於由非氮化鎵材質所形成之一基板上之一氮化鎵薄膜。發光二極體的製作通常自材料供應商處購入氮化鎵基板,並接著沈積額外之氮化鎵膜層及其他之材料,以製作發光二極體。典型之氮化鎵基板包括了沈積於一藍寶石或碳化矽基板上之一氮化鎵膜層。目前使用氮化鎵基板之世界性市場約每年300萬美元。
材料供應商通常沈積氮化鎵於氧化鋁(Al2
O3
)之上,由於此兩種材料具有一適當且良好的晶格匹配情形。然而,氮化鎵與氧化鋁具有不同熱膨脹係數。當發光二極體製造商於加熱氮化鎵/氧化鋁結構以沈積其他膜層時,上述之熱膨脹係數差異將造成了其結構的彎曲(bowing)。如此之彎曲造成了氧化鋁晶圓之部分沒有接觸到支撐座(suspector),即位於沈積腔體內之基板加熱器。其結果為,氧化鋁晶圓的溫度隨著其位置而改變。不均勻之氧化鋁晶圓溫度造成了膜層之組成與厚度的變化。其實際後果為商造商對於最終得到之發光二極體之發射波長的不易控制情形。
目前見有一種可解決或至少改善上述問題之氮化鎵基板的製造技術。此技術的出現使得可取得來自於一施體晶圓(donor wafer)之一氮化鎵薄膜,並將之結合於具有一熱膨脹係數相似於氮化鎵之一氧化鋁基板。施體晶圓通常為具有單晶氮化鎵之一晶圓。習知方法用於自施體晶圓取得氮化鎵薄膜係關於離子佈植與分離。製造商係佈植氫離子進入施體晶圓,以製造出一分裂平面(cleave plane),接著分割施體晶圓藉由回火之或藉由施加機械壓力。上述技術使得其可能分離多重薄膜自一施體晶圓處。
第11圖顯示了一第二實施例,其提供了一新穎之施體晶圓,適用於較單晶氮化鎵之一施體晶圓為低成本之製造。此方法起使於採用如具有(111)結晶方向之矽晶圓之一基板1000。然而,於部分實施例中,亦可採用如(100)之結晶方向之其他方向。基板1000可經過n摻雜或p摻雜。於基板1000之上沈積有介電材料1010之膜層。接著,形成具有大體垂直側壁之溝槽於介電材料1010之膜層內,進而露出矽晶圓1010之表面。於如第11圖所示之製造階段中,此些溝槽大體為下述之半導體材料1100所填滿。如前所述,為了促進貫穿差排的捕捉,各溝槽之寬度需少於或等於介電材料之厚度。亦可藉由前述技術而選擇性地潔淨位於溝槽底部內之矽基板1000之表面。
次一步驟為成長半導體材料1110(例如氮化鎵)之一膜層直至此材料溢出於溝槽,而來自於相鄰溝槽之此材料接合成了一單一連續薄膜。半導體材料之實施情形則如前所述。半導體材料1110填入於溝槽內之之該部係作為缺陷捕捉區1050,其捕捉了貫穿差排1040。高於捕捉區1050之半導體材料1110於成長時大體不具有貫穿差排。然而於其成長時位於相鄰溝槽接合處可能於部分之位置處形成有接合缺陷,但是其接合缺陷之密度極低(通常少於或等於5x 107
/cm2
)以使得此結構適用於實際製作。
第11圖顯示了一新穎施體晶圓,其可自膜層處產生多個半導體材料1110之薄膜。舉例來說,圖示之實施例可藉由離子佈植與剝落而作為提供多重氮化鎵膜層之來源,並接著將之接合至氮化鋁晶圓上。深寬比捕捉技術使得可於一較不昂貴之矽基板之施體晶圓上製造高品質之氮化鎵薄膜。
如第11圖所示之實施例中,施體晶圓主要包括下述元件:一半導體晶圓基板1000、包覆了矽晶圓基板1000之一介電材料1010之膜層、溝槽介電材料1010之膜層包括了露出了矽晶圓基板1000之表面之溝槽、此些溝槽具有大體垂直側壁、以及此些溝槽之高與寬的比例大於或等於1、半導體材料1110填入於溝槽內並溢出於溝槽以形成一單一連續膜層,以及位於溝槽內之捕捉區,其可使得貫穿差排1040為介電材料之側壁所攔截並於該處終止。
第12圖顯示了如第11圖所示之施體晶圓之一製造方法。包括以下步驟:
沈積一介電材料1010之膜層於一矽晶圓1000之表面上,形成溝槽於介電材料1010之膜層內,以露出矽晶圓1000之表面,各溝槽具有大體垂直側壁,以及各溝槽之高度與寬度的比例大於或等於1;以及成長如氮化鎵之一半導體材料1110之膜層以填入溝槽並接合成一單一連續膜層。
第13圖則總結了如第12圖所示之製造方法之一變化情形,其中於成長半導體材料1110之前,先潔淨了位於溝槽底部之矽晶圓基板1000的表面。第14圖則總結了如第12圖所示製造方法之另一變化情形,其包括了平坦化了半導體材料1110之表面。
接著描述如前所述之用於分離施體晶圓概念之一方法,以形成一氮化鎵基板,例如為結合於一氮化鋁晶圓之一高品質氮化鎵薄膜。其較佳地為形成接合於一基板材料之半導體材料之製造方法。
於製造出施體晶圓(如第11圖所示)後,第15圖顯示了後續之製造步驟:
使用如氫離子或氫離子與氦離子的組合,以離子佈植半導體材料1110之膜層以形成一分裂平面1120。接著採用習知技術結合半導體材料1110之膜層與握持基板1130,如第16圖所示。當半導體材料1110為氮化鎵時,通常用於握持基板1130之較佳材料為具有相似熱膨脹係數之一材料,例如為氮化鋁。
最終步驟為藉由回火或施加機械壓力自分裂平面1120分裂半導體材料1110之膜層,所得到之結果為如第17圖所示:
接合於一握持基板1130一半導體材料1110之膜層。當半導體材料1110之缺陷密度為低時(例如少於或等於5x107
/cm2
)時、或當於半導體材料1110與握持基板1130之間具有不匹配之晶格常數,且/或具有於半導體1110與握持晶圓1130之間似有接近之匹配熱膨脹時,上述結構特別有用。再次地,對於部分材料,如GaN、InN、AlN或上述材料之三元或四元組成物,當差排密度少於108
/cm2
才適用於裝置之應用。對於某些材料言而,如GaAs或InP,則需要更低之差排密度以適用於裝置,例如少於106
/cm2
。
第18圖總結了用於製造由半導體材料之膜層結合於一基板之前述方:
沈積一介電材料1010之膜層於矽晶圓1000之表面;形成溝槽於介電材料1010之內,以露出矽晶圓1000之表面,各溝槽具有大體垂直側壁,而各溝槽之高與寬的比例大於或等於1;成長半導體材料1110之一膜層於溝槽內並接合成一連續膜層;使用離子佈植半導體材料1110之膜層以製作出一分裂平面1120;接合握持基板1130與半導體材料1110之膜層;以及自分裂平面1120分裂半導體材料1110之膜層。
第19圖總結了如第18圖所示方法之一變化情形,其中於半導體材料1010沈積之前,先潔淨了位於溝槽底部之半導體晶圓1000之表面。第20圖則總結了如第18圖所示方法之又一變化情形,其中於佈植離子之前,先平坦化了半導體材料1110之表面。
於部分實施例中,由於相較於矽晶圓基板磊晶材料通常具有較大的熱膨脹係數,故藉由深寬比捕捉技術所成長之接合薄膜可能遭遇破裂之疑慮。當自成長溫度冷卻之後,形成之結構內之薄膜較基板更為收縮。如第21圖所示,於薄膜內之拉伸應變(tensile strain)導致了破裂1140。破裂1140將衝擊了如發光二極體或太陽能電池之裝置之表現與可靠度。
第22圖顯示了一新穎之解決方法:
製造凹洞(divot)1150於半導體材料之膜層內。可採用標準技術以形成此些凹洞,例如為微影、蝕刻或雷射剝離術。此些凹洞1150有效地限制了接合膜層的區域。其結果為,降低了於半導體材料內之熱導應變。當此些凹洞具有適當尺寸與間距時,其可允許半導體材料彈性地調和熱應力,且極大地降低或減少晶圓的彎曲情形。第23圖總結了藉由深寬比捕捉技術於一矽基板之上成長半導體材料之一接合膜層,以降低熱導應力之方法,包括:
沈積一介電材料1010之膜層於一矽晶圓1000之表面上;形成溝槽於介電材料1010之膜層內,以露出矽晶圓1000之表面,各溝槽具有大體垂直側壁,而各溝槽之高度與寬度的比例可大於或等於1;成長半導體材料1030之膜層以填入於溝槽內並接合成一單一連續薄膜;以及於半導體材料內形成凹洞1150。
於一實施例中,示範性之第一凹洞可沿著平行於如介於約0.1-1.0微米之一規則、不規則、規定的、週期的或間歇的間距之一第一方向而延伸。於此方法中,半導體材料可參照數個條狀物或片段而形成。相似於第一凹洞,一示範性之第二凹洞則可延伸於有別於(例如是垂直於)第一方向之一第二方向。於此情形中,半導體材料可製作成為數個島狀物。當第一凹洞與第二凹洞的圖案為規則且相等的,其所得到之島狀物可為正方形,然而亦可使用適用於此島狀物之其他已知形狀。於一實施例中,半導體材料可包括一底二極體區、一主動二極體區與一頂二極體區。
降低成長於一矽基板上藉由深寬比捕捉技術所形成之用於發光二極體之接合膜層內之熱導應變之一示範方法,包括:
沈積一介電材料1010之膜層於一矽晶圓1000之表面上;形成溝槽或孔洞於介電材料1010之膜層內,以露出具有未被圖案化之線狀物或片狀物之矽晶圓的表面,分別具有大體垂直側壁,而各溝槽之高度與寬度可足夠製作出之捕捉區;以及接著藉由標準技術(如金屬有機化學氣相沈積法)成長一接合底二極體區、一主動二極體區與一頂二極體區於符合未經圖案化之介電材料1010內之巷道內之圖案化區域內,以於未經圖案化之介電材料1010之巷道之上形成凹洞。
第23A圖顯示了數個步驟之結果。對應於位於半導體材料內凹洞以分離(例如切割或剝離)形成單一發光二極體1600及/或施行相對於第一實施例之額外步驟,以形成發光二極體之另一實施例。
於一實施例中於對應之發光二極體之各巷弄中之凹洞可佔據其長度或寬度尺寸之10-30%。示範的凹洞可具有相對於一鄰近發光二極體之頂面約為45度角之一傾斜側壁。或者,凹洞的側壁可使用一更大或更小角度,例如為30度、60度等。
於一III-N系統中,可於鬆散(relaxed)氮化鎵上成長用於發光二極體之主動區。舉例來說,如此之經鬆散之氮化鎵可為c平面(c plane)氮化鎵晶圓或為成長於藍寶石或碳化矽之一基板上大體經鬆散之c平面氮化鎵磊晶。然而,對於可見光發射情形而言,發射區域需維持銦之顯著分量。因此,位於一III-N系統內用於可見光發光二極體之發射區具有一或多個InGaN合金膜層,InGaN膜層相較於氮化鎵具有一較大晶格常數。為了避免或降低弄亂所伴隨之放鬆應變磊晶層之離子,可使於下方之氮化鎵層上之InGaN膜層仍維持應變(例如當其成長時,其具有大體相同如下方氮化鎵層之晶格常數)。再者,上述c平面III-N半導體材料係為極性物質(polar material),且於發射區之應變導致了顯著之極化區域(例如壓電極化,piezoelectric polarization),其會干擾裝置表現。舉例來說,其可劣化裝置/發射效率或造成發射光之波長的偏移。
第23B圖顯示了依據另一實施例之用於發光二極體之一示範性二極體結構。請參照第23B圖,至少鄰近於基板之一底二極體區之一部包括了InGaN(以取代GaN)。此底部二極體區內之InGaN可為採用深寬比捕捉技術形成之具有較低或經控制之缺陷密度之一鬆散層。如此底二極體區之InGaN可為具有顯著降低應變之發射區域之一平台(如發光二極體之發光區)。舉例來說,用於主動二極體區(例如具有低應變或沒有應變之InGaN)與頂部二極體區之後續成長可導致了於發射區內之顯著降低應變。如第23B圖所示,底二極體區1502係為經鬆散之N型InGaN位於並部分地於一缺陷捕捉區1504內,一主動二極體區1512則包括了AlGaN阻障區1506(例如具有等同底部二極體區晶格空間)、一降低應變InGaN發射區1508與一AlGaN阻障區1510(例如具有等同於發射區之晶格空間)。於主動二極體區1512之上形成有一頂二極體區1514,其材質例如為經鬆散之P型InGaN。於第23B圖中,基板可為一矽基板1500,且可適度的增加接觸了上部/頂部或下部/底部二極體區之導電接觸物(如前所述結構)。
發光二極體的製作可藉由於一單一封裝物或模組內安裝不同材料之半導體晶片以製作出單晶片方案。此技術使得其可結合不同色彩以形成白光。
研究者已發展出高效率太陽能電池之多晶片方案,其藉由於一單一封裝物或模組內安裝由不同材料所製成之半導體晶片。其應用了”分離光譜(split spectrum)”方法,其將太陽能光譜之一部導向至晶片處,以最佳化於之該部之該光譜。
於前述之兩實施例中,安裝與封裝多重晶片之成本可為極高。因此本發明提供了一種單晶片方案,其較為不昂貴。基於圖示之目的,在此僅描述了具有三個不同之單一二極體之單一晶片。
第24圖顯示了第一部份之步驟。沈積一第一介電材料1010之膜層於一矽基板1000上。接著形成溝槽1160於第一介電材料1010之膜層之第一區內,其具有大體垂直側壁。各溝槽露出該矽晶圓1000之表面。各溝槽之寬度可相同於或少於介電材料之厚度,以使得溝槽可捕捉差排缺陷。
接著可藉由前述方法而選擇性地潔淨位於溝槽1160之底部之矽基板1000之表面。
接著遮蔽於所有位置之結構的頂面,除了二極體裝置1195之區域。可成長底二極體區1170,於溝槽填入半導體材料並接合成單一連續薄膜,如第25圖所示,示範性半導體材料則如前所示。貫穿差排形成於底二極體區1170與矽基板1000之間之介面處。貫穿差排向上朝向一45度角傳播,而為溝槽之側壁所攔截並終止於此捕捉區內。
此時,可平坦化底二極體區1170。
接著成長一半導體材料膜層,以形成主動二極體區1180,以及成長另一半導體材料以形成頂二極體區1190。同時,底二極體區1170、主動二極體區1180與頂二極體區1190組成了第一(#1)二極體裝置1195。
接著沈積一第二介電材料1200之膜層。舉例來說,當第一介電材料為SiO2
時,第二介電材料可為SiNx
。藉由濕蝕刻或乾蝕刻選擇性地自所有區域移除第二介電材料1200除了,包括二極體裝置元件1之區域,留下如第26圖所示結構。
接著遮蔽所有位置處之結構,除了第二(#2)二極體裝置(1240)處之結構。於後續步驟中,藉由形成#1二極體裝置之相同步驟以形成第二(#2)二極體裝置(1240),進而得到了如第27圖所示之結構。如第27圖所示,一底二極體區1210、一主動二極體區1220與一頂二極體區1230組成了#2二極體裝置(1240)。
沈積另一第二介電材料1200之膜層,以覆蓋二極體裝置構件2(1240)。接著藉由濕蝕刻或乾蝕刻選擇性地移除包括了第三(#3)二極體裝置(1280)之區域的第二介電材料1200之膜層。
接著遮蔽所有區域,除了#3二極體裝置(1280)之區域,並藉由相同用於形成#1二極體裝置(1195)與#2二極體裝置(1240)之步驟製作#3二極體裝置(1280)。如此形成了如第28圖所示之結構。如第28圖所示,底二極體區1250、主動二極體區1260與頂二極體區1270形成了#3二極體裝置構件。
最後,採用第二介電材料1200覆蓋#3二極體裝置,並圖案化形成通過第二介電材料1200之接觸介層物(contact vias,未顯示),並沈積各別之導電接觸物1290於各二極體裝置之頂部。以及形成一底導電接觸物(1300)於支撐基板1000之上,其較佳地但非必要地為各裝置所共用。
第29圖顯示了最終結果。不同二極體裝置可包括用於形成頂、主動與底二極體區等構件之不同組的半導體材料。於各二極體裝置中,材料之能隙經過設計以發射出所期望之光線(於單一的二極體中)或吸收期望頻率之光線(於太陽能電池中)。此些實施例代表了於單一晶片之上採用相對不昂貴方式而形成了多個二極體裝置。
總而言之,包括複數個二極體裝置之單晶片,包括下述元件:
一矽晶圓基板1000、覆蓋矽晶圓基板1000之一第一介電材料1010之膜層、第一介電材料1010之膜層露出了矽晶圓基板1000之表面包括了溝槽1160,此些溝槽1160具有大體垂直側壁,而此些溝槽1160之高與寬的比例大於或等於1、數個二極體裝置(至少為三個裝置1995、1240、1280)分別包括填入於溝槽1160且位於第一介電材料1010之膜層一部內之一半導體材料,其溢出於溝槽1160以形成一底二極體區(1170、1210、1250),用於捕捉貫穿差排位於溝槽1160內之一捕捉區、一主動二極體區(1180、1220、1260)及一頂二極體區(1195、1240、1280)、頂部導電接觸物(1290)與底部導電接觸物(1300)。
第30圖總結了如第29圖所示結構之一製造方法。此方法可於單一晶片上製造數個二極體裝置,包括下列步驟:沈積一第一介電材料1010之膜層於一矽晶圓1000的表面上;形成溝槽1160於第一介電材料1010的膜層內,以露出矽晶圓1000之表面,各溝槽1160具有大體垂直側壁,而各溝槽1160的高與寬比例大於或等於1;遮蔽#1二極體裝置1(1195)以外所有位置處之結構;採用以下步驟製作#1二極體裝置:成長一半導體材料之膜層,其填入於溝槽內、溢出溝槽且接合成具有單一連續薄膜形態之一底二極體區1170;成長一半導體材料以形成一主動區1180;以及成長一半導體材料以形成一頂二極體區1190;沈積一第二介電材料(1200)之膜層;選擇性地移除用於設置#1二極體裝置(1195)以外所有區域除之第二介電材料(1200);遮蔽#2二極體裝置(1240)所有位置以外之所有位置之結構;藉由形成#1二極體裝置(1195)之相同步驟形成#2二極體裝置(1240);沈積第二介電材料(1200)以覆蓋#2二極體裝置(1240);選擇性地移除用於設置#3二極體裝置(1280)所在位置區域之第二介電材料(1200);遮蔽設置#3二極體裝置3(1280)所在位置以外所有位置之結構;利用製作#1二極體裝置(1195)與#2二極體裝置(1240)之相同步驟製造#3二極體裝置(1280);沈積一第二介電材料(1200)以覆蓋#3二極體裝置(1280);形成圖案化之接觸介層物,穿過第二介電材料1280;形成頂導電接觸物(1290)至#1二極體裝置、#2二極體裝置2與#3二極體裝置;以及形成為以上三個二極體所共用之一底導電接觸物1300。
可以理解的是,可以的話,可於單一晶片之上形成任何數量之二極體,其唯一限制為所能使用之空間。
本發明之實施例中係採用溝槽之描述以形成捕捉區,然而亦可使用如凹口之具有可捕捉缺陷之足夠剖面之其他結構,且於此處可稱之為溝槽。
本發明之應用提供了可用於或藉由磊晶成長或相似情形所形成之多個方法、結構或裝置。舉例來說示範之適當磊晶成長系統可為單一晶圓或多晶圓之批次反應器。亦可使用不同化學氣相沈積技術。於製造應用中之常用於體積磊晶(volume epitaxy)之適當的化學氣相沈積系統包括如由德國Aixtron提供之Aixtron 2600多晶圓系統;由應用材料所產製之EPI CENTURA單晶片磊晶反應器;或由荷蘭ASM國際所產製之EPSILON單晶圓多重腔體系統。
於說明書中關於”一實施例”、”一實施例”、”示範性之實施例”、”另一實施例”等描述意謂著於本發明之至少一實施例中所包括之一特定構件、結構或特性。於說明書內不同處之上述描述的出現並非指同一實施例。再者,當於任一實施例描述了相關之一特殊構件、結構、特性時,可以理解的是熟悉此技藝者可瞭解如此之特徵、結構或特性亦可用於其他之實施例。再者,為了方便瞭解,特定方法步驟可採用分隔步驟表現,然而此些分隔步驟依照其表現並不會限制其順序。此即為部分步驟可依照其他順序、或同時的施行。此外,示範性圖表顯示了依據本發明之實施例不同方法。可於此描述如此之示範性方法的實施例並提供了對應之裝置實施例,然而此些方法實施例並未用於限制本發明。
雖然本發明繪示了並描述了之部分實施例,可以理解的是熟悉此技藝者可依照本發明之精神與原則而針對此些實施例進行變更。前述之實施例便視為所有方面之圖示情形而非於此用於限制本發明。本發明之範疇因此依照申請中專利範圍所限定,而非前述之描述。於本說明書中,”較佳地”之描述係意謂著”較佳地,但非用以加以限制”。申請專利範圍內之描述依照本發明之概念而採用其最大解釋範圍。舉例來說,”耦接於”及”連接”等描述係採用以解說直接與非直接連接與耦合情形。於另一範例中,”具有”與”包括”,其相似描述可與”包括”相同(即上述描述皆視為開放性描述),僅”由...組成”與”實質上由...組成”可視為”封閉型”描述。
本發明之較佳實施例包括了一光電裝置,包括:
一基板;一介電材料,包括兩個或更多個開口露出基板之一部,此兩個或兩個以上之開口分別具有至少為1之一深寬比;一底部二極體材料,包括晶格不相稱於該基板之一化合物半導體材料,且其中該化合物半導體材料佔據了該兩個或兩個以上之開口並於該兩個或兩個以上之開口之上接合成一底二極體區域;一頂二極體材料;以及一主動二極體區,位於該頂部二極體材料與該底部二極體材料之間。此基板係擇自由矽、藍寶石與碳化矽所組成之族群。此基板為具有一結晶方向為(111)或(100)之一單晶矽晶圓。此主動二極體區包括由該頂部二極體材料與該底部二極體材料之接面所形成之一p-n接面。此主動二極體區包括不同於該頂部二極體材料與該底部二極體材料之一材料,而該主動二極體材料構成了位於該頂部二極體材料與底部二極體材料間之一p-i-n接面之一本徵區。此主動二極體區包括複數個多重量子井,形成於該頂部二極體材料與該底部二極體材料之間。此介電材料包括實質上擇自由二氧化矽、氮化矽、氮氧化矽、鉿之氧化物、鉿之矽化物、鋯之氧化物、鋯之矽化物及其組合之一材料。此開口為於兩平行軸向上具有至少為1之一深寬比之一孔洞。此半導體材料擇自由實質上包括一III-V族化合物、一II-VI族化合物、一IV族合金以及其組合物所組成之族群。此底部二極體材料包括一n型摻質,而該頂部二極體材料包括一p型摻質。上述裝置更包括一接觸物,形成於該頂部二極體區之上。及更包括一第二接觸物形成並鄰近於該基板。
本發明之其他較佳實施例可包括一種光電裝置,包括:
一基板;以及一光電二極體,包括:一第一區,鄰近該基板之一第一頂面;一第二區,鄰近該第一區;以及一主動區,介於該第一區與該第二區之間,其中該第二區包括鄰近於該主動區之一表面,該表面大體平行於該基板之該頂面;以及該第二區包括與該主動區相分隔之至少一缺陷捕捉區,該缺陷捕捉區包括延伸自該基板之該頂面之一表面。該第一區之一表面係連結於一握持基板。該握持基板連結有一中間層,該中間層位於該第一區與該握持基板之間。該握持晶圓包括電性連結於該第一區之一導體。上述裝置更包括一接觸物,連結於該握持基板並電性連結於該第一二極體區。
本發明之其他較佳實施例包括一種光電裝置之製造方法。上述方法包括:沈積一第一介電材料層於一基板之上;圖案化該第一介電材料層以於其內形成兩個或兩個以上之開口,露出該基板之該表面之部分,該兩個或兩個以上之開口具有至少為1之深寬比;藉由成長晶格不相稱於該基板之一化合物半導體材料於該兩個或兩個以上之開口內並使得該化合物半導體材料填滿該兩個或兩個以上之開口並於該兩個或兩個以上開口之上結合成一連續膜層,以形成一底部二極體區;形成一主動二極體區於該底部二極體區之上;以及形成一頂部二極體區於該主動二極體區之上。上述方法更包括連結一握持晶圓至該頂部二極體區;以及移除該基板。
本發明之另一較佳實施例可提供一光電裝置,其具有一底二極體區,包括兩個或兩個以上之差排捕捉區且包括一化合物半導體材料、一主動二極體區、一頂二極體區、一握持基板、相連於握持基板之一第一導電接觸物與相連於底二極體區之一第二導電接觸物。
本發明之另一較佳實施例提供了一種光電裝置之製造方法,包括沈積一介電材料之膜層於一基板上,形成兩個或兩個以上開口於介電材料內以露出基板之表面,此兩個或兩個以上開口具有至少為1之深寬比,形成一底部二極體區藉由成長一化合物半導體材料晶格不匹配於基板於此兩個或兩個以上開口內並使得化合物半導體填入於兩個或兩個以上開口並相連於其上以形成一連續膜層,形成一主動二極體區位於底部二極體區之上,形成一頂二極體區位於主動二極體區之上,接合一握持晶圓與頂二極體區,移除基板移除介電材料,接觸第一導電接觸物與該握持基板與接觸一第二電性接觸物與底部二極體區。
本發明另一較佳實施例包括了用於製造包括接合於一基板之一半導體材料之一製造方法。此方法可包括沈積一介電材料之膜層於一基板上,形成兩個或更多開口於介電材料內以露出基板之表面的部分,此兩個或更多開口具有至少為1之深寬比,成長一化合物半導體材料晶格不匹配於基板於兩個或更多開口內並使得其填入於其中並接合成一連續膜層,佈植離子進入半導體材料以形成一分裂平面,接合一握持基板與半導體材料以及自該分裂平面處分離半導體材料。
於某些方面,較佳實施例提供了包括了數個分離之光電裝置形成於其上之一晶片。此晶片可包括一基板、覆蓋該基板且具有數個具有深寬比至少為1之開口位於其內之一第一介電材料之膜層,複數個分離之光電裝置,各光電裝置包括(i)不匹配於基板之一半導體材料膜層,佔據兩個開口且接合於開口之上以形成單一底二極體區;(ii)一主動二極體區;及(iii)一頂部二極體區,一第二介電材料層覆蓋該些分離光電裝置,至少一頂導電接觸物與至少一底導電接觸物。
用於製作包括複數個分離之光電裝置於其上之一晶片之另一較佳方法包括:
沈積一介電材料之膜層於一基板上,形成第一組開口於介電材料內以露出基板之表面,該第一組開口具有至少為1之深寬比,形成一第一底二極體區,其藉由成長一半導體材料之膜層晶格不匹配於基板於第一組開口內並使得半導體材料填滿第一組開口並於第一組開口之上接合成為一連續膜層,形成一第一主動二極體區於第一底二極體區上,形成第一頂二極體區於第一主動二極體區之上,成長一介電材料層以覆蓋該第一底二極體區、該第一主動二極體區、與該第一頂二極體區,於該介電材料之膜層內圖案化形成一第二組開口具有深寬比至少為1,形成一第二底部二極體區藉由於第二開口內成長晶格不匹配於基板之一半導體材料之膜層並使得半導體材料填滿第二組開口並於第二組開口之上接合成為一連續膜層,形成一第二主動二極體區於第一底部二極體區上,形成第二頂二極體區於第二主動二極體區之上,成長一介電材料層以覆蓋該第二底二極體區、該第二主動二極體區、與該第二頂二極體區。此方法更包括接觸一第一導電接觸物與基板,接觸一第二導電接觸物與第一部電極區、以及接觸一第三導電接觸物與一第二頂電極區。
雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此項技藝者,在不脫離本發明之精神和範圍內,當可作更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10...矽晶圓
20...介電材料
30...晶格不匹配半導體
40...貫穿差排
50...捕捉區
60...無缺陷區
70...單一連續膜層
80...接合缺陷
101、1000...基板
105、106...導電接觸物
1010...介電材料
1020...溝槽
102、1030、1170、1210、1250、1502‧‧‧底二極體區
1040‧‧‧貫穿差排
1050‧‧‧捕捉區
103、1060、1180、1220、1260、1512‧‧‧主動二極體區
104、1070、1190、1230、1270、1514‧‧‧頂二極體區
1080‧‧‧握持晶圓
1090‧‧‧第一電性接觸物
1100‧‧‧第二電性接觸物
1110‧‧‧半導體材料
1120‧‧‧分裂平面
1130‧‧‧握持基板
1140‧‧‧破裂
1150‧‧‧凹洞
1160‧‧‧溝槽
1195、1240、1280‧‧‧二極體裝置
1200‧‧‧第二介電材料
1290‧‧‧接觸物
1300‧‧‧底電性接觸物
1500‧‧‧矽基板
1504‧‧‧缺陷捕捉區
1506‧‧‧AlGaN阻障區
1508‧‧‧InGaN發射區
1510‧‧‧AlGaN阻障區
第1圖顯示了深寬比捕捉技術之原理,以及於矽晶圓上沈積高品質化合物半導體或其他之晶格不相稱半導體之方法;
第2圖顯示了藉由深寬比捕捉技術以於矽晶圓上成長高品質之化合物半導體或其他晶格不相稱半導體之薄膜之技術;
第3圖顯示了半導體二極體之一結構;
第4圖顯示了依據本發明一第一實施例之一半導體二極體;
第5圖與第6圖顯示了用於製造第一實施例之半導體二極體之連續階段;
第7圖為一流程圖,顯示了依據本發明之第一實施例之一製造方法;
第8、9、10圖顯示了如第7圖所示之製造方法的變化;
第11圖顯示了依據本發明之一第二實施例之一施體晶圓;
第12圖為一流程圖,顯示依據本發明之第二實施例之一施體晶圓之一製造方法;
第13圖與第14圖顯示了第12圖內之製造方法的變化;
第15-17圖顯示了於利用一施體晶圓以形成一氮化鎵基板之一方法中之不同步驟;
第18圖為一流程圖,顯示了如第15-17圖所示之方法;
第19-20圖顯示了如第18圖所示方法之變化情形;
第21圖顯示了可能發生於磊晶成長膜層內之破裂情形;
第22圖顯示了藉由深寬比捕捉而降低位於成長於一矽基板上之半導體材料之一結合膜層內之熱應力之方法;
第23圖為一流程圖,顯示了如第22圖內所示方法;
第23A圖顯示了一發光二極體製程內之中間情形;
第23B顯示了依據本發明另一實施例之一發光二極體之二極體結構;
第24-28圖顯示了依據本發明之一第三實施例內包括複數個二極體裝置之一單晶片之製造步驟;
第29圖顯示了依據本發明之第三實施例所製造出之一結構;以及
第30A及30B圖為一流程圖,顯示了依據本發明之第三實施例之製造方法。
1030‧‧‧底二極體區
1040‧‧‧貫穿差排
1050‧‧‧捕捉區
1060‧‧‧主動二極體區
1070‧‧‧頂二極體區
1080‧‧‧握持晶圓
1090‧‧‧第一導電接觸物
1100‧‧‧第二導電接觸物
Claims (3)
- 一種光電裝置之製造方法,包括:沈積一第一介電材料層於一基板之上;圖案化該第一介電材料層以於其內形成兩個或兩個以上之開口,以露出該基板之該表面之部分,該兩個或兩個以上之開口具有至少為1之深寬比;藉由成長晶格不相稱於該基板之一化合物半導體材料於該兩個或兩個以上之開口內,使得該化合物半導體材料填滿該兩個或兩個以上之開口以及於該兩個或兩個以上開口之上接合成一連續膜層,以形成一底二極體區;形成一主動二極體區於該底部二極體區之上;以及形成一頂二極體區於該主動二極體區之上。
- 如申請專利範圍第1項所述之光電裝置之製造方法,更包括:接合一握持晶圓至該頂部二極體區;以及移除該基板。
- 如申請專利範圍第1項所述之光電裝置之製造方法,更包括:佈植離子進入該半導體材料以製造出一分裂平面;接合一握持基板至該半導體材料;以及自該分裂平面處分裂該半導體材料之膜層。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/684,499 US8304805B2 (en) | 2009-01-09 | 2010-01-08 | Semiconductor diodes fabricated by aspect ratio trapping with coalesced films |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201125162A TW201125162A (en) | 2011-07-16 |
TWI427830B true TWI427830B (zh) | 2014-02-21 |
Family
ID=43836833
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW99122432A TWI427830B (zh) | 2010-01-08 | 2010-07-08 | 光電裝置之製造方法 |
Country Status (7)
Country | Link |
---|---|
US (4) | US8304805B2 (zh) |
EP (1) | EP2343742B1 (zh) |
JP (3) | JP5399335B2 (zh) |
KR (1) | KR20110081742A (zh) |
CN (1) | CN102122675B (zh) |
SG (1) | SG173245A1 (zh) |
TW (1) | TWI427830B (zh) |
Families Citing this family (62)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9153645B2 (en) | 2005-05-17 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
WO2007112066A2 (en) | 2006-03-24 | 2007-10-04 | Amberwave Systems Corporation | Lattice-mismatched semiconductor structures and related methods for device fabrication |
WO2008030574A1 (en) | 2006-09-07 | 2008-03-13 | Amberwave Systems Corporation | Defect reduction using aspect ratio trapping |
WO2008039534A2 (en) | 2006-09-27 | 2008-04-03 | Amberwave Systems Corporation | Quantum tunneling devices and circuits with lattice- mismatched semiconductor structures |
WO2008051503A2 (en) | 2006-10-19 | 2008-05-02 | Amberwave Systems Corporation | Light-emitter-based devices with lattice-mismatched semiconductor structures |
US9508890B2 (en) | 2007-04-09 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photovoltaics on silicon |
US7825328B2 (en) | 2007-04-09 | 2010-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride-based multi-junction solar cell modules and methods for making the same |
US8304805B2 (en) * | 2009-01-09 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor diodes fabricated by aspect ratio trapping with coalesced films |
US8237151B2 (en) | 2009-01-09 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
US8329541B2 (en) | 2007-06-15 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | InP-based transistor fabrication |
CN101884117B (zh) | 2007-09-07 | 2013-10-02 | 台湾积体电路制造股份有限公司 | 多结太阳能电池 |
US8183667B2 (en) | 2008-06-03 | 2012-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial growth of crystalline material |
US8274097B2 (en) | 2008-07-01 | 2012-09-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
US8981427B2 (en) | 2008-07-15 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polishing of small composite semiconductor materials |
US8034697B2 (en) | 2008-09-19 | 2011-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of devices by epitaxial layer overgrowth |
US20100072515A1 (en) | 2008-09-19 | 2010-03-25 | Amberwave Systems Corporation | Fabrication and structures of crystalline material |
US8253211B2 (en) | 2008-09-24 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor sensor structures with reduced dislocation defect densities |
WO2010114956A1 (en) | 2009-04-02 | 2010-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices formed from a non-polar plane of a crystalline material and method of making the same |
CN102790006B (zh) * | 2011-05-17 | 2014-09-17 | 中国科学院微电子研究所 | 半导体结构及其制作方法 |
US8564085B2 (en) * | 2011-07-18 | 2013-10-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | CMOS image sensor structure |
US8749015B2 (en) | 2011-11-17 | 2014-06-10 | Avogy, Inc. | Method and system for fabricating floating guard rings in GaN materials |
US9018517B2 (en) | 2011-11-07 | 2015-04-28 | International Business Machines Corporation | Silicon heterojunction photovoltaic device with wide band gap emitter |
US9323010B2 (en) * | 2012-01-10 | 2016-04-26 | Invensas Corporation | Structures formed using monocrystalline silicon and/or other materials for optical and other applications |
US9653639B2 (en) | 2012-02-07 | 2017-05-16 | Apic Corporation | Laser using locally strained germanium on silicon for opto-electronic applications |
EP2629320B1 (en) * | 2012-02-15 | 2018-10-17 | IMEC vzw | Mask structure and method for defect-free heteroepitaxial deposition |
US9257339B2 (en) * | 2012-05-04 | 2016-02-09 | Silicon Genesis Corporation | Techniques for forming optoelectronic devices |
CN104541379B (zh) * | 2012-06-22 | 2017-09-12 | 埃皮沃克斯股份有限公司 | 半导体基多结光伏装置的制造 |
DE102012107001A1 (de) * | 2012-07-31 | 2014-02-06 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines optoelektronischen Halbleiterchips und optoelektronischer Halbleiterchip |
US8669135B2 (en) | 2012-08-10 | 2014-03-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | System and method for fabricating a 3D image sensor structure |
JP5881560B2 (ja) * | 2012-08-30 | 2016-03-09 | 株式会社東芝 | 半導体発光装置及びその製造方法 |
JP6004429B2 (ja) * | 2012-09-10 | 2016-10-05 | 国立研究開発法人産業技術総合研究所 | 単結晶SiGe層の製造方法及びそれを用いた太陽電池 |
TWI565094B (zh) * | 2012-11-15 | 2017-01-01 | 財團法人工業技術研究院 | 氮化物半導體結構 |
US10164038B2 (en) | 2013-01-30 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of implanting dopants into a group III-nitride structure and device formed |
WO2014136749A1 (ja) * | 2013-03-07 | 2014-09-12 | 学校法人名城大学 | 窒化物半導体結晶及びその作製方法 |
US8916445B1 (en) | 2013-08-16 | 2014-12-23 | International Business Machines Corporation | Semiconductor devices and methods of manufacture |
GB2520399B (en) * | 2013-11-01 | 2017-10-25 | Ibm | Silicon heterojunction photovoltaic device with non-crystalline wide band gap emitter |
KR101531875B1 (ko) * | 2013-12-27 | 2015-06-29 | (재)한국나노기술원 | 트랩홀에 의한 계단형 트렌치를 이용하여 실리콘 기판 상에 대면적 화합물 반도체 소자를 제조하는 방법 |
KR102122361B1 (ko) | 2013-12-27 | 2020-06-15 | 삼성전자주식회사 | 플립칩 엘이디 패키지 기판 및 플립칩 엘이디 패키지 구조 |
KR102168969B1 (ko) | 2014-02-28 | 2020-10-22 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US20160284957A1 (en) * | 2015-03-23 | 2016-09-29 | Toshiba Corporation | REFLECTIVE CONTACT FOR GaN-BASED LEDS |
US9401583B1 (en) | 2015-03-30 | 2016-07-26 | International Business Machines Corporation | Laser structure on silicon using aspect ratio trapping growth |
US9754968B2 (en) * | 2015-04-30 | 2017-09-05 | International Business Machines Corporation | Structure and method to form III-V, Ge and SiGe fins on insulator |
US9917414B2 (en) | 2015-07-15 | 2018-03-13 | International Business Machines Corporation | Monolithic nanophotonic device on a semiconductor substrate |
TW201718930A (zh) * | 2015-09-04 | 2017-06-01 | 南洋理工大學 | 具有經減低之線差排密度的基材之製造方法 |
US9646841B1 (en) | 2015-10-14 | 2017-05-09 | International Business Machines Corporation | Group III arsenide material smoothing and chemical mechanical planarization processes |
US9646842B1 (en) | 2015-10-14 | 2017-05-09 | International Business Machines Corporation | Germanium smoothing and chemical mechanical planarization processes |
US9916985B2 (en) | 2015-10-14 | 2018-03-13 | International Business Machines Corporation | Indium phosphide smoothing and chemical mechanical planarization processes |
EP3170574B1 (de) | 2015-11-19 | 2022-07-13 | Heraeus Deutschland GmbH & Co. KG | Verfahren zur herstellung einer hülse für eine elektrode für medizinische anwendungen |
JP6706414B2 (ja) * | 2015-11-27 | 2020-06-10 | 国立研究開発法人情報通信研究機構 | Ge単結晶薄膜の製造方法及び光デバイス |
CN107132942A (zh) * | 2016-02-26 | 2017-09-05 | 鸿富锦精密工业(深圳)有限公司 | 触控显示装置 |
US9793113B2 (en) * | 2016-03-21 | 2017-10-17 | Globalfoundries Inc. | Semiconductor structure having insulator pillars and semiconductor material on substrate |
TWI638453B (zh) * | 2016-03-25 | 2018-10-11 | 晶元光電股份有限公司 | 半導體元件及其製造方法 |
TWI607582B (zh) | 2016-03-25 | 2017-12-01 | 晶元光電股份有限公司 | 半導體元件及其製造方法 |
US9966466B2 (en) * | 2016-08-08 | 2018-05-08 | Globalfoundries Inc. | Semiconductor-on-insulator wafer, semiconductor structure including a transistor, and methods for the formation and operation thereof |
US9620590B1 (en) * | 2016-09-20 | 2017-04-11 | International Business Machines Corporation | Nanosheet channel-to-source and drain isolation |
DE102017002935A1 (de) * | 2017-03-24 | 2018-09-27 | 3-5 Power Electronics GmbH | III-V-Halbleiterdiode |
US10720520B2 (en) * | 2017-06-21 | 2020-07-21 | Infineon Technologies Austria Ag | Method of controlling wafer bow in a type III-V semiconductor device |
CN107591464B (zh) * | 2017-11-08 | 2019-02-12 | 宁波高新区斯汀环保科技有限公司 | 一种多功能曲面显示屏用led材料及其制造方法 |
CN111435679B (zh) * | 2019-01-14 | 2023-06-13 | 联华电子股份有限公司 | 具有非对称应变源极/漏极结构的半导体元件其制作方法 |
EP3806152B1 (en) | 2019-10-11 | 2022-08-24 | Imec VZW | A method of forming a semiconductor device structure |
US11742203B2 (en) | 2020-02-26 | 2023-08-29 | The Hong Kong University Of Science And Technology | Method for growing III-V compound semiconductor thin films on silicon-on-insulators |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080093622A1 (en) * | 2006-10-19 | 2008-04-24 | Amberwave Systems Corporation | Light-Emitter-Based Devices with Lattice-Mismatched Semiconductor Structures |
TW200828465A (en) * | 2006-12-21 | 2008-07-01 | Taiwan Semiconductor Mfg | Methods for fabricating semiconductor structures and probing dies |
Family Cites Families (410)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US1310808A (en) | 1919-07-22 | Planoqilaph co | ||
US4307510A (en) | 1980-03-12 | 1981-12-29 | The United States Of America As Represented By The Administrator Of The National Aeronautics & Space Administration | Computer circuit card puller |
WO1981002948A1 (en) * | 1980-04-10 | 1981-10-15 | Massachusetts Inst Technology | Methods of producing sheets of crystalline material and devices made therefrom |
US4322253A (en) * | 1980-04-30 | 1982-03-30 | Rca Corporation | Method of making selective crystalline silicon regions containing entrapped hydrogen by laser treatment |
US4370510A (en) * | 1980-09-26 | 1983-01-25 | California Institute Of Technology | Gallium arsenide single crystal solar cell structure and method of making |
US4651179A (en) * | 1983-01-21 | 1987-03-17 | Rca Corporation | Low resistance gallium arsenide field effect transistor |
US4545109A (en) | 1983-01-21 | 1985-10-08 | Rca Corporation | Method of making a gallium arsenide field effect transistor |
US5091333A (en) * | 1983-09-12 | 1992-02-25 | Massachusetts Institute Of Technology | Reducing dislocations in semiconductors utilizing repeated thermal cycling during multistage epitaxial growth |
US4860081A (en) | 1984-06-28 | 1989-08-22 | Gte Laboratories Incorporated | Semiconductor integrated circuit structure with insulative partitions |
US4551394A (en) | 1984-11-26 | 1985-11-05 | Honeywell Inc. | Integrated three-dimensional localized epitaxial growth of Si with localized overgrowth of GaAs |
CA1292550C (en) | 1985-09-03 | 1991-11-26 | Masayoshi Umeno | Epitaxial gallium arsenide semiconductor wafer and method of producing the same |
JPS62188386A (ja) * | 1986-02-14 | 1987-08-17 | Omron Tateisi Electronics Co | 半導体発光素子 |
US4774205A (en) | 1986-06-13 | 1988-09-27 | Massachusetts Institute Of Technology | Monolithic integration of silicon and gallium arsenide devices |
JPS6381855A (ja) | 1986-09-25 | 1988-04-12 | Mitsubishi Electric Corp | ヘテロ接合バイポ−ラトランジスタの製造方法 |
US5236546A (en) | 1987-01-26 | 1993-08-17 | Canon Kabushiki Kaisha | Process for producing crystal article |
US5269876A (en) | 1987-01-26 | 1993-12-14 | Canon Kabushiki Kaisha | Process for producing crystal article |
US5281283A (en) * | 1987-03-26 | 1994-01-25 | Canon Kabushiki Kaisha | Group III-V compound crystal article using selective epitaxial growth |
US5166767A (en) | 1987-04-14 | 1992-11-24 | National Semiconductor Corporation | Sidewall contact bipolar transistor with controlled lateral spread of selectively grown epitaxial layer |
US4876210A (en) | 1987-04-30 | 1989-10-24 | The University Of Delaware | Solution growth of lattice mismatched and solubility mismatched heterostructures |
US4826784A (en) | 1987-11-13 | 1989-05-02 | Kopin Corporation | Selective OMCVD growth of compound semiconductor materials on silicon substrates |
JPH01165177A (ja) * | 1987-12-22 | 1989-06-29 | Ricoh Co Ltd | 光電変換素子 |
US5079616A (en) * | 1988-02-11 | 1992-01-07 | Gte Laboratories Incorporated | Semiconductor structure |
US5272105A (en) | 1988-02-11 | 1993-12-21 | Gte Laboratories Incorporated | Method of manufacturing an heteroepitaxial semiconductor structure |
GB2215514A (en) | 1988-03-04 | 1989-09-20 | Plessey Co Plc | Terminating dislocations in semiconductor epitaxial layers |
US5156995A (en) | 1988-04-01 | 1992-10-20 | Cornell Research Foundation, Inc. | Method for reducing or eliminating interface defects in mismatched semiconductor epilayers |
US5032893A (en) | 1988-04-01 | 1991-07-16 | Cornell Research Foundation, Inc. | Method for reducing or eliminating interface defects in mismatched semiconductor eiplayers |
DE3821596A1 (de) | 1988-06-27 | 1990-02-01 | Horst J Ing Grad Feist | Verfahren und vorrichtung zum herstellen von graphitelektroden |
JPH0213988A (ja) * | 1988-07-01 | 1990-01-18 | Inobeeshiyon Center Kk | 多色ディスプレイとその製造方法 |
EP0352472A3 (en) | 1988-07-25 | 1991-02-06 | Texas Instruments Incorporated | Heteroepitaxy of lattice-mismatched semiconductor materials |
US5238869A (en) | 1988-07-25 | 1993-08-24 | Texas Instruments Incorporated | Method of forming an epitaxial layer on a heterointerface |
US5061644A (en) | 1988-12-22 | 1991-10-29 | Honeywell Inc. | Method for fabricating self-aligned semiconductor devices |
EP0380815B1 (en) | 1989-01-31 | 1994-05-25 | Agfa-Gevaert N.V. | Integration of GaAs on Si substrate |
US5034337A (en) | 1989-02-10 | 1991-07-23 | Texas Instruments Incorporated | Method of making an integrated circuit that combines multi-epitaxial power transistors with logic/analog devices |
US4948456A (en) | 1989-06-09 | 1990-08-14 | Delco Electronics Corporation | Confined lateral selective epitaxial growth |
US5256594A (en) | 1989-06-16 | 1993-10-26 | Intel Corporation | Masking technique for depositing gallium arsenide on silicon |
US5098850A (en) * | 1989-06-16 | 1992-03-24 | Canon Kabushiki Kaisha | Process for producing substrate for selective crystal growth, selective crystal growth process and process for producing solar battery by use of them |
US5093699A (en) * | 1990-03-12 | 1992-03-03 | Texas A & M University System | Gate adjusted resonant tunnel diode device and method of manufacture |
US5164359A (en) | 1990-04-20 | 1992-11-17 | Eaton Corporation | Monolithic integrated circuit having compound semiconductor layer epitaxially grown on ceramic substrate |
US5158907A (en) * | 1990-08-02 | 1992-10-27 | At&T Bell Laboratories | Method for making semiconductor devices with low dislocation defects |
US5105247A (en) | 1990-08-03 | 1992-04-14 | Cavanaugh Marion E | Quantum field effect device with source extension region formed under a gate and between the source and drain regions |
JP3202223B2 (ja) | 1990-11-27 | 2001-08-27 | 日本電気株式会社 | トランジスタの製造方法 |
US5403751A (en) | 1990-11-29 | 1995-04-04 | Canon Kabushiki Kaisha | Process for producing a thin silicon solar cell |
US5223043A (en) | 1991-02-11 | 1993-06-29 | The United States Of America As Represented By The United States Department Of Energy | Current-matched high-efficiency, multijunction monolithic solar cells |
US5091767A (en) * | 1991-03-18 | 1992-02-25 | At&T Bell Laboratories | Article comprising a lattice-mismatched semiconductor heterostructure |
JPH04299569A (ja) | 1991-03-27 | 1992-10-22 | Nec Corp | Soisの製造方法及びトランジスタとその製造方法 |
JPH04315419A (ja) * | 1991-04-12 | 1992-11-06 | Nec Corp | 元素半導体基板上の絶縁膜/化合物半導体積層構造 |
US5269852A (en) | 1991-05-27 | 1993-12-14 | Canon Kabushiki Kaisha | Crystalline solar cell and method for producing the same |
JP3058954B2 (ja) | 1991-09-24 | 2000-07-04 | ローム株式会社 | 絶縁層の上に成長層を有する半導体装置の製造方法 |
JP2773487B2 (ja) | 1991-10-15 | 1998-07-09 | 日本電気株式会社 | トンネルトランジスタ |
JPH05121317A (ja) | 1991-10-24 | 1993-05-18 | Rohm Co Ltd | Soi構造形成方法 |
JP3286920B2 (ja) | 1992-07-10 | 2002-05-27 | 富士通株式会社 | 半導体装置の製造方法 |
JP2875124B2 (ja) * | 1992-11-26 | 1999-03-24 | シャープ株式会社 | 半導体発光素子およびその製造方法 |
DE59308841D1 (de) | 1992-12-04 | 1998-09-10 | Siemens Ag | Verfahren zur Herstellung eines seitlich begrenzten, einkristallinen Gebietes mittels selektiver Epitaxie und dessen Anwendung zur Herstellung eines Bipolartransistors sowie eines MOS-transistors |
JP3319472B2 (ja) | 1992-12-07 | 2002-09-03 | 富士通株式会社 | 半導体装置とその製造方法 |
US5295150A (en) * | 1992-12-11 | 1994-03-15 | Eastman Kodak Company | Distributed feedback-channeled substrate planar semiconductor laser |
US5407491A (en) | 1993-04-08 | 1995-04-18 | University Of Houston | Tandem solar cell with improved tunnel junction |
EP0627799B1 (en) * | 1993-06-04 | 1997-10-08 | Sharp Kabushiki Kaisha | Semiconductor light-emitting device with third cladding layer |
JP3748905B2 (ja) | 1993-08-27 | 2006-02-22 | 三洋電機株式会社 | 量子効果デバイス |
US5792679A (en) | 1993-08-30 | 1998-08-11 | Sharp Microelectronics Technology, Inc. | Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant |
US5461243A (en) | 1993-10-29 | 1995-10-24 | International Business Machines Corporation | Substrate for tensilely strained semiconductor |
US5405453A (en) | 1993-11-08 | 1995-04-11 | Applied Solar Energy Corporation | High efficiency multi-junction solar cell |
US5489539A (en) | 1994-01-10 | 1996-02-06 | Hughes Aircraft Company | Method of making quantum well structure with self-aligned gate |
JPH0851109A (ja) | 1994-04-11 | 1996-02-20 | Texas Instr Inc <Ti> | 酸化物でパターン化されたウェーハの窓内にエピタキシャルシリコンを成長させる方法 |
US6011271A (en) * | 1994-04-28 | 2000-01-04 | Fujitsu Limited | Semiconductor device and method of fabricating the same |
US5710436A (en) * | 1994-09-27 | 1998-01-20 | Kabushiki Kaisha Toshiba | Quantum effect device |
US5825240A (en) | 1994-11-30 | 1998-10-20 | Massachusetts Institute Of Technology | Resonant-tunneling transmission line technology |
JP3835225B2 (ja) | 1995-02-23 | 2006-10-18 | 日亜化学工業株式会社 | 窒化物半導体発光素子 |
US5528209A (en) | 1995-04-27 | 1996-06-18 | Hughes Aircraft Company | Monolithic microwave integrated circuit and method |
JPH08306700A (ja) | 1995-04-27 | 1996-11-22 | Nec Corp | 半導体装置及びその製造方法 |
TW304310B (zh) | 1995-05-31 | 1997-05-01 | Siemens Ag | |
US5621227A (en) | 1995-07-18 | 1997-04-15 | Discovery Semiconductors, Inc. | Method and apparatus for monolithic optoelectronic integrated circuit using selective epitaxy |
JPH11500873A (ja) | 1995-12-15 | 1999-01-19 | フィリップス エレクトロニクス ネムローゼ フェンノートシャップ | SiGe層を具えた半導体電界効果デバイス |
TW314621B (zh) | 1995-12-20 | 1997-09-01 | Toshiba Co Ltd | |
DE69736151T2 (de) | 1996-05-17 | 2007-05-10 | Canon K.K. | Photovoltaische Anordnung und Herstellungsverfahren |
JP3719618B2 (ja) | 1996-06-17 | 2005-11-24 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
US6229153B1 (en) * | 1996-06-21 | 2001-05-08 | Wisconsin Alumni Research Corporation | High peak current density resonant tunneling diode |
JP3260660B2 (ja) * | 1996-08-22 | 2002-02-25 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP3449516B2 (ja) | 1996-08-30 | 2003-09-22 | 株式会社リコー | 半導体多層膜反射鏡および半導体多層膜反射防止膜および面発光型半導体レーザおよび受光素子 |
US6191432B1 (en) * | 1996-09-02 | 2001-02-20 | Kabushiki Kaisha Toshiba | Semiconductor device and memory device |
US5825049A (en) | 1996-10-09 | 1998-10-20 | Sandia Corporation | Resonant tunneling device with two-dimensional quantum well emitter and base layers |
JPH10126010A (ja) | 1996-10-23 | 1998-05-15 | Ricoh Co Ltd | 半導体レーザ装置の製造方法 |
SG65697A1 (en) | 1996-11-15 | 1999-06-22 | Canon Kk | Process for producing semiconductor article |
US5853497A (en) | 1996-12-12 | 1998-12-29 | Hughes Electronics Corporation | High efficiency multi-junction solar cells |
US6348096B1 (en) | 1997-03-13 | 2002-02-19 | Nec Corporation | Method for manufacturing group III-V compound semiconductors |
JP3853905B2 (ja) | 1997-03-18 | 2006-12-06 | 株式会社東芝 | 量子効果装置とblトンネル素子を用いた装置 |
EP0874405A3 (en) | 1997-03-25 | 2004-09-15 | Mitsubishi Cable Industries, Ltd. | GaN group crystal base member having low dislocation density, use thereof and manufacturing methods thereof |
JP3184115B2 (ja) | 1997-04-11 | 2001-07-09 | 松下電器産業株式会社 | オーミック電極形成方法 |
CN1131548C (zh) | 1997-04-04 | 2003-12-17 | 松下电器产业株式会社 | 半导体装置 |
JP3047852B2 (ja) | 1997-04-04 | 2000-06-05 | 松下電器産業株式会社 | 半導体装置 |
JP2008034862A (ja) * | 1997-04-11 | 2008-02-14 | Nichia Chem Ind Ltd | 窒化物半導体の成長方法 |
EP2234142A1 (en) | 1997-04-11 | 2010-09-29 | Nichia Corporation | Nitride semiconductor substrate |
US5998781A (en) | 1997-04-30 | 1999-12-07 | Sandia Corporation | Apparatus for millimeter-wave signal generation |
US5903170A (en) | 1997-06-03 | 1999-05-11 | The Regents Of The University Of Michigan | Digital logic design using negative differential resistance diodes and field-effect transistors |
US5883549A (en) * | 1997-06-20 | 1999-03-16 | Hughes Electronics Corporation | Bipolar junction transistor (BJT)--resonant tunneling diode (RTD) oscillator circuit and method |
JP3535527B2 (ja) | 1997-06-24 | 2004-06-07 | マサチューセッツ インスティテュート オブ テクノロジー | 傾斜GeSi層と平坦化を用いたゲルマニウム・オン・シリコンの貫通転位の制御 |
US5869845A (en) * | 1997-06-26 | 1999-02-09 | Texas Instruments Incorporated | Resonant tunneling memory |
US6015979A (en) * | 1997-08-29 | 2000-01-18 | Kabushiki Kaisha Toshiba | Nitride-based semiconductor element and method for manufacturing the same |
JP3930161B2 (ja) | 1997-08-29 | 2007-06-13 | 株式会社東芝 | 窒化物系半導体素子、発光素子及びその製造方法 |
EP1036412A1 (en) | 1997-09-16 | 2000-09-20 | Massachusetts Institute Of Technology | CO-PLANAR Si AND Ge COMPOSITE SUBSTRATE AND METHOD OF PRODUCING SAME |
FR2769924B1 (fr) | 1997-10-20 | 2000-03-10 | Centre Nat Rech Scient | Procede de realisation d'une couche epitaxiale de nitrure de gallium, couche epitaxiale de nitrure de gallium et composant optoelectronique muni d'une telle couche |
WO1999023693A1 (en) | 1997-10-30 | 1999-05-14 | Sumitomo Electric Industries, Ltd. | GaN SINGLE CRYSTALLINE SUBSTRATE AND METHOD OF PRODUCING THE SAME |
JP3180743B2 (ja) | 1997-11-17 | 2001-06-25 | 日本電気株式会社 | 窒化化合物半導体発光素子およびその製法 |
JP3468082B2 (ja) | 1998-02-26 | 2003-11-17 | 日亜化学工業株式会社 | 窒化物半導体素子 |
US6150242A (en) | 1998-03-25 | 2000-11-21 | Texas Instruments Incorporated | Method of growing crystalline silicon overlayers on thin amorphous silicon oxide layers and forming by method a resonant tunneling diode |
JPH11274467A (ja) | 1998-03-26 | 1999-10-08 | Murata Mfg Co Ltd | 光電子集積回路素子 |
US6500257B1 (en) | 1998-04-17 | 2002-12-31 | Agilent Technologies, Inc. | Epitaxial material grown laterally within a trench and method for producing same |
JP3338778B2 (ja) | 1998-04-24 | 2002-10-28 | 日本電気株式会社 | 窒化物系化合物半導体レーザ素子 |
US6265289B1 (en) * | 1998-06-10 | 2001-07-24 | North Carolina State University | Methods of fabricating gallium nitride semiconductor layers by lateral growth from sidewalls into trenches, and gallium nitride semiconductor structures fabricated thereby |
JP4005701B2 (ja) | 1998-06-24 | 2007-11-14 | シャープ株式会社 | 窒素化合物半導体膜の形成方法および窒素化合物半導体素子 |
KR100580307B1 (ko) | 1998-07-14 | 2006-05-16 | 후지쯔 가부시끼가이샤 | 반도체 레이저 및 반도체 장치 |
EP1115163A4 (en) | 1998-09-10 | 2001-12-05 | Rohm Co Ltd | SEMICONDUCTOR LEDS AND MANUFACTURING METHOD THEREOF |
US6252261B1 (en) | 1998-09-30 | 2001-06-26 | Nec Corporation | GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor |
JP3868136B2 (ja) | 1999-01-20 | 2007-01-17 | 日亜化学工業株式会社 | 窒化ガリウム系化合物半導体発光素子 |
JP3372226B2 (ja) | 1999-02-10 | 2003-01-27 | 日亜化学工業株式会社 | 窒化物半導体レーザ素子 |
US7145167B1 (en) | 2000-03-11 | 2006-12-05 | International Business Machines Corporation | High speed Ge channel heterostructures for field effect devices |
JP3760663B2 (ja) | 1999-03-31 | 2006-03-29 | 豊田合成株式会社 | Iii族窒化物系化合物半導体素子の製造方法 |
JP3702700B2 (ja) * | 1999-03-31 | 2005-10-05 | 豊田合成株式会社 | Iii族窒化物系化合物半導体素子及びその製造方法 |
DE10017137A1 (de) | 1999-04-14 | 2000-10-26 | Siemens Ag | Silizium-Aufbau und Verfahren zu dessen Herstellung |
US6803598B1 (en) | 1999-05-07 | 2004-10-12 | University Of Delaware | Si-based resonant interband tunneling diodes and method of making interband tunneling diodes |
JP3587081B2 (ja) | 1999-05-10 | 2004-11-10 | 豊田合成株式会社 | Iii族窒化物半導体の製造方法及びiii族窒化物半導体発光素子 |
WO2000070683A1 (fr) * | 1999-05-13 | 2000-11-23 | Hitachi, Ltd. | Mémoire à semi-conducteurs |
US6252287B1 (en) | 1999-05-19 | 2001-06-26 | Sandia Corporation | InGaAsN/GaAs heterojunction for multi-junction solar cells |
JP3555500B2 (ja) | 1999-05-21 | 2004-08-18 | 豊田合成株式会社 | Iii族窒化物半導体及びその製造方法 |
US6214653B1 (en) | 1999-06-04 | 2001-04-10 | International Business Machines Corporation | Method for fabricating complementary metal oxide semiconductor (CMOS) devices on a mixed bulk and silicon-on-insulator (SOI) substrate |
JP2001007447A (ja) | 1999-06-18 | 2001-01-12 | Nichia Chem Ind Ltd | 窒化物半導体レーザ素子 |
US6635110B1 (en) | 1999-06-25 | 2003-10-21 | Massachusetts Institute Of Technology | Cyclic thermal anneal for dislocation reduction |
US6228691B1 (en) | 1999-06-30 | 2001-05-08 | Intel Corp. | Silicon-on-insulator devices and method for producing the same |
GB9919479D0 (en) | 1999-08-17 | 1999-10-20 | Imperial College | Island arrays |
US6339232B1 (en) * | 1999-09-20 | 2002-01-15 | Kabushika Kaisha Toshiba | Semiconductor device |
JP2001102678A (ja) | 1999-09-29 | 2001-04-13 | Toshiba Corp | 窒化ガリウム系化合物半導体素子 |
US6984571B1 (en) * | 1999-10-01 | 2006-01-10 | Ziptronix, Inc. | Three dimensional device integration method and integrated device |
US6812053B1 (en) | 1999-10-14 | 2004-11-02 | Cree, Inc. | Single step pendeo- and lateral epitaxial overgrowth of Group III-nitride epitaxial layers with Group III-nitride buffer layer and resulting structures |
JP2001189483A (ja) | 1999-10-18 | 2001-07-10 | Sharp Corp | バイパス機能付太陽電池セルおよびバイパス機能付き多接合積層型太陽電池セルおよびそれらの製造方法 |
EP1672700A2 (en) * | 1999-11-15 | 2006-06-21 | Matsushita Electric Industrial Co., Ltd. | Field effect semiconductor device |
US6521514B1 (en) * | 1999-11-17 | 2003-02-18 | North Carolina State University | Pendeoepitaxial methods of fabricating gallium nitride semiconductor layers on sapphire substrates |
JP2001176805A (ja) | 1999-12-16 | 2001-06-29 | Sony Corp | 窒化物系iii−v族化合物の結晶製造方法、窒化物系iii−v族化合物結晶基板、窒化物系iii−v族化合物結晶膜およびデバイスの製造方法 |
US6403451B1 (en) | 2000-02-09 | 2002-06-11 | Noerh Carolina State University | Methods of fabricating gallium nitride semiconductor layers on substrates including non-gallium nitride posts |
CA2398801C (en) * | 2000-02-11 | 2007-12-04 | Novo Rps Ulc | Stent delivery system and method of use |
US6902987B1 (en) | 2000-02-16 | 2005-06-07 | Ziptronix, Inc. | Method for low temperature bonding and bonded structure |
JP3512701B2 (ja) | 2000-03-10 | 2004-03-31 | 株式会社東芝 | 半導体装置及びその製造方法 |
TW504754B (en) * | 2000-03-24 | 2002-10-01 | Sumitomo Chemical Co | Group III-V compound semiconductor and method of producing the same |
US20050184302A1 (en) | 2000-04-04 | 2005-08-25 | Toshimasa Kobayashi | Nitride semiconductor device and method of manufacturing the same |
US6362071B1 (en) * | 2000-04-05 | 2002-03-26 | Motorola, Inc. | Method for forming a semiconductor device with an opening in a dielectric layer |
JP2001338988A (ja) | 2000-05-25 | 2001-12-07 | Hitachi Ltd | 半導体装置及びその製造方法 |
US6841808B2 (en) * | 2000-06-23 | 2005-01-11 | Toyoda Gosei Co., Ltd. | Group III nitride compound semiconductor device and method for producing the same |
US20020008234A1 (en) | 2000-06-28 | 2002-01-24 | Motorola, Inc. | Mixed-signal semiconductor structure, device including the structure, and methods of forming the device and the structure |
US20020030246A1 (en) * | 2000-06-28 | 2002-03-14 | Motorola, Inc. | Structure and method for fabricating semiconductor structures and devices not lattice matched to the substrate |
US20020011612A1 (en) * | 2000-07-31 | 2002-01-31 | Kabushiki Kaisha Toshiba | Semiconductor device and method for manufacturing the same |
JP2002118255A (ja) | 2000-07-31 | 2002-04-19 | Toshiba Corp | 半導体装置およびその製造方法 |
JP4269541B2 (ja) * | 2000-08-01 | 2009-05-27 | 株式会社Sumco | 半導体基板と電界効果型トランジスタ並びにSiGe層の形成方法及びこれを用いた歪みSi層の形成方法と電界効果型トランジスタの製造方法 |
JP2002062090A (ja) | 2000-08-17 | 2002-02-28 | Mekku Corporation:Kk | プレート型直交熱交換器のダスト除去装置 |
US6579463B1 (en) | 2000-08-18 | 2003-06-17 | The Regents Of The University Of Colorado | Tunable nanomasks for pattern transfer and nanocluster array formation |
US6815993B1 (en) | 2000-08-21 | 2004-11-09 | Mitsubishi Denki Kabushiki Kaisha | π/2 phase shifter |
US7301199B2 (en) | 2000-08-22 | 2007-11-27 | President And Fellows Of Harvard College | Nanoscale wires and related devices |
US20060175601A1 (en) | 2000-08-22 | 2006-08-10 | President And Fellows Of Harvard College | Nanoscale wires and related devices |
US6407425B1 (en) | 2000-09-21 | 2002-06-18 | Texas Instruments Incorporated | Programmable neuron MOSFET on SOI |
US6456214B1 (en) | 2000-09-27 | 2002-09-24 | Raytheon Company | High-speed comparator utilizing resonant tunneling diodes and associated method |
JP4044276B2 (ja) * | 2000-09-28 | 2008-02-06 | 株式会社東芝 | 半導体装置及びその製造方法 |
US7163864B1 (en) * | 2000-10-18 | 2007-01-16 | International Business Machines Corporation | Method of fabricating semiconductor side wall fin |
US6720090B2 (en) | 2001-01-02 | 2004-04-13 | Eastman Kodak Company | Organic light emitting diode devices with improved luminance efficiency |
US7052979B2 (en) | 2001-02-14 | 2006-05-30 | Toyoda Gosei Co., Ltd. | Production method for semiconductor crystal and semiconductor luminous element |
JP4084544B2 (ja) | 2001-03-30 | 2008-04-30 | 豊田合成株式会社 | 半導体基板及び半導体素子の製造方法 |
JP4084541B2 (ja) | 2001-02-14 | 2008-04-30 | 豊田合成株式会社 | 半導体結晶及び半導体発光素子の製造方法 |
US6380590B1 (en) | 2001-02-22 | 2002-04-30 | Advanced Micro Devices, Inc. | SOI chip having multiple threshold voltage MOSFETs by using multiple channel materials and method of fabricating same |
US6475869B1 (en) | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
JP3679720B2 (ja) * | 2001-02-27 | 2005-08-03 | 三洋電機株式会社 | 窒化物系半導体素子および窒化物系半導体の形成方法 |
JP2002270516A (ja) * | 2001-03-07 | 2002-09-20 | Nec Corp | Iii族窒化物半導体の成長方法、iii族窒化物半導体膜およびそれを用いた半導体素子 |
US7205604B2 (en) | 2001-03-13 | 2007-04-17 | International Business Machines Corporation | Ultra scalable high speed heterojunction vertical n-channel MISFETs and methods thereof |
JP3705142B2 (ja) | 2001-03-27 | 2005-10-12 | ソニー株式会社 | 窒化物半導体素子及びその作製方法 |
CA2442985C (en) * | 2001-03-30 | 2016-05-31 | The Regents Of The University Of California | Methods of fabricating nanostructures and nanowires and devices fabricated therefrom |
JP3956637B2 (ja) | 2001-04-12 | 2007-08-08 | ソニー株式会社 | 窒化物半導体の結晶成長方法及び半導体素子の形成方法 |
GB0110112D0 (en) | 2001-04-25 | 2001-06-20 | Univ Glasgow | Improved optoelectronic device |
GB0111207D0 (en) | 2001-05-08 | 2001-06-27 | Btg Int Ltd | A method to produce germanium layers |
US6784074B2 (en) | 2001-05-09 | 2004-08-31 | Nsc-Nanosemiconductor Gmbh | Defect-free semiconductor templates for epitaxial growth and method of making same |
JP3819730B2 (ja) | 2001-05-11 | 2006-09-13 | 三洋電機株式会社 | 窒化物系半導体素子および窒化物半導体の形成方法 |
US20020168802A1 (en) | 2001-05-14 | 2002-11-14 | Hsu Sheng Teng | SiGe/SOI CMOS and method of making the same |
US7358578B2 (en) * | 2001-05-22 | 2008-04-15 | Renesas Technology Corporation | Field effect transistor on a substrate with (111) orientation having zirconium oxide gate insulation and cobalt or nickel silicide wiring |
WO2002103812A1 (en) | 2001-06-13 | 2002-12-27 | Matsushita Electric Industrial Co., Ltd. | Nitride semiconductor, production method therefor and nitride semiconductor element |
JP3515974B2 (ja) | 2001-06-13 | 2004-04-05 | 松下電器産業株式会社 | 窒化物半導体、その製造方法及び窒化物半導体素子 |
US6566284B2 (en) | 2001-08-07 | 2003-05-20 | Hrl Laboratories, Llc | Method of manufacture for 80 nanometer diameter resonant tunneling diode with improved peak-to-valley ratio and resonant tunneling diode therefrom |
JP3785970B2 (ja) * | 2001-09-03 | 2006-06-14 | 日本電気株式会社 | Iii族窒化物半導体素子の製造方法 |
JP2003077847A (ja) * | 2001-09-06 | 2003-03-14 | Sumitomo Chem Co Ltd | 3−5族化合物半導体の製造方法 |
JP2003163370A (ja) | 2001-09-11 | 2003-06-06 | Toyoda Gosei Co Ltd | 半導体結晶の製造方法 |
TW544930B (en) | 2001-09-11 | 2003-08-01 | Toyoda Gosei Kk | Method for producing semiconductor crystal |
US7105865B2 (en) * | 2001-09-19 | 2006-09-12 | Sumitomo Electric Industries, Ltd. | AlxInyGa1−x−yN mixture crystal substrate |
JP3697406B2 (ja) * | 2001-09-26 | 2005-09-21 | 株式会社東芝 | 半導体発光装置及びその製造方法 |
US6689650B2 (en) * | 2001-09-27 | 2004-02-10 | International Business Machines Corporation | Fin field effect transistor with self-aligned gate |
US20030064535A1 (en) | 2001-09-28 | 2003-04-03 | Kub Francis J. | Method of manufacturing a semiconductor device having a thin GaN material directly bonded to an optimized substrate |
US6710368B2 (en) | 2001-10-01 | 2004-03-23 | Ken Scott Fisher | Quantum tunneling transistor |
US20030070707A1 (en) | 2001-10-12 | 2003-04-17 | King Richard Roland | Wide-bandgap, lattice-mismatched window layer for a solar energy conversion device |
JP2003142728A (ja) | 2001-11-02 | 2003-05-16 | Sharp Corp | 半導体発光素子の製造方法 |
JP2003152220A (ja) * | 2001-11-15 | 2003-05-23 | Sharp Corp | 半導体発光素子の製造方法および半導体発光素子 |
US6835246B2 (en) | 2001-11-16 | 2004-12-28 | Saleem H. Zaidi | Nanostructures for hetero-expitaxial growth on silicon substrates |
JP3758562B2 (ja) * | 2001-11-27 | 2006-03-22 | 日亜化学工業株式会社 | 窒化物半導体多色発光素子 |
US6576532B1 (en) | 2001-11-30 | 2003-06-10 | Motorola Inc. | Semiconductor device and method therefor |
JP4284188B2 (ja) | 2001-12-20 | 2009-06-24 | パナソニック株式会社 | 窒化物系半導体基板の製造方法および窒化物系半導体装置の製造方法 |
EP2105977B1 (en) | 2002-01-28 | 2014-06-25 | Nichia Corporation | Nitride semiconductor element with supporting substrate and method for producing nitride semiconductor element |
KR100458288B1 (ko) | 2002-01-30 | 2004-11-26 | 한국과학기술원 | 이중-게이트 FinFET 소자 및 그 제조방법 |
US7411233B2 (en) * | 2002-08-27 | 2008-08-12 | E-Phocus, Inc | Photoconductor-on-active-pixel (POAP) sensor utilizing a multi-layered radiation absorbing structure |
US6492216B1 (en) | 2002-02-07 | 2002-12-10 | Taiwan Semiconductor Manufacturing Company | Method of forming a transistor with a strained channel |
JP3782021B2 (ja) | 2002-02-22 | 2006-06-07 | 株式会社東芝 | 半導体装置、半導体装置の製造方法、半導体基板の製造方法 |
JP4092927B2 (ja) | 2002-02-28 | 2008-05-28 | 豊田合成株式会社 | Iii族窒化物系化合物半導体、iii族窒化物系化合物半導体素子及びiii族窒化物系化合物半導体基板の製造方法 |
US6635909B2 (en) | 2002-03-19 | 2003-10-21 | International Business Machines Corporation | Strained fin FETs structure and method |
WO2004061909A1 (en) | 2002-12-16 | 2004-07-22 | The Regents Of The University Of California | Growth of reduced dislocation density non-polar gallium nitride by hydride vapor phase epitaxy |
US7208393B2 (en) | 2002-04-15 | 2007-04-24 | The Regents Of The University Of California | Growth of planar reduced dislocation density m-plane gallium nitride by hydride vapor phase epitaxy |
WO2003089696A1 (en) | 2002-04-15 | 2003-10-30 | The Regents Of The University Of California | Dislocation reduction in non-polar gallium nitride thin films |
US20060162768A1 (en) | 2002-05-21 | 2006-07-27 | Wanlass Mark W | Low bandgap, monolithic, multi-bandgap, optoelectronic devices |
US8067687B2 (en) | 2002-05-21 | 2011-11-29 | Alliance For Sustainable Energy, Llc | High-efficiency, monolithic, multi-bandgap, tandem photovoltaic energy converters |
US7217882B2 (en) | 2002-05-24 | 2007-05-15 | Cornell Research Foundation, Inc. | Broad spectrum solar cell |
CN2550906Y (zh) | 2002-05-27 | 2003-05-14 | 李映华 | 立体光双面结光电池 |
FR2840452B1 (fr) * | 2002-05-28 | 2005-10-14 | Lumilog | Procede de realisation par epitaxie d'un film de nitrure de gallium separe de son substrat |
TWI271877B (en) | 2002-06-04 | 2007-01-21 | Nitride Semiconductors Co Ltd | Gallium nitride compound semiconductor device and manufacturing method |
US6995430B2 (en) | 2002-06-07 | 2006-02-07 | Amberwave Systems Corporation | Strained-semiconductor-on-insulator device structures |
US7074623B2 (en) | 2002-06-07 | 2006-07-11 | Amberwave Systems Corporation | Methods of forming strained-semiconductor-on-insulator finFET device structures |
JP2004014856A (ja) | 2002-06-07 | 2004-01-15 | Sharp Corp | 半導体基板の製造方法及び半導体装置の製造方法 |
CN100399586C (zh) | 2002-06-19 | 2008-07-02 | 麻省理工学院 | Ge光电探测器 |
US6887773B2 (en) | 2002-06-19 | 2005-05-03 | Luxtera, Inc. | Methods of incorporating germanium within CMOS process |
US7012298B1 (en) * | 2002-06-21 | 2006-03-14 | Advanced Micro Devices, Inc. | Non-volatile memory device |
US6617643B1 (en) | 2002-06-28 | 2003-09-09 | Mcnc | Low power tunneling metal-oxide-semiconductor (MOS) device |
US7335908B2 (en) | 2002-07-08 | 2008-02-26 | Qunano Ab | Nanostructures and methods for manufacturing the same |
US6982204B2 (en) * | 2002-07-16 | 2006-01-03 | Cree, Inc. | Nitride-based transistors and methods of fabrication thereof using non-etched contact recesses |
US20040012037A1 (en) * | 2002-07-18 | 2004-01-22 | Motorola, Inc. | Hetero-integration of semiconductor materials on silicon |
EP2267762A3 (en) | 2002-08-23 | 2012-08-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor heterostructures having reduced dislocation pile-ups and related methods |
US20040043584A1 (en) * | 2002-08-27 | 2004-03-04 | Thomas Shawn G. | Semiconductor device and method of making same |
US7015497B1 (en) | 2002-08-27 | 2006-03-21 | The Ohio State University | Self-aligned and self-limited quantum dot nanoswitches and methods for making same |
GB0220438D0 (en) * | 2002-09-03 | 2002-10-09 | Univ Warwick | Formation of lattice-turning semiconductor substrates |
US7122733B2 (en) | 2002-09-06 | 2006-10-17 | The Boeing Company | Multi-junction photovoltaic cell having buffer layers for the growth of single crystal boron compounds |
US6830953B1 (en) | 2002-09-17 | 2004-12-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Suppression of MOSFET gate leakage current |
US6815241B2 (en) | 2002-09-25 | 2004-11-09 | Cao Group, Inc. | GaN structures having low dislocation density and methods of manufacture |
US6787864B2 (en) | 2002-09-30 | 2004-09-07 | Advanced Micro Devices, Inc. | Mosfets incorporating nickel germanosilicided gate and methods for their formation |
US6800910B2 (en) | 2002-09-30 | 2004-10-05 | Advanced Micro Devices, Inc. | FinFET device incorporating strained silicon in the channel region |
JP4546021B2 (ja) | 2002-10-02 | 2010-09-15 | ルネサスエレクトロニクス株式会社 | 絶縁ゲート型電界効果型トランジスタ及び半導体装置 |
US6902991B2 (en) | 2002-10-24 | 2005-06-07 | Advanced Micro Devices, Inc. | Semiconductor device having a thick strained silicon layer and method of its formation |
US6709982B1 (en) * | 2002-11-26 | 2004-03-23 | Advanced Micro Devices, Inc. | Double spacer FinFET formation |
US6855990B2 (en) * | 2002-11-26 | 2005-02-15 | Taiwan Semiconductor Manufacturing Co., Ltd | Strained-channel multiple-gate transistor |
US6920159B2 (en) | 2002-11-29 | 2005-07-19 | Optitune Plc | Tunable optical source |
US7003436B1 (en) * | 2002-12-04 | 2006-02-21 | Southwest Sciences Incorporated | Determination of fit basis functions |
WO2004054003A1 (en) | 2002-12-05 | 2004-06-24 | Blue Photonics, Inc. | High efficiency, monolithic multijunction solar cells containing lattice-mismatched materials and methods of forming same |
US6645797B1 (en) | 2002-12-06 | 2003-11-11 | Advanced Micro Devices, Inc. | Method for forming fins in a FinFET device using sacrificial carbon layer |
US7071494B2 (en) * | 2002-12-11 | 2006-07-04 | Lumileds Lighting U.S. Llc | Light emitting device with enhanced optical scattering |
US7012314B2 (en) * | 2002-12-18 | 2006-03-14 | Agere Systems Inc. | Semiconductor devices with reduced active region defects and unique contacting schemes |
US7453129B2 (en) | 2002-12-18 | 2008-11-18 | Noble Peak Vision Corp. | Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry |
US7589380B2 (en) * | 2002-12-18 | 2009-09-15 | Noble Peak Vision Corp. | Method for forming integrated circuit utilizing dual semiconductors |
JP2004200375A (ja) | 2002-12-18 | 2004-07-15 | Matsushita Electric Ind Co Ltd | 半導体レーザ装置およびその製造方法 |
US6794718B2 (en) | 2002-12-19 | 2004-09-21 | International Business Machines Corporation | High mobility crystalline planes in double-gate CMOS technology |
US6686245B1 (en) * | 2002-12-20 | 2004-02-03 | Motorola, Inc. | Vertical MOSFET with asymmetric gate structure |
US7098487B2 (en) | 2002-12-27 | 2006-08-29 | General Electric Company | Gallium nitride crystal and method of making same |
KR100513316B1 (ko) * | 2003-01-21 | 2005-09-09 | 삼성전기주식회사 | 고효율 반도체 소자 제조방법 |
US6762483B1 (en) | 2003-01-23 | 2004-07-13 | Advanced Micro Devices, Inc. | Narrow fin FinFET |
JP2004235190A (ja) | 2003-01-28 | 2004-08-19 | Sony Corp | 光半導体装置 |
WO2004073044A2 (en) | 2003-02-13 | 2004-08-26 | Massachusetts Institute Of Technology | Finfet device and method to make same |
DE10320160A1 (de) | 2003-02-14 | 2004-08-26 | Osram Opto Semiconductors Gmbh | Verfahren zum Herstellen einer Mehrzahl von Halbleiterkörper und elektronischer Halbleiterkörper |
US6815738B2 (en) | 2003-02-28 | 2004-11-09 | International Business Machines Corporation | Multiple gate MOSFET structure with strained Si Fin body |
JP4695824B2 (ja) | 2003-03-07 | 2011-06-08 | 富士電機ホールディングス株式会社 | 半導体ウエハの製造方法 |
WO2004081982A2 (en) | 2003-03-07 | 2004-09-23 | Amberwave Systems Corporation | Shallow trench isolation process |
US20070029643A1 (en) * | 2003-03-21 | 2007-02-08 | Johnson Mark A L | Methods for nanoscale structures from optical lithography and subsequent lateral growth |
US6936851B2 (en) | 2003-03-21 | 2005-08-30 | Tien Yang Wang | Semiconductor light-emitting device and method for manufacturing the same |
US7061065B2 (en) | 2003-03-31 | 2006-06-13 | National Chung-Hsing University | Light emitting diode and method for producing the same |
JP4628651B2 (ja) * | 2003-04-02 | 2011-02-09 | 日亜化学工業株式会社 | 窒化物半導体発光素子の製造方法 |
US6900502B2 (en) | 2003-04-03 | 2005-05-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel on insulator device |
TWI231994B (en) | 2003-04-04 | 2005-05-01 | Univ Nat Taiwan | Strained Si FinFET |
US20050212051A1 (en) | 2003-04-16 | 2005-09-29 | Sarnoff Corporation | Low voltage silicon controlled rectifier (SCR) for electrostatic discharge (ESD) protection of silicon-on-insulator technologies |
JP2004336040A (ja) * | 2003-04-30 | 2004-11-25 | Osram Opto Semiconductors Gmbh | 複数の半導体チップの製造方法および電子半導体基体 |
US6867433B2 (en) * | 2003-04-30 | 2005-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors |
US6909186B2 (en) | 2003-05-01 | 2005-06-21 | International Business Machines Corporation | High performance FET devices and methods therefor |
US6838322B2 (en) * | 2003-05-01 | 2005-01-04 | Freescale Semiconductor, Inc. | Method for forming a double-gated semiconductor device |
US7088143B2 (en) | 2003-05-22 | 2006-08-08 | The Regents Of The University Of Michigan | Dynamic circuits having improved noise tolerance and method for designing same |
US6849487B2 (en) * | 2003-05-27 | 2005-02-01 | Motorola, Inc. | Method for forming an electronic structure using etch |
TWI242232B (en) * | 2003-06-09 | 2005-10-21 | Canon Kk | Semiconductor substrate, semiconductor device, and method of manufacturing the same |
US7262117B1 (en) | 2003-06-10 | 2007-08-28 | Luxtera, Inc. | Germanium integrated CMOS wafer and method for manufacturing the same |
JP4105044B2 (ja) | 2003-06-13 | 2008-06-18 | 株式会社東芝 | 電界効果トランジスタ |
US6974733B2 (en) | 2003-06-16 | 2005-12-13 | Intel Corporation | Double-gate transistor with enhanced carrier mobility |
US6943407B2 (en) | 2003-06-17 | 2005-09-13 | International Business Machines Corporation | Low leakage heterojunction vertical transistors and high performance devices thereof |
JP2005011915A (ja) | 2003-06-18 | 2005-01-13 | Hitachi Ltd | 半導体装置、半導体回路モジュールおよびその製造方法 |
US7045401B2 (en) | 2003-06-23 | 2006-05-16 | Sharp Laboratories Of America, Inc. | Strained silicon finFET device |
KR100631832B1 (ko) | 2003-06-24 | 2006-10-09 | 삼성전기주식회사 | 백색 발광소자 및 그 제조방법 |
US7122392B2 (en) | 2003-06-30 | 2006-10-17 | Intel Corporation | Methods of forming a high germanium concentration silicon germanium alloy by epitaxial lateral overgrowth and structures formed thereby |
US20050017351A1 (en) * | 2003-06-30 | 2005-01-27 | Ravi Kramadhati V. | Silicon on diamond wafers and devices |
US6921982B2 (en) | 2003-07-21 | 2005-07-26 | International Business Machines Corporation | FET channel having a strained lattice structure along multiple surfaces |
EP1519420A2 (en) | 2003-09-25 | 2005-03-30 | Interuniversitaire Microelectronica Centrum vzw ( IMEC) | Multiple gate semiconductor device and method for forming same |
JP2005051022A (ja) * | 2003-07-28 | 2005-02-24 | Seiko Epson Corp | 半導体装置およびその製造方法 |
CN100536167C (zh) | 2003-08-05 | 2009-09-02 | 富士通微电子株式会社 | 半导体装置及其制造方法 |
US6855583B1 (en) * | 2003-08-05 | 2005-02-15 | Advanced Micro Devices, Inc. | Method for forming tri-gate FinFET with mesa isolation |
US6835618B1 (en) | 2003-08-05 | 2004-12-28 | Advanced Micro Devices, Inc. | Epitaxially grown fin for FinFET |
US7101742B2 (en) | 2003-08-12 | 2006-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained channel complementary field-effect transistors and methods of manufacture |
US20050035410A1 (en) * | 2003-08-15 | 2005-02-17 | Yee-Chia Yeo | Semiconductor diode with reduced leakage |
US7355253B2 (en) * | 2003-08-22 | 2008-04-08 | International Business Machines Corporation | Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates |
US6815278B1 (en) | 2003-08-25 | 2004-11-09 | International Business Machines Corporation | Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations |
JP4160881B2 (ja) * | 2003-08-28 | 2008-10-08 | 松下電器産業株式会社 | 半導体発光装置、発光モジュール、照明装置、および半導体発光装置の製造方法 |
US6955969B2 (en) | 2003-09-03 | 2005-10-18 | Advanced Micro Devices, Inc. | Method of growing as a channel region to reduce source/drain junction capacitance |
US7078299B2 (en) | 2003-09-03 | 2006-07-18 | Advanced Micro Devices, Inc. | Formation of finFET using a sidewall epitaxial layer |
JP4439358B2 (ja) | 2003-09-05 | 2010-03-24 | 株式会社東芝 | 電界効果トランジスタ及びその製造方法 |
US7579263B2 (en) * | 2003-09-09 | 2009-08-25 | Stc.Unm | Threading-dislocation-free nanoheteroepitaxy of Ge on Si using self-directed touch-down of Ge through a thin SiO2 layer |
US20050054164A1 (en) * | 2003-09-09 | 2005-03-10 | Advanced Micro Devices, Inc. | Strained silicon MOSFETs having reduced diffusion of n-type dopants |
US7138292B2 (en) | 2003-09-10 | 2006-11-21 | Lsi Logic Corporation | Apparatus and method of manufacture for integrated circuit and CMOS device including epitaxially grown dielectric on silicon carbide |
US20050056827A1 (en) * | 2003-09-15 | 2005-03-17 | Agency For Science, Technology And Research | CMOS compatible low band offset double barrier resonant tunneling diode |
US7211864B2 (en) * | 2003-09-15 | 2007-05-01 | Seliskar John J | Fully-depleted castellated gate MOSFET device and method of manufacture thereof |
US20050104152A1 (en) | 2003-09-19 | 2005-05-19 | Snyder John P. | Schottky barrier integrated circuit |
US6919258B2 (en) | 2003-10-02 | 2005-07-19 | Freescale Semiconductor, Inc. | Semiconductor device incorporating a defect controlled strained channel structure and method of making the same |
US6831350B1 (en) | 2003-10-02 | 2004-12-14 | Freescale Semiconductor, Inc. | Semiconductor structure with different lattice constant materials and method for forming the same |
CN1868045A (zh) | 2003-10-03 | 2006-11-22 | 斯平内克半导体股份有限公司 | 使用各向同性蚀刻工艺的肖特基势垒mosfet制造方法 |
US6900491B2 (en) | 2003-10-06 | 2005-05-31 | Hewlett-Packard Development Company, L.P. | Magnetic memory |
WO2005038901A1 (en) | 2003-10-22 | 2005-04-28 | Spinnaker Semiconductor, Inc. | Dynamic schottky barrier mosfet device and method of manufacture |
US7009215B2 (en) | 2003-10-24 | 2006-03-07 | General Electric Company | Group III-nitride based resonant cavity light emitting devices fabricated on single crystal gallium nitride substrates |
US6977194B2 (en) | 2003-10-30 | 2005-12-20 | International Business Machines Corporation | Structure and method to improve channel mobility by gate electrode stress modification |
US7057216B2 (en) | 2003-10-31 | 2006-06-06 | International Business Machines Corporation | High mobility heterojunction complementary field effect transistors and methods thereof |
US6902965B2 (en) | 2003-10-31 | 2005-06-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strained silicon structure |
GB0326321D0 (en) | 2003-11-12 | 2003-12-17 | Univ Warwick | Formation of lattice-tuning semiconductor substrates |
US20050104156A1 (en) | 2003-11-13 | 2005-05-19 | Texas Instruments Incorporated | Forming a semiconductor structure in manufacturing a semiconductor device using one or more epitaxial growth processes |
US7247534B2 (en) | 2003-11-19 | 2007-07-24 | International Business Machines Corporation | Silicon device on Si:C-OI and SGOI and method of manufacture |
US7176522B2 (en) * | 2003-11-25 | 2007-02-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having high drive current and method of manufacturing thereof |
JP2005191530A (ja) | 2003-12-03 | 2005-07-14 | Sumitomo Electric Ind Ltd | 発光装置 |
JP4473710B2 (ja) | 2003-12-05 | 2010-06-02 | 株式会社東芝 | 半導体装置 |
US7198995B2 (en) | 2003-12-12 | 2007-04-03 | International Business Machines Corporation | Strained finFETs and method of manufacture |
US6958286B2 (en) | 2004-01-02 | 2005-10-25 | International Business Machines Corporation | Method of preventing surface roughening during hydrogen prebake of SiGe substrates |
US7247912B2 (en) | 2004-01-05 | 2007-07-24 | International Business Machines Corporation | Structures and methods for making strained MOSFETs |
US7705345B2 (en) | 2004-01-07 | 2010-04-27 | International Business Machines Corporation | High performance strained silicon FinFETs device and method for forming same |
US7138302B2 (en) | 2004-01-12 | 2006-11-21 | Advanced Micro Devices, Inc. | Method of fabricating an integrated circuit channel region |
US7268058B2 (en) | 2004-01-16 | 2007-09-11 | Intel Corporation | Tri-gate transistors and methods to fabricate same |
US7385247B2 (en) | 2004-01-17 | 2008-06-10 | Samsung Electronics Co., Ltd. | At least penta-sided-channel type of FinFET transistor |
US7198970B2 (en) | 2004-01-23 | 2007-04-03 | The United States Of America As Represented By The Secretary Of The Navy | Technique for perfecting the active regions of wide bandgap semiconductor nitride devices |
US7118987B2 (en) | 2004-01-29 | 2006-10-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of achieving improved STI gap fill with reduced stress |
US7180134B2 (en) * | 2004-01-30 | 2007-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and structures for planar and multiple-gate transistors formed on SOI |
DE102004005506B4 (de) * | 2004-01-30 | 2009-11-19 | Atmel Automotive Gmbh | Verfahren zur Erzeugung von aktiven Halbleiterschichten verschiedener Dicke in einem SOI-Wafer |
US6855982B1 (en) * | 2004-02-02 | 2005-02-15 | Advanced Micro Devices, Inc. | Self aligned double gate transistor having a strained channel region and process therefor |
US7205210B2 (en) | 2004-02-17 | 2007-04-17 | Freescale Semiconductor, Inc. | Semiconductor structure having strained semiconductor and method therefor |
JP2005277374A (ja) * | 2004-02-26 | 2005-10-06 | Toyoda Gosei Co Ltd | Iii族窒化物系化合物半導体発光素子及びその製造方法 |
US7492022B2 (en) | 2004-02-27 | 2009-02-17 | University Of Iowa Research Foundation | Non-magnetic semiconductor spin transistor |
US6995456B2 (en) * | 2004-03-12 | 2006-02-07 | International Business Machines Corporation | High-performance CMOS SOI devices on hybrid crystal-oriented substrates |
US7160753B2 (en) * | 2004-03-16 | 2007-01-09 | Voxtel, Inc. | Silicon-on-insulator active pixel sensors |
US6888181B1 (en) | 2004-03-18 | 2005-05-03 | United Microelectronics Corp. | Triple gate device having strained-silicon channel |
US20050211291A1 (en) | 2004-03-23 | 2005-09-29 | The Boeing Company | Solar cell assembly |
US7154118B2 (en) | 2004-03-31 | 2006-12-26 | Intel Corporation | Bulk non-planar transistor having strained enhanced mobility and methods of fabrication |
US6998684B2 (en) * | 2004-03-31 | 2006-02-14 | International Business Machines Corporation | High mobility plane CMOS SOI |
US7087965B2 (en) | 2004-04-22 | 2006-08-08 | International Business Machines Corporation | Strained silicon CMOS on hybrid crystal orientations |
US7445673B2 (en) | 2004-05-18 | 2008-11-04 | Lumilog | Manufacturing gallium nitride substrates by lateral overgrowth through masks and devices fabricated thereof |
US7084441B2 (en) | 2004-05-20 | 2006-08-01 | Cree, Inc. | Semiconductor devices having a hybrid channel layer, current aperture transistors and methods of fabricating same |
WO2005122267A2 (en) | 2004-06-03 | 2005-12-22 | The Regents Of The University Of California | Growth of planar reduced dislocation density m-plane gallium nitride by hydride vapor phase epitaxy |
US7125785B2 (en) | 2004-06-14 | 2006-10-24 | International Business Machines Corporation | Mixed orientation and mixed material semiconductor-on-insulator wafer |
US7807921B2 (en) | 2004-06-15 | 2010-10-05 | The Boeing Company | Multijunction solar cell having a lattice mismatched GrIII-GrV-X layer and a composition-graded buffer layer |
US7244958B2 (en) | 2004-06-24 | 2007-07-17 | International Business Machines Corporation | Integration of strained Ge into advanced CMOS technology |
US6991998B2 (en) * | 2004-07-02 | 2006-01-31 | International Business Machines Corporation | Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer |
US7384829B2 (en) * | 2004-07-23 | 2008-06-10 | International Business Machines Corporation | Patterned strained semiconductor substrate and device |
WO2006015185A2 (en) * | 2004-07-30 | 2006-02-09 | Aonex Technologies, Inc. | GaInP/GaAs/Si TRIPLE JUNCTION SOLAR CELL ENABLED BY WAFER BONDING AND LAYER TRANSFER |
US20060211210A1 (en) | 2004-08-27 | 2006-09-21 | Rensselaer Polytechnic Institute | Material for selective deposition and etching |
TWI442456B (zh) | 2004-08-31 | 2014-06-21 | Sophia School Corp | 發光元件 |
US20060073681A1 (en) | 2004-09-08 | 2006-04-06 | Han Sang M | Nanoheteroepitaxy of Ge on Si as a foundation for group III-V and II-VI integration |
US7002175B1 (en) * | 2004-10-08 | 2006-02-21 | Agency For Science, Technology And Research | Method of making resonant tunneling diodes and CMOS backend-process-compatible three dimensional (3-D) integration |
US7846759B2 (en) | 2004-10-21 | 2010-12-07 | Aonex Technologies, Inc. | Multi-junction solar cells and methods of making same using layer transfer and bonding techniques |
US20060105533A1 (en) | 2004-11-16 | 2006-05-18 | Chong Yung F | Method for engineering hybrid orientation/material semiconductor substrate |
FR2878535B1 (fr) * | 2004-11-29 | 2007-01-05 | Commissariat Energie Atomique | Procede de realisation d'un substrat demontable |
US20060113603A1 (en) | 2004-12-01 | 2006-06-01 | Amberwave Systems Corporation | Hybrid semiconductor-on-insulator structures and related methods |
US20060131606A1 (en) | 2004-12-18 | 2006-06-22 | Amberwave Systems Corporation | Lattice-mismatched semiconductor structures employing seed layers and related fabrication methods |
KR100682873B1 (ko) * | 2004-12-28 | 2007-02-15 | 삼성전기주식회사 | 반도체 발광 소자 및 그 제조 방법 |
US7405436B2 (en) | 2005-01-05 | 2008-07-29 | International Business Machines Corporation | Stressed field effect transistors on hybrid orientation substrate |
JP2006196631A (ja) | 2005-01-13 | 2006-07-27 | Hitachi Ltd | 半導体装置及びその製造方法 |
US7138309B2 (en) | 2005-01-19 | 2006-11-21 | Sharp Laboratories Of America, Inc. | Integration of biaxial tensile strained NMOS and uniaxial compressive strained PMOS on the same wafer |
US7344942B2 (en) | 2005-01-26 | 2008-03-18 | Micron Technology, Inc. | Isolation regions for semiconductor devices and their formation |
US7224033B2 (en) | 2005-02-15 | 2007-05-29 | International Business Machines Corporation | Structure and method for manufacturing strained FINFET |
JP2006253181A (ja) | 2005-03-08 | 2006-09-21 | Seiko Epson Corp | 半導体装置および半導体装置の製造方法 |
KR100712753B1 (ko) | 2005-03-09 | 2007-04-30 | 주식회사 실트론 | 화합물 반도체 장치 및 그 제조방법 |
US20070267722A1 (en) | 2006-05-17 | 2007-11-22 | Amberwave Systems Corporation | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
US8324660B2 (en) | 2005-05-17 | 2012-12-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
JP5063594B2 (ja) * | 2005-05-17 | 2012-10-31 | 台湾積體電路製造股▲ふん▼有限公司 | 転位欠陥密度の低い格子不整合半導体構造およびこれに関連するデバイス製造方法 |
US9153645B2 (en) * | 2005-05-17 | 2015-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication |
JP2006332295A (ja) | 2005-05-26 | 2006-12-07 | Matsushita Electric Ind Co Ltd | ヘテロ接合バイポーラトランジスタ及びヘテロ接合バイポーラトランジスタの製造方法 |
TW200703463A (en) | 2005-05-31 | 2007-01-16 | Univ California | Defect reduction of non-polar and semi-polar III-nitrides with sidewall lateral epitaxial overgrowth (SLEO) |
KR20060131327A (ko) * | 2005-06-16 | 2006-12-20 | 엘지전자 주식회사 | 발광 다이오드의 제조 방법 |
US7626246B2 (en) | 2005-07-26 | 2009-12-01 | Amberwave Systems Corporation | Solutions for integrated circuit integration of alternative active area materials |
US7801406B2 (en) * | 2005-08-01 | 2010-09-21 | Massachusetts Institute Of Technology | Method of fabricating Ge or SiGe/Si waveguide or photonic crystal structures by selective growth |
US20070054467A1 (en) | 2005-09-07 | 2007-03-08 | Amberwave Systems Corporation | Methods for integrating lattice-mismatched semiconductor structure on insulators |
US7638842B2 (en) | 2005-09-07 | 2009-12-29 | Amberwave Systems Corporation | Lattice-mismatched semiconductor structures on insulators |
JP4462249B2 (ja) * | 2005-09-22 | 2010-05-12 | ソニー株式会社 | 発光ダイオードの製造方法、集積型発光ダイオードの製造方法および窒化物系iii−v族化合物半導体の成長方法 |
US7358107B2 (en) | 2005-10-27 | 2008-04-15 | Sharp Laboratories Of America, Inc. | Method of fabricating a germanium photo detector on a high quality germanium epitaxial overgrowth layer |
KR101316947B1 (ko) | 2005-11-01 | 2013-10-15 | 메사추세츠 인스티튜트 오브 테크놀로지 | 모놀리식 집적 반도체 재료 및 소자 |
TW200733424A (en) | 2005-11-04 | 2007-09-01 | Univ California | High light extraction efficiency light emitting diode (LED) |
US7977703B2 (en) * | 2005-11-22 | 2011-07-12 | Rohm Co., Ltd. | Nitride semiconductor device having a zinc-based substrate |
JP2007158100A (ja) * | 2005-12-06 | 2007-06-21 | Rohm Co Ltd | 窒化物半導体発光素子の製造方法 |
JP2007196165A (ja) * | 2006-01-27 | 2007-08-09 | National Institute For Materials Science | 新規なデバイス |
US7629661B2 (en) | 2006-02-10 | 2009-12-08 | Noble Peak Vision Corp. | Semiconductor devices with photoresponsive components and metal silicide light blocking structures |
KR100790869B1 (ko) | 2006-02-16 | 2008-01-03 | 삼성전자주식회사 | 단결정 기판 및 그 제조방법 |
US7691698B2 (en) | 2006-02-21 | 2010-04-06 | International Business Machines Corporation | Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain |
WO2007112066A2 (en) * | 2006-03-24 | 2007-10-04 | Amberwave Systems Corporation | Lattice-mismatched semiconductor structures and related methods for device fabrication |
CN101114661A (zh) * | 2006-07-25 | 2008-01-30 | 格科微电子(上海)有限公司 | Cmos图像传感器 |
WO2008030574A1 (en) | 2006-09-07 | 2008-03-13 | Amberwave Systems Corporation | Defect reduction using aspect ratio trapping |
WO2008036256A1 (en) | 2006-09-18 | 2008-03-27 | Amberwave Systems Corporation | Aspect ratio trapping for mixed signal applications |
WO2008039495A1 (en) | 2006-09-27 | 2008-04-03 | Amberwave Systems Corporation | Tri-gate field-effect transistors formed by aspect ratio trapping |
WO2008039534A2 (en) | 2006-09-27 | 2008-04-03 | Amberwave Systems Corporation | Quantum tunneling devices and circuits with lattice- mismatched semiconductor structures |
US20080154197A1 (en) | 2006-12-20 | 2008-06-26 | Joel Brian Derrico | System and method for regulating the temperature of a fluid injected into a patient |
JP2008198656A (ja) | 2007-02-08 | 2008-08-28 | Shin Etsu Chem Co Ltd | 半導体基板の製造方法 |
US8237151B2 (en) | 2009-01-09 | 2012-08-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diode-based devices and methods for making the same |
US7825328B2 (en) | 2007-04-09 | 2010-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Nitride-based multi-junction solar cell modules and methods for making the same |
US8304805B2 (en) | 2009-01-09 | 2012-11-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor diodes fabricated by aspect ratio trapping with coalesced films |
US9508890B2 (en) | 2007-04-09 | 2016-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Photovoltaics on silicon |
KR20080102065A (ko) | 2007-05-18 | 2008-11-24 | 삼성전자주식회사 | 에피택시얼 실리콘 구조물 형성 방법 및 이를 이용한 반도체 소자의 형성 방법 |
US8329541B2 (en) * | 2007-06-15 | 2012-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | InP-based transistor fabrication |
KR20090010284A (ko) | 2007-07-23 | 2009-01-30 | 엘지이노텍 주식회사 | 반도체 발광소자 및 그 제조방법 |
JP2007300146A (ja) * | 2007-08-20 | 2007-11-15 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
CN101884117B (zh) | 2007-09-07 | 2013-10-02 | 台湾积体电路制造股份有限公司 | 多结太阳能电池 |
US7883990B2 (en) | 2007-10-31 | 2011-02-08 | International Business Machines Corporation | High resistivity SOI base wafer using thermally annealed substrate |
KR20100094460A (ko) | 2007-12-28 | 2010-08-26 | 스미또모 가가꾸 가부시키가이샤 | 반도체 기판, 반도체 기판의 제조 방법 및 전자 디바이스 |
CN101946307B (zh) * | 2008-03-01 | 2012-12-19 | 住友化学株式会社 | 半导体基板、半导体基板的制造方法及电子装置 |
JP4247413B1 (ja) * | 2008-03-19 | 2009-04-02 | 株式会社 東北テクノアーチ | デバイスの製造方法 |
US8183667B2 (en) | 2008-06-03 | 2012-05-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial growth of crystalline material |
US8274097B2 (en) * | 2008-07-01 | 2012-09-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reduction of edge effects from aspect ratio trapping |
US8981427B2 (en) * | 2008-07-15 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polishing of small composite semiconductor materials |
US8034697B2 (en) | 2008-09-19 | 2011-10-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of devices by epitaxial layer overgrowth |
US20100072515A1 (en) | 2008-09-19 | 2010-03-25 | Amberwave Systems Corporation | Fabrication and structures of crystalline material |
US8253211B2 (en) | 2008-09-24 | 2012-08-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor sensor structures with reduced dislocation defect densities |
WO2010114956A1 (en) | 2009-04-02 | 2010-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Devices formed from a non-polar plane of a crystalline material and method of making the same |
-
2010
- 2010-01-08 US US12/684,499 patent/US8304805B2/en active Active
- 2010-05-04 SG SG2010031417A patent/SG173245A1/en unknown
- 2010-06-17 KR KR20100057747A patent/KR20110081742A/ko active Search and Examination
- 2010-07-02 EP EP10006883.2A patent/EP2343742B1/en active Active
- 2010-07-08 TW TW99122432A patent/TWI427830B/zh active
- 2010-07-09 CN CN2010102295095A patent/CN102122675B/zh active Active
- 2010-07-09 JP JP2010156436A patent/JP5399335B2/ja active Active
-
2012
- 2012-10-12 US US13/650,206 patent/US8765510B2/en active Active
- 2012-12-04 JP JP2012265450A patent/JP5829598B2/ja active Active
-
2014
- 2014-05-27 US US14/288,197 patent/US9029908B2/en active Active
-
2015
- 2015-03-16 JP JP2015052114A patent/JP6484076B2/ja active Active
- 2015-04-13 US US14/685,399 patent/US9449868B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080093622A1 (en) * | 2006-10-19 | 2008-04-24 | Amberwave Systems Corporation | Light-Emitter-Based Devices with Lattice-Mismatched Semiconductor Structures |
TW200828465A (en) * | 2006-12-21 | 2008-07-01 | Taiwan Semiconductor Mfg | Methods for fabricating semiconductor structures and probing dies |
Also Published As
Publication number | Publication date |
---|---|
EP2343742A3 (en) | 2014-03-19 |
TW201125162A (en) | 2011-07-16 |
JP5399335B2 (ja) | 2014-01-29 |
CN102122675B (zh) | 2013-04-17 |
US20100176371A1 (en) | 2010-07-15 |
JP2013048301A (ja) | 2013-03-07 |
CN102122675A (zh) | 2011-07-13 |
US20140264272A1 (en) | 2014-09-18 |
EP2343742A2 (en) | 2011-07-13 |
EP2343742B1 (en) | 2019-03-13 |
KR20110081742A (ko) | 2011-07-14 |
US9449868B2 (en) | 2016-09-20 |
JP5829598B2 (ja) | 2015-12-09 |
JP6484076B2 (ja) | 2019-03-13 |
US8304805B2 (en) | 2012-11-06 |
JP2015130530A (ja) | 2015-07-16 |
US20150221546A1 (en) | 2015-08-06 |
US9029908B2 (en) | 2015-05-12 |
SG173245A1 (en) | 2011-08-29 |
JP2011142294A (ja) | 2011-07-21 |
US8765510B2 (en) | 2014-07-01 |
US20130034924A1 (en) | 2013-02-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI427830B (zh) | 光電裝置之製造方法 | |
US9853118B2 (en) | Diode-based devices and methods for making the same | |
JP5420137B2 (ja) | テクスチャ基板上で成長させるiii族発光素子 | |
TWI469187B (zh) | 電路結構 | |
JP2012522402A (ja) | 結晶物質の非極性面から形成される装置とその製作方法 | |
KR101146819B1 (ko) | 단결정 기판의 제조방법, 이에 의해 제조된 단결정 기판, 상기 단결정 기판을 포함하는 발광소자, 및 이의 제조방법 | |
KR20110097007A (ko) | 질화물 반도체 박막 성장 방법 |