JP6943314B2 - 集積回路デバイス及び方法 - Google Patents
集積回路デバイス及び方法 Download PDFInfo
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- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
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Description
EFF=|Vout/VDDIO|
に制限され得ることが知られる。ここで、VoutはVBP又はVBNである。例えば、VBN=−0.6V及びVDDIO=2.5Vであるとすると、効率は24%に満たない。
(付記1)
集積回路デバイスであって、
当該集積回路デバイスの電源電圧とは異なる第1ボディバイアス電圧を生成するよう構成される少なくとも1つの第1ボディバイアス回路と、
第1ボディバイアスノードを第1電源電圧に設定し、その後に前記第1ボディバイアスノードが前記第1ボディバイアス電圧に設定されることを可能にするよう構成される少なくとも1つの第1バイアス制御回路と、
前記第1ボディバイアスノードへ接続されるボディを備える複数の第1トランジスタと
を有する集積回路デバイス。
(付記2)
前記第1バイアス制御回路は、前記第1電源電圧が所定レベルに達した後に前記第1ボディバイアスノードを前記第1電源電圧に設定するよう構成される、
付記1に記載の集積回路デバイス。
(付記3)
前記第1バイアス制御回路は、該第1バイアス制御回路への電源電圧がない場合に前記第1ボディバイアスノードを前記第1電源電圧に設定するよう構成される、
付記2に記載の集積回路デバイス。
(付記4)
前記第1バイアス制御回路は、前記第1電源電圧と前記第1ボディバイアスノードとの間に結合されるソース−ドレイン経路を備えるデプレッション形トランジスタを含む、
付記3に記載の集積回路デバイス。
(付記5)
当該集積回路デバイスの電源電圧及び前記第1ボディバイアス電圧とは異なる第2ボディバイアス電圧を生成するよう構成される第2ボディバイアス回路と、
第2ボディバイアスノードを第2電源電圧に設定し、その後に前記第2ボディバイアスノードを前記第2ボディバイアス電圧に設定するよう構成される第2バイアス制御回路と、
前記第2ボディバイアスノードへ接続されるボディを備える複数の第2トランジスタと
を更に有する付記1に記載の集積回路デバイス。
(付記6)
前記第1トランジスタはnチャネルトランジスタであり、前記第2トランジスタはpチャネルトランジスタである、
付記5に記載の集積回路デバイス。
(付記7)
当該集積回路デバイスは、第1の高電源電圧と、該第1の高電源電圧よりも大きい第2の高電源電圧と、低電源電圧とを受け、
前記第1バイアス制御回路は、前記第2の高電源電圧から給電され、該第2の高電源電圧に応答して前記第1ボディバイアスノードを前記第1電源電圧に設定し、前記第1の高電源電圧が所定レベルに達することに応答して前記第1ボディバイアスノードを前記第1ボディバイアス電圧に設定するよう構成される、
付記1に記載の集積回路デバイス。
(付記8)
前記第1の高電源電圧は1.5ボルトよりも小さく、前記第2の高電源電圧は1.5ボルトよりも大きい、
付記7に記載の集積回路デバイス。
(付記9)
前記第1バイアス制御回路は、前記第1電源電圧と前記第1ボディバイアスノードとの間に結合されるソース−ドレイン経路を備えるクランピングトランジスタと、前記第1ボディバイアス回路が前記第1ボディバイアス電圧を発現させている最中は前記クランピングトランジスタを有効にし、前記第1ボディバイアス電圧が確立される場合に前記クランピングトランジスタを無効にするよう構成されるゲート制御回路とを含み、
前記クランピングトランジスタは、絶縁ゲート形電界効果トランジスタ及び接合形電界効果トランジスタのグループから選択される、
付記1に記載の集積回路デバイス。
(付記10)
前記第1トランジスタの少なくとも一部はDDCトランジスタを有し、夫々のDDCトランジスタは、実質的に非ドープのチャネルの下に形成されたスクリーニング領域を備え、該スクリーニング領域は、当該DDCトランジスタのソース及びドレインの導電型とは反対の導電型のドーパントを含む1×1018ドーパントatoms/cm3に満たないドーパント濃度を有する、
付記1に記載の集積回路デバイス。
(付記11)
集積回路デバイスに第1電源電圧を印加し、
最初に少なくとも1つの第1ボディバイアスノードを前記第1電源電圧にクランピングし、
前記第1電源電圧により少なくとも1つの第1ボディバイアス電圧を生成し、
その後に前記第1ボディバイアスノードが前記第1ボディバイアス電圧によって駆動されることを可能にし、
前記第1ボディバイアスノードは、前記第1ボディバイアス電圧を複数の第1トランジスタのボディへ供給する、
方法。
(付記12)
前記第1電源電圧により前記第1ボディバイアス電圧を生成するより前に、前記第1電源電圧よりも大きい第2電源電圧によりクランプイネーブル信号を生成し、
前記第1ボディバイアスノードは、前記クランプイネーブル信号に応答して前記第1電源電圧にクランピングされる、
付記11に記載の方法。
(付記13)
最初に前記第1ボディバイアスノードを前記第1電源電圧にクランピングすることは、前記第1電源電圧が発現しようとしている最中に起こる、
付記11に記載の方法。
(付記14)
最初に第2ボディバイアスノードを第2電源電圧にクランピングし、
前記第1電源電圧により第2ボディバイアス電圧を生成し、
その後に前記第2ボディバイアスノードが前記第2ボディバイアス電圧によって駆動されることを可能にし、
前記第2ボディバイアスノードは、前記第2ボディバイアス電圧を複数の第2トランジスタのボディへ供給する、
付記11に記載の方法。
(付記15)
前記第1ボディバイアス電圧は、前記第1電源電圧よりも大きい逆方向pチャネルボディバイアス電圧(VBP)、及び低電源電圧よりも小さい逆方向nチャネルボディバイアス電圧(VBN)のグループから選択される逆方向ボディバイアス電圧である、
付記11に記載の方法。
(付記16)
逆方向VBPは、前記第1電源電圧よりも0.1ボルトから1.0ボルト大きい範囲をとり、前記逆方向VBNは、前記低電源電圧よりも0.1ボルトから1.0ボルト小さい範囲をとる、
付記15に記載の方法。
(付記17)
前記第1トランジスタの少なくとも一部はDDCトランジスタを有し、夫々のDDCトランジスタは、実質的に非ドープのチャネルの下に形成されたスクリーニング領域を備え、該スクリーニング領域は、当該DDCトランジスタのソース及びドレインの導電型とは反対の導電型のドーパントを含み且つ1×1018ドーパントatoms/cm3に満たないドーパント濃度を有する、
付記11に記載の方法。
(付記18)
第1電源電圧を受けるよう構成される第1電源接続と、
前記第1電源電圧よりも大きい第2電源電圧を受けるよう構成される第2電源接続と、
発生器電源ノードで電力を受けるよう結合され、第1ボディバイアス電圧を生成するよう構成される少なくとも1つの第1ボディバイアス発生器回路と、
前記第1電源接続又は前記第2電源接続のどちらか一方を前記発生器電源ノードへ結合するよう構成されるスイッチ回路と、
前記第1ボディバイアス電圧を受けるよう結合されるボディを備える複数の第1トランジスタと
を有する集積回路デバイス。
(付記19)
前記第2電源電圧を前記第1ボディバイアス発生器回路への印加より前にレギュレートするよう構成される電圧レギュレータ
を更に有する付記18に記載の集積回路デバイス。
(付記20)
前記第1トランジスタの少なくとも一部はDDCトランジスタを有し、夫々のDDCトランジスタは、実質的に非ドープのチャネルの下に形成されたスクリーニング領域を備え、該スクリーニング領域は、当該DDCトランジスタのソース及びドレインの導電型とは反対の導電型のドーパントを含む1×1018ドーパントatoms/cm3に満たないドーパント濃度を有する、
付記18に記載の集積回路デバイス。
102 ボディバイアス発生器回路
104 スイッチ回路
106 電圧レギュレータ
202−0,302−0 PBB発生器回路
202−1,302−1 NBB発生器回路
204−0,304−0 第1クランプ回路
204−1,304−1 第2クランプ回路
214,314 クランプ制御回路
420,520,620,720 クランピングトランジスタ
1000 クランピング回路
1171 DDCトランジスタ
1181 実質的に非ドープのチャネル
1187 スクリーニング領域
1189 閾電圧設定領域
CTRL 制御信号
VBx,VBP_Gen,VBN_Gen ボディバイアス電圧
VDD 第1電源電圧
VDDIn 電源電圧
VDDIO 第2電源電圧
Claims (8)
- 第1電源電圧を受けるよう構成される第1電源接続と、
前記第1電源電圧よりも大きく、前記第1電源電圧よりも前に立ち上がる第2電源電圧を受けるよう構成される第2電源接続と、
発生器電源ノードで電力を受けるよう結合され、第1ボディバイアス電圧を生成するよう構成される少なくとも1つの第1ボディバイアス発生器回路と、
前記第1電源電圧が立ち上がり中であるときに前記第2電源接続を前記発生器電源ノードへ結合し、前記第1電源電圧の立ち上がりが完了し、安定したレベルに達した後に、前記第1電源接続を前記発生器電源ノードへ結合するよう構成されるスイッチ回路と、
前記第1ボディバイアス電圧を受けるよう結合されるボディを備える複数の第1トランジスタと
を有する集積回路デバイス。 - 前記第2電源電圧を前記第1ボディバイアス発生器回路への印加より前にレギュレートするよう構成される電圧レギュレータ
を更に有する請求項1に記載の集積回路デバイス。 - 前記電圧レギュレータは、前記第1電源電圧の立ち上がりが完了したときの電圧を得るようにレギュレートする、
請求項2に記載の集積回路デバイス。 - 前記第1トランジスタの少なくとも一部はDDCトランジスタを有し、夫々のDDCトランジスタは、非ドープのチャネルの下に形成されたスクリーニング領域を備え、該スクリーニング領域は、当該DDCトランジスタのソース及びドレインの導電型とは反対の導電型のドーパントを含み、5×1018から1×1020ドーパントatoms/cm3の間のドーパント濃度を有する、
請求項1に記載の集積回路デバイス。 - 前記第1電源電圧は、前記第1トランジスタへと供給される、
請求項1に記載の集積回路デバイス。 - 集積回路デバイスに第1電源電圧と、前記第1電源電圧よりも大きく、且つ前記第1電源電圧よりも前に立ち上がる第2電源電圧とを印加し、
前記第1電源電圧又は前記第2電源電圧により第1ボディバイアス電圧を生成することを可能とし、
前記第1電源電圧が立ち上がり中であるときに前記第2電源電圧により前記第1ボディバイアス電圧を生成し、
前記第1電源電圧の立ち上がりが完了し、安定したレベルに達したときに前記第1電源電圧により前記第1ボディバイアス電圧を生成し、
前記第1ボディバイアス電圧を複数の第1トランジスタのボディへ供給する、
方法。 - 前記第2電源電圧は、前記集積回路デバイスの前記第1ボディバイアス電圧を生成する第1ボディバイアス発生器回路へ印加される前に、電圧レギュレータによりレギュレートされる、
請求項6に記載の方法。 - 前記電圧レギュレータは、前記第1電源電圧の立ち上がりが完了したときの電圧を得るようにレギュレートする、
請求項7に記載の方法。
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US14/341,733 | 2014-07-25 | ||
US14/341,733 US9710006B2 (en) | 2014-07-25 | 2014-07-25 | Power up body bias circuits and methods |
JP2015140054A JP6746881B2 (ja) | 2014-07-25 | 2015-07-13 | 電源立ち上げ時のボディバイアス電圧を確立する集積回路デバイス及び方法 |
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US9811625B2 (en) * | 2015-04-28 | 2017-11-07 | Arm Limited | Computer-implemented method and computer program for generating a layout of a circuit block of an integrated circuit |
US9627529B1 (en) * | 2015-05-21 | 2017-04-18 | Altera Corporation | Well-tap structures for analog matching transistor arrays |
US10387690B2 (en) * | 2016-04-21 | 2019-08-20 | Texas Instruments Incorporated | Integrated power supply scheme for powering memory card host interface |
US10003325B2 (en) | 2016-08-01 | 2018-06-19 | Samsung Electronics Co., Ltd. | System and method for providing an area efficient and design rule check (DRC) friendly power sequencer for digital circuits |
KR102044629B1 (ko) * | 2018-05-09 | 2019-11-13 | 광운대학교 산학협력단 | 낮은 온-저항을 갖는 cmos 스위치 |
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US20160026207A1 (en) | 2016-01-28 |
CN105429618B (zh) | 2018-12-11 |
US9710006B2 (en) | 2017-07-18 |
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