CN100477092C - 利用固相外延再生长的具有降低的结泄漏的半导体衬底及其制作方法 - Google Patents

利用固相外延再生长的具有降低的结泄漏的半导体衬底及其制作方法 Download PDF

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CN100477092C
CN100477092C CNB2004800379563A CN200480037956A CN100477092C CN 100477092 C CN100477092 C CN 100477092C CN B2004800379563 A CNB2004800379563 A CN B2004800379563A CN 200480037956 A CN200480037956 A CN 200480037956A CN 100477092 C CN100477092 C CN 100477092C
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B·J·保拉克
R·J·杜菲
R·林赛
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Abstract

制作半导体器件的方法，包括：a)提供半导体衬底，b)通过适当的注入在半导体衬底的顶层中制作第一非晶层，该第一非晶层具有第一深度，c)在半导体衬底中注入第一掺杂剂以便为第一非晶层提供第一掺杂轮廓，d)施加第一固相外延再生长操作以局部地再生长第一非晶层，并形成具有小于第一深度的第二深度的第二非晶层，以及激活第一掺杂剂，e)在半导体衬底中注入第二掺杂剂以便为第二非晶层提供具有比第一掺杂轮廓高的掺杂浓度的第二掺杂轮廓，f)施加第二固相外延再生长操作以再生长第二非晶层并激活第二掺杂剂。

Description

利用固相外延再生长的具有降低的结泄漏的半导体衬底及其制作方法
技术领域
本发明涉及制作半导体器件的方法，其中使用固相外延再生长技术来制作浅结。
背景技术
US-A-6,063,682公开了SPER技术。根据该现有技术文献，在硅衬底中注入重离子。注入的重离子在衬底的顶表面处形成非晶层。该非晶层没有沟道。接着，执行硅注入步骤以形成与衬底顶层内的填隙相比过量的空位。由于非晶化的硅层没有沟道，因此注入的深度主要受限于该非晶化的硅层。
用于将来的CMOS技术节点代的最有前途的方法之一是低温处理。这是由于几个原因，例如需要降低的热预算的金属栅和结形成引起的。通过固相外延再生长(SPER)形成的超浅的(源极和漏极延伸)结可以利用良好的亚稳态B激活、有限的掺杂剂扩散和极好的陡度而获得。用于结再生长的典型温度在T＝550℃和T＝750℃之间。在这些低温下的处理并没有完全除去注入后损伤，因此这些结遭受了更高的漏电流。深能级瞬态谱(DLTS)研究表明，典型缺陷位于导带下面0.457eV。
然而，连同结中的高掺杂剂激活水平和极好的结陡度，带与带之间漏电流的显著增加也已经被观察到。
发明内容
因此，本发明的目的是提供制作如开始时所述的半导体器件的方法，其降低了结的漏电流。
为了实现该目的，本发明提供制作半导体器件的方法，包括：
a)提供半导体衬底，
b)通过注入在半导体衬底的顶层中制作第一非晶层，该第一非晶层具有第一深度，
c)在半导体衬底中注入第一掺杂剂以便为第一非晶层提供第一掺杂轮廓，
d)应用第一固相外延再生长操作以部分地再生长第一非晶层，并形成具有小于第一深度的第二深度的第二非晶层，以及激活第一掺杂剂，
e)在半导体衬底中注入第二掺杂剂以便为第二非晶层提供具有比第一掺杂轮廓更高的掺杂浓度的第二掺杂轮廓，
f)应用第二固相外延再生长操作以再生长第二非晶层并激活第二掺杂剂。
通过该方法，提供具有接近衬底表面的两个浅区域的半导体衬底。邻近衬底的顶表面设置的第一区域具有比邻近第一区域并延伸进入衬底的第二区域更高的掺杂水平。该第二区域可以被制作得比第一区域更浅。例如，邻近表面的第一区域可以具有6-12nm的厚度，而第二区域可以具有2-4nm的厚度。由于掺杂水平不同，因此能够有效地降低来自第一区域的跨越结的漏电流。
根据本发明的实施例，该方法包括，在操作b)之前，注入初始掺杂剂以提供比第一非晶层延伸得更深的HALO注入。
在另一实施例中，本发明涉及利用固相外延再生长技术制作的半导体器件，其包括带有具有第一电导率轮廓的第一区域和具有第二电导率轮廓的第二区域的半导体衬底，该第一区域具有6-12nm的厚度并邻近半导体衬底的顶表面设置，以及该第二区域具有2-4nm的厚度并邻近第一区域设置，该第二电导率轮廓具有比第一电导率轮廓更低的电导率。
此外，本发明涉及包括这种器件的金属氧化物半导体器件。
最后，本发明涉及设有这种半导体器件的装置。
现在将参考一些图来说明本发明，其仅仅旨在说明本发明，并不旨在限制它的范围。该范围仅由附加到该说明书的权利要求的限定及其技术等价物来限制。
附图说明
图1a-1f示出制作根据本发明的半导体器件的不同阶段。
图2示出根据从现有技术得知的方法，在半导体衬底中作为深度的函数的掺杂剂浓度和电导率轮廓的实例。
图3示出根据本发明，在半导体衬底中作为深度的函数的掺杂剂浓度和电导率轮廓的实例。
具体实施方式
在下面的描述中，在全部图中相同的参考数字指的是相同的元件。图1a-1f涉及利用本发明制作金属氧化物半导体器件。然而，正如对本领域技术人员来说显而易见的，这些发明特征可以应用在任何其它类型的需要浅结的半导体器件的制作中。
图1a示出p型半导体衬底1。场氧化物区3设置在半导体衬底1的顶表面上。在特定位置处，利用本领域技术人员已知的技术提供薄氧化物层5。然后，薄氧化物层5可以用作将要制作的MOS器件内的栅氧化物层。然而，本发明并不限于应用薄氧化物层5来获得希望的效果，这将在下面的描述中可以清楚地看到。
图1a的结构设有适当的光致抗蚀剂层30，在薄氧化物层5之上具有开口。随后，执行注入操作以在衬底1内制作n阱11。
薄氧化物层5可以被除去并被新的新鲜氧化物层代替，并且以后用作将要制作的MOS器件中的栅氧化物层。然而，在此假定薄氧化物层5保留在原位。如图1c所示，在薄氧化物层5的顶部上，提供多晶硅层13，其随后将用作将要制作的MOS器件的栅极。
执行非晶化注入15以在衬底1的顶部中制作非晶层。限定非晶层深度的注入深度用参考数字17表示。可以使用Ge、GeF2或Si来执行用以制作该非晶层的注入主5。然而，替代地，可以应用诸如铟之类的其它原子。通过该注入，在非晶层中消除了硅衬底1中的沟道。
制作非晶层的这个步骤之后是随后的掺杂剂注入，例如利用硼(B)、磷(P)、砷(As)或铟(In)。由于在非晶层内不存在沟道，因此诸如硼之类的掺杂剂注入原子将渗透硅衬底1直到仅略微在非晶层下方的深度。这种随后的掺杂剂注入的深度用参考数字19表示。应当理解，注入的深度19仅略微大于非晶层的深度17。虚线17和顶表面之间的距离以及虚线19和衬底1的顶表面之间的距离没有按照比例绘制。绘制它们仅用以说明本发明的原理。
现在参考图2。
图2示出硅衬底的顶部、非晶层的深度17和硼(作为实例)的注入深度19。硼轮廓对应于现有技术文献US-A-6,063,682中所示的硼轮廓。
下一操作是应用所谓的低温方法，即固相外延再生长(SPER)技术。在SPER中，硅晶体首先被预非晶化，然后被掺杂并且最终在典型在550℃和750℃之间的温度下被再生长。通过这种温度操作，非晶层被再生长并且掺杂剂(例如硼)被激活。SPER的主要优点是有限的掺杂剂扩散(几乎不超过非晶层17)和上述的固溶性掺杂剂激活。
然而，实验已经表明，SPER的低温操作并没有完全除去注入后损伤。因此，利用SPER制作的结会遭受更高的漏电流。
本发明提出利用参考图3解释的方法来解决这一问题。
图3再次示出硅衬底的顶部区域。图3以比图2更大的尺度示出非晶层的深度17。
非晶层17可以通过注入Ge、GeF2、Si、Ar或Xe原子中的至少一种来制作。当使用Ge时，典型能量可以在2-30keV之间，并且典型剂量可以是1015原子/cm2。可以使用其它能量或剂量。
然后，以相当低的能量，半导体衬底1被注入掺杂剂，例如B。当注入B时，这种低能量一般可以在3-10keV之间。那么剂量一般可以是1014原子/cm2的数量级。产生表示为“低B浓度”的B掺杂浓度。可以使用P、As或In来代替B。
随后，根据本发明，利用SPER技术，并非完全地而仅仅是局部地再生长非晶层17。也就是说，仅在几秒钟期间执行在典型在550℃和750℃之间的温度下应用的SPER工艺。通过该SPER工艺，可以仅利用低激活的B来形成2-6nm的层。仅一部分较早的层17保持非晶，如虚线21所示。也就是说，衬底从虚线17再生长到虚线21，而非晶层保留在虚线21和半导体表面之间。从半导体表面到虚线21的深度可以是6-12nm。
接着，例如再次使用B进行另一掺杂剂注入。能量范围一般可以在0.5和3keV之间。典型剂量可以是1015原子/cm2的数量级。这些B原子一般将不会更深于剩余非晶层的深度，即达到虚线21。可以使用P、As或In来代替B。
仅在该操作之后，才完全地再生长非晶层21的剩余部分。这再次利用SPER工艺来完成。典型温度范围也是在550℃和750℃之间。然而，所需的典型时间为1分钟的数量级。
因而，邻近半导体表面的顶部区域产生了具有两个组合的掺杂剂浓度，即，在邻近半导体表面的第一区域中具有比邻近第一区域的第二区域中更高的掺杂水平。在虚线21和17之间的第二区域具有比在半导体表面和虚线21之间的第一区域更低的掺杂水平。在完成该操作之后，形成如图3所示的电导率轮廓，其在半导体表面和虚线21之间的区域中具有比在虚线21和虚线17之间的区域中更高的电导率。
实验已经表明，在完成图3所示的结构之后，虚线21和17之间的区域中掺杂剂的激活水平越高，泄漏减少则越低。例如，虚线21和17之间的区域中的典型激活水平可以是6.5×1019Bat/cm2。然而，同时，研究表明，如果虚线21和17之间的区域宽度超过6nm，则不存在进一步的改善。
正如下面将要解释的，半导体表面和虚线17之间的区域最终将形成晶体管的源极/漏极延伸。利用上述方法，该区域的掺杂可以仍被高度激活，其使得调节包括这种源极/漏极延伸的晶体管的开/关电流成为可能。换句话说，对将要制作的晶体管沟道区具有良好的控制。
现在，将参考图1d-1f来解释将要制作的半导体器件的完成。
如图1d所示，在SPER工艺之后，产生轻掺杂区18，其将成为衬底1上的MOS晶体管的源/漏延伸区。这些掺杂区18的深度将基本等于较早的非晶层的深度17。
在该结构的顶部上，淀积间隔材料21。间隔材料21可以是二氧化硅。然而，可以使用其它的间隔材料，正如本领域技术人员所已知的。
采用仅保留与多晶硅层13相邻的侧间隔物23的方式，利用合适的刻蚀剂刻蚀间隔材料21。参见图1e。这全都是现有技术并且在此不需要进一步解释。应当注意，由于刻蚀工艺，仅保留了薄氧化物层5的一部分，即在多晶硅层13下面的部分和侧间隔物23下面的部分。通过刻蚀工艺除去薄氧化物层5的位于其它地方的部分。
如图1f所示，执行进一步的离子注入操作。在所示的实施例中，用以制作p+源区27和p+漏区152的是p+注入29。这些源和漏区27、25比在前的掺杂区18在衬底1中延伸得更深。侧间隔物23用作掩模以保护在前的掺杂区18的部分免受该后来的p+注入29的影响。因此，在该操作之后保留了延伸区18。
正如本领域的技术人员已知的，通过例如提供合适的硅化物工艺以在漏极25、源极27和用作栅极的多晶硅层13上形成硅化物，来完成MOS器件的制作。这个后来的硅化物工艺是本领域的技术人员已知的，并且在图1f中没有示出。
正如对本领域技术人员来说显而易见的，本发明并不限于以上给出的实例。
例如，为了在非晶层的部分再生长之前和之后都注入掺杂剂，并不需要在半导体衬底表面上存在绝缘层5。
此外，本发明已经通过包括B的掺杂剂来制作源区和漏区的p型延伸而示出。然而，如果希望制作n型延伸，将使用其它类型的掺杂剂。此外，正如对本领域技术人员来说显而易见的，可以存在比延伸18延伸到衬底1中更深的HALO背景区域。图4示出这种HALO背景区域29，其比延伸区域18延伸到衬底1中更深，但是并不分别比源区和漏区27和25更深。这种HALO区域是本领域技术人员已知的，并且在此不需要进一步解释。为了制作这些HALO区域29，衬底1被注入导电类型与用于制作延伸区域18和19以及源区和漏区27、25的掺杂剂的导电类型相反的掺杂剂。在制作图1c和图3所示的非晶层17之前执行对halo区域29的这种注入。
通过在延伸区域18中，即在半导体衬底表面和虚线21之间的区域和在虚线21和17之间的区域、以及在HALO区域29中和图3所示的区域宽度中，应用最佳的激活水平组合可以获得希望的晶体管性能。

Claims (10)

1.制作半导体器件的方法，包括：
a)提供半导体衬底，
b)通过注入在所述半导体衬底的顶层中制作第一非晶层，所述第一非晶层具有第一深度，
c)在所述半导体衬底中注入第一掺杂剂，以便为所述第一非晶层提供第一掺杂轮廓，
d)应用第一固相外延再生长操作以部分地再生长所述第一非晶层，并形成具有小于所述第一深度的第二深度的第二非晶层，以及激活所述第一掺杂剂，
e)在所述半导体衬底中注入第二掺杂剂，以便为所述第二非晶层提供具有比所述第一掺杂轮廓更高的掺杂浓度的第二掺杂轮廓，
f)应用第二固相外延再生长操作，以再生长所述第二非晶层并激活所述第二掺杂剂。
2.根据权利要求1的方法，其中所述半导体衬底是Si衬底，并且利用Ge、GeF2、Si、Ar或Xe原子中的至少一种来执行操作b)。
3.根据权利要求2的方法，其中利用Ge在1015原子/cm2的剂量和2和30keV之间的能量下执行所述操作b)。
4.根据前述权利要求中的任何一个的方法，其中利用B、P、As和In中的至少一种在3和10keV之间的能量以及1014原子/cm2的剂量下执行所述操作c)。
5.根据权利要求5的方法，其中在550-750℃的温度下执行操作d)。
6.根据前述权利要求中的任何一个的方法，其中利用B、P、As和In中的至少一种在0.5和3keV之间的能量以及1015原子/cm2的剂量下执行所述操作e)。
7.根据前述权利要求中的任何一个的方法，其中在所述操作b)之前，注入初始掺杂剂以提供延伸得比所述第一非晶层更深的HALO注入区域。
8.利用固相外延再生长技术制作的半导体器件，包括带有具有第一电导率轮廓的第一区域和具有第二电导率轮廓的第二区域的半导体衬底，该第一区域具有6-12nm的厚度并邻近所述半导体衬底的顶表面设置，以及所述第二区域具有2-6nm的厚度并邻近所述第一区域设置，所述第二电导率轮廓具有比所述第一电导率轮廓更低的电导率。
9.包括如权利要求8所述的器件的金属氧化物半导体器件。
10.设有如权利要求8或9所述的半导体器件的装置。
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