CN100495663C - 集成电路的制造方法 - Google Patents

集成电路的制造方法 Download PDF

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CN100495663C
CN100495663C CNB2005101251667A CN200510125166A CN100495663C CN 100495663 C CN100495663 C CN 100495663C CN B2005101251667 A CNB2005101251667 A CN B2005101251667A CN 200510125166 A CN200510125166 A CN 200510125166A CN 100495663 C CN100495663 C CN 100495663C
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doped region
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CN1801468A (zh
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王志豪
王大维
胡正明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Abstract

本发明提供一种集成电路(IC)的制造方法，可在口袋掺杂与延伸掺杂完成后，于栅极侧壁形成超低温间隙壁；也可在超晕圈形成后，进行高斜角的延伸掺杂；或可在延伸掺杂后，进行固相外延，再进行低温制程，或者也可在进行口袋掺杂后，先进行热回火，然后再进行上述的延伸掺杂步骤；或者可先进行高能量低剂量的倾斜源极/漏极掺杂，再进行高剂量的源极/漏极掺杂。

Description

集成电路的制造方法
技术领域
本发明涉及一种集成电路(IC)的制造方法，特别是涉及一种可提高金属氧化物半导体晶体管(Metal Oxide Semiconductor Transistor；MOS)元件的性能的集成电路的制造方法。
背景技术
在集成电路元件的微型化趋势下，如何提高集成电路元件的性能是现今半导体界致力研究的重要课题之一。在集成电路元件中，互补式金属氧化物半导体晶体管(Complementary MOS；CMOS)的应用相当广泛。随着互补式金属氧化物半导体晶体管尺寸的持续缩减，以获得较佳的操作性能及较低的运转漏电流(Leakage Current)时，极易引发短通道效应。而短通道效应的产生将会严重影响元件的可靠性，并降低元件的性能。因此，在元件尺寸下降的同时，短通道效应的控制已成为互补式金属氧化物半导体晶体管发展的重要挑战之一。
此外，由于源极/漏极与基板的结电容(Junction Capacitance；Cj)的增加会导致元件的性能下降，因此如何有效降低结电容，也是提升互补式金属氧化物半导体晶体管元件的性能的重要关键之一。
另外，在进行基板的口袋掺杂与延伸掺杂时，极易因温度的变化，而使基板内部的掺质产生扩散，而无法有效掌控源极/漏极(Source/Drain；S/D)的范围。如此一来，不仅会导致元件的电可靠性下降，更会严重影响元件的操作性能。
发明内容
本发明的主要目的之一是提供一种集成电路的制造方法，其在口袋掺杂(Pocket Implant)与延伸掺杂(Extension Implant)后，以极低温沉积间隙壁材料并形成间隙壁(Spacer)后，再进行热回火。如此一来，可省略回火步骤，并避免快速暂态扩散(Transient Enhanced Diffusion；TED)的产生。
本发明的另一目的是提供一种集成电路的制造方法，其在斜向口袋掺杂后，在栅极侧壁上形成偏移间隙壁(Offset Spacer)，再进行延伸掺杂或以高斜角方式进行延伸掺杂。过程中，不须额外再进行热回火，可省略回火步骤，避免快速暂态扩散产生，并可顺利形成超晕圈(Super-halo)，更可获得超浅结(Ultra-shallow Junction)。
本发明的另一目的是提供一种集成电路的制造方法，其在延伸掺杂后，先进行固相外延(Solid Phase Epitaxy；SPE)步骤，再进行低温的热处理。或者，在延伸掺杂前，先进行口袋掺杂及回火，再进行延伸掺杂与后续的固相外延步骤，然后进行低温的热处理。因此，可降低掺质的扩散，提升元件的电特性。
本发明的另一目的是提供一种集成电路的制造方法，其先进行高能量且低剂量的倾斜源极/漏极掺杂，再进行高剂量的源极/漏极掺杂。因此，可形成倾斜源极/漏极，进而有效降低结电容。
根据以上所述的目的，本发明提供一种集成电路的制造方法，至少包括如下步骤：提供一基板，其中此基板上至少已形成一栅极结构，且此栅极结构至少包括依序堆迭的一介电层以及一导电层；对上述基板进行一口袋掺杂步骤；对上述基板进行—延伸掺杂步骤；以及在上述栅极结构的侧壁上形成一间隙壁，其中形成此间隙壁的步骤更至少包括进行一低温沉积步骤。
由于上述沉积间隙壁材料时的温度相当低，介于350℃至750℃之间，因此不需在延伸掺杂步骤后对基板进行回火，也不会在沉积间隙壁材料时引发掺质的快速暂态扩散。
根据以上所述的目的，本发明提供另一种集成电路的制造方法，至少包括如下步骤：提供一基板，其中此基板上至少已形成一栅极结构，且此栅极结构至少包括依序堆迭的一介电层以及一导电层；对上述基板进行斜角的口袋掺杂步骤；在上述栅极结构的侧壁上形成一偏移间隙壁，其中形成此偏移间隙壁的步骤至少包括进行一低温沉积步骤；以及对上述基板进行高斜角的延伸掺杂步骤。
由于口袋掺杂具有高斜角，同时于口袋掺杂后不须额外回火，而偏移间隙壁再加上具有高斜角的延伸掺杂，可兼顾通道长度，可形成超浅结，并顺利形成超晕圈。
根据以上所述的目的，本发明提供另一种集成电路的制造方法，至少包括如下步骤：提供一基板，其中此基板上至少已形成一栅极结构，且此栅极结构至少包括依序堆迭的一介电层以及一导电层；对上述基板进行一延伸掺杂步骤；对上述基板进行一固相外延步骤；以及进行一低温热处理步骤，其中此低温热处理步骤的温度低于800℃。此外，更可在延伸掺杂步骤前，先对基板进行口袋掺杂形成超晕圈，再进行回火，以活化超晕圈。
由于固相外延后掺质较不易扩散，且后续的热处理步骤的温度较低，因此对掺杂区域的范围具有较佳的控制能力。
根据以上所述的目的，本发明提供另一种集成电路的制造方法，至少包括如下步骤：提供一基板，其中此基板上至少已形成一栅极结构，且此栅极结构至少包括依序堆迭的一介电层以及一导电层；对上述基板进行高能量且低剂量的一倾斜源极/漏极掺杂步骤；以及对上述基板进行高剂量的一源极/漏极掺杂步骤。
由于具有高能量且低剂量的倾斜源极/漏极掺杂步骤在高剂量的源极/漏极掺杂步骤前进行，因此可顺利形成倾斜的源极/漏极，而达到降低结电容的目的。
附图说明
将参照附图详细说明本发明的优选实施例，其中：
图1至图3示出本发明的第一优选实施例的集成电路的制造方法剖面图；
图4与图5示出本发明的第二优选实施例的集成电路的制造方法剖面图；
图6与图7示出本发明的第三优选实施例的集成电路的制造方法剖面图；
图8至图10示出本发明的第四优选实施例的集成电路的制造方法剖面图；
图11至图13示出本发明的第五优选实施例的集成电路的制造方法剖面图；以及
图14与图15示出本发明的第六优选实施例的集成电路的制造方法剖面图。
其中，附图标记说明如下：
100 基板             102 介电层
104 导电层           106 离子
108 掺杂区           110 掺杂区
112 离子             114 掺杂区
116 掺杂区           122 间隙壁
200 基板             202 介电层
204 导电层           206 离子
208 掺杂区           210 掺杂区
212 掺杂区           214 间隙壁
216 离子             218 掺杂区
220 掺杂区           300 基板
302 介电层           304 导电层
306 离子             308 掺杂区
310 掺杂区           312 固相外延区
314 固相外延区       400 基板
402 介电层           404 导电层
406 离子             408 掺杂区
410 掺杂区           412 离子
414 掺杂区           415 非晶半导体层
416 掺杂区           417 非晶半导体层
418 固相外延区       420 固相外延区
500 基板             502 介电层
504 导电层           506 间隙壁
508 离子             510 掺杂区
512 掺杂区           514 离子
516 掺杂区           517 非晶半导体层
518 掺杂区           519 非晶半导体层
520 固相外延区       522 固相外延区
600 基板             602 介电层
604 导电层           606 间隙壁
608 离子             610 掺杂区
612 掺杂区           614 离子
具体实施方式
本发明公开一种集成电路的制造方法，可避免晶体管元件的短通道效应，降低结电容，进而可提升元件的性能。
请参照图1至图3，图1至图3示出本发明的第一优选实施例的集成电路的制造方法剖面图。首先提供半导体材料所构成的基板100，其中基板100上至少已形成有由依序堆迭的介电层102与导电层104所构成的栅极结构。而上述导电层104的材料可例如为多晶硅(Poly-Si)、多晶硅锗(Poly-SiGe)、金属、金属氧化物、金属氮化物、以及金属硅化物等。接着，以介电层102与导电层104所构成的栅极结构作为掩模，对基板100进行口袋掺杂步骤，以将离子106植入基板100中，而在栅极结构的两侧形成掺杂区108与掺杂区110，如图1所示的结构。
完成基板100的口袋掺杂步骤后，对基板100进行延伸掺杂步骤，以将离子112注入基板100中，而在部分栅极结构下方的基板100中形成掺杂区114与掺杂区116，如图2所示。其中，掺杂区114与掺杂区116一般又称为轻掺杂漏极(Lightly Doped Drain；LDD)。
然后，在极低温的环境下沉积间隙壁122的材料，覆盖在栅极结构与基板100上，其中沉积间隙壁122材料的反应温度优选控制在介于350℃至750℃之间，且沉积的反应时间优选介于5秒至600分钟之间，且间隙壁122可为单层或多层结构。接着，以例如回蚀刻的方式移除所沉积之间隙壁122材料的一部分，并暴露出部分的基板100与部分的导电层104，而在栅极结构的侧壁上形成间隙壁122，如同图3所示的结构。
由于沉积间隙壁122材料时，温度相当低，不会引发基板100中的掺质产生快速暂态扩散，因此不需在延伸掺杂步骤与间隙壁122材料沉积步骤之间，额外加入回火步骤。因此，可减少制造方法的热预算，降低制造方法的成本。
请参照图4与图5，图4与图5示出本发明的第二优选实施例的集成电路的制造方法剖面图。首先提供由半导体材料所构成的基板200，其中此基板200上至少已形成依序堆迭的介电层202以及导电层204，此介电层202与导电层204构成栅极结构。而导电层204的材料可为例如多晶硅、多晶硅锗、金属、金属氧化物、金属氮化物、以及金属硅化物等。接着，利用栅极结构作为掩模，并以高斜角的方式对基板200进行口袋掺杂，以将离子206斜向注入基板200中，而在栅极结构的两侧的基板200中形成掺杂区208与掺杂区210，且在栅极结构下方略低于掺杂区208与掺杂区210的基板200中形成掺杂浓度较高的掺杂区212，如图4所示。而位于掺杂区208与掺杂区210间的栅极结构正下方区域的掺杂浓度、掺杂区208、及掺杂区210的掺杂浓度均小于掺杂区212，因而构成超晕圈。
接着，请参照图5，先以例如沉积方式形成间隙壁214的材料，覆盖在基板200与栅极结构上，此间隙壁214可为单层或多层结构，再利用例如回蚀刻的方式移除部分之间隙壁214材料，并暴露出部分基板200与部分导电层204，而在栅极结构的侧壁上形成间隙壁214。其中，此间隙壁214也可称为偏移间隙壁，可将掺杂区218与掺杂区220的位置朝栅极结构的两侧偏移。在上述沉积间隙壁214的材料时，沉积的反应温度优选是控制在介于350℃至750℃之间，且沉积的反应时间优选则介于5秒至600分钟之间。然后，利用栅极结构作为掩模，再次以高斜角的方式对基板200进行延伸掺杂，以将离子216斜向注入基板200中，而在栅极结构边缘下的基板200中形成掺杂区218与掺杂区220。由于延伸掺杂同样以高斜角的方式进行，因此可提高掺杂区212的掺杂浓度。
值得注意的一点是，本发明也可在尚未进行基板200的口袋掺杂前，先于栅极结构的侧壁上形成另一偏移间隙壁，再以高斜角的方式对基板200进行口袋掺杂。或者，在基板200的口袋掺杂前，先形成偏移间隙壁，再依序对基板200进行口袋掺杂与延伸掺杂。也就是说，在进行高斜角的口袋掺杂与延伸掺杂时，栅极结构的侧壁上已先形成有偏移间隙壁。
由于高斜角的掺杂方式除了可在栅极结构下方较掺杂区208与掺杂区210低的区域形成掺杂浓度较浓的掺杂区212，同时过程中不须额外的回火步骤，而形成超晕圈，更可大幅缩减结的深度，而获得超浅结。
请参照图6与图7，图6与图7示出本发明的第三优选实施例的集成电路的制造方法剖面图。同样地，提供半导体材料所构成的基板300，其中此基板300上至少已形成依序堆迭的介电层302与导电层304。介电层302与导电层304构成栅极结构，且导电层304的材料可例如为多晶硅、多晶硅锗、金属、金属氧化物、金属氮化物、以及金属硅化物等。接着，以上述的栅极结构为掩模，对基板300进行延伸掺杂，以将离子306注入基板300中，而在栅极结构两侧的基板300中形成掺杂区308与掺杂区310，如图6所示。其中，半导体的基板300经离子注入后，掺杂区308与掺杂区310的晶体半导体转变成非晶(Amorphous)半导体。
然后，以热处理方式进行固相外延步骤，由于基板300中的掺杂区308与掺杂区310经离子注入后已转变成非晶半导体，因此掺杂区308与掺杂区310可为固相外延步骤所活化，而分别形成固相外延区312与固相外延区314，如同图7所示。其中，上述固相外延步骤的反应温度优选是控制在介于450℃至700℃之间，而固相外延步骤的反应时间优选则是控制在介于1分钟至10小时之间。
完成固相外延步骤后，进行后续的热处理，以完成互补式金属氧化物半导体晶体管元件等集成电路的源极与漏极(仅示出其中的固相外延区312与固相外延区314)的制作。其中，此热处理为低温热处理，且此热处理的反应温度优选是低于800℃。由于，固相外延区312与固相外延区314在低温时，其内的掺质不易产生扩散。因此，可提升对集成电路的源极与漏极区域的控制能力，而增加元件的可靠性。
请参照图8至图10示出本发明的第四优选实施例的集成电路的制造方法剖面图。本发明的第四优选实施例为第三优选实施例的修改，首先提供半导体材料所构成的基板400，其中此基板400上至少已形成依序堆迭的介电层402与导电层404。介电层402与导电层404构成栅极结构，且导电层404的材料可例如为多晶硅、多晶硅锗、金属、金属氧化物、金属氮化物、以及金属硅化物等。接着，可利用栅极结构作为掩模，先对基板400进行口袋掺杂步骤，以将离子406注入基板400中，而在栅极结构两侧的基板400中形成掺杂区408与掺杂区410，如图8所示。再进行热回火步骤，以活化掺杂区408与掺杂区410，并修补经离子注入后的基板400。其中，此热回火步骤的反应温度优选是控制在介于700℃至1050℃之间，且反应时间优选是控制在大于0秒且小于60秒之间。
然后，如同本发明的第三实施例，以上述的栅极结构为掩模，对基板400进行延伸掺杂，以将离子412注入基板400中，而在栅极结构两侧的基板400中形成掺杂区414与掺杂区416，如图9所示。其中，半导体的基板400经离子注入后，掺杂区408的表面与掺杂区414、及掺杂区410的表面与掺杂区416的晶体半导体分别转变成非晶半导体层415及非晶半导体层417。
然后，以热处理方式进行固相外延步骤，由于基板400中的掺杂区408的表面与掺杂区414、及掺杂区410的表面与掺杂区416经离子注入后已分别转变成非晶半导体层415及非晶半导体层417，因此非晶半导体层415及非晶半导体层417可为固相外延步骤所活化，而分别形成固相外延区418与固相外延区420，如同图10所示。其中，上述固相外延步骤的反应温度优选是控制在介于450℃至700℃间，而固相外延步骤的反应时间优选则是控制在介于1分钟至10小时间。
完成固相外延步骤后，进行后续的制造方法，以完成互补式金属氧化物半导体晶体管元件等集成电路的源极与漏极(仅示出其中的固相外延区418与固相外延区420)的制作。其中，此热处理为低温热处理，且此热处理的反应温度优选是低于800℃。由于，固相外延区418与固相外延区420在低温时，其内的掺质不易产生扩散，且基板400经口袋掺杂后，已运用回火步骤修补基板400。因此，不仅可有效地提升对集成电路的源极与漏极区域的控制能力，更可大幅改善元件的电特性。
请参照图11至图13，图11至图13示出本发明的第五优选实施例的集成电路的制造方法剖面图。此第五优选实施例运用上述第三优选实施例与第四优选实施例的技术特征所得的一实施例。首先，同样提供由半导体材料所构成的基板500。其中，此基板500上至少已形成依序堆迭的介电层502以及导电层504，此介电层502与导电层504构成栅极结构，且栅极结构的侧壁上已形成有可去除间隙壁(Spacer)506。而导电层504的材料可例如为多晶硅、多晶硅锗、金属、金属氧化物、金属氮化物、以及金属硅化物等。接着，利用上述的栅极结构及其侧壁上之间隙壁506作为掩模，对基板500进行口袋掺杂步骤，以将离子508注入基板500中，而在间隙壁506两侧的基板500中分别形成掺杂区510与掺杂区512，如同图11所示。完成基板500的口袋掺杂步骤后，进行热回火步骤，以修补基板500的材料结构缺陷，并活化掺杂区510与掺杂区512。其中，此热回火步骤的反应温度优选是控制在介于700℃至1050℃之间，且反应时间优选是控制在大于0秒且小于60秒之间。
然后，移除间隙壁506，再以栅极结构作为掩模，对基板500进行延伸掺杂步骤，以将离子514注入基板500中，而在栅极结构两侧的基板500中分别形成掺杂区516与掺杂区518，如同图12所示。其中，半导体的基板500经离子注入后，掺杂区510的表面与掺杂区516、及掺杂区512的表面与掺杂区518的晶体半导体分别转变成非晶半导体层517及非晶半导体层519。
完成基板500的延伸掺杂后，以热处理方式进行固相外延步骤，由于基板500中的掺杂区510的表面与掺杂区516、及掺杂区512的表面与掺杂区518经离子注入后已分别转变成非晶半导体层517及非晶半导体层519，因此非晶半导体层517及非晶半导体层519可为固相外延步骤所活化，而分别形成固相外延区520与固相外延区522，如同图13所示。其中，上述固相外延步骤的反应温度优选是控制在介于450℃至700℃之间，而固相外延步骤的反应时间优选则是控制在介于1分钟至10小时之间。
由于间隙壁506的形成与口袋掺杂步骤后的回火步骤皆在固相外延步骤前进行，因此可避免固相外延区520与固相外延区522内的掺质产生扩散。如此一来，有利于源极与漏极的范围的控制，而提升制造方法的可靠性。
请参照图14与图15，图14与图15示出本发明的第六优选实施例的集成电路的制造方法剖面图。首先，同样提供由半导体材料所构成的基板600，且此基板600上至少已形成依序堆迭的介电层602以及导电层604。其中，介电层602与导电层604构成栅极结构，且栅极结构的侧壁上已形成有间隙壁(Spacer)606。而导电层604的材料可例如为多晶硅、多晶硅锗、金属、金属氧化物、金属氮化物、以及金属硅化物等。接着，利用栅极结构与其侧壁上之间隙壁606作为掩模，对基板600进行高能量且低剂量的源极/漏极掺杂步骤，以将离子608注入基板600中，而在间隙壁606两侧的基板600中分别形成倾斜的掺杂区610与倾斜的掺杂区612，如同图14所示的结构。其中，上述的源极/漏极掺杂步骤的掺杂能量优选是控制在介于5keV与60keV之间，且源极/漏极掺杂步骤的掺杂剂量优选是控制在介于1e12cm-2与9e13cm-2之间。
然后，同样利用栅极结构与其侧壁上之间隙壁606作为掩模，对基板600进行高剂量的源极/漏极掺杂步骤，以将离子614注入基板600的掺杂区610与掺杂区612中，如同图15所示。其中，此高剂量的源极/漏极掺杂步骤的掺杂能量优选是控制在介于1keV与40keV之间，且此高剂量的源极/漏极掺杂步骤的掺杂剂量优选则是控制在介于1e15cm-2与8e15cm-2之间。
由于，先进行高能量且低剂量的源极/漏极掺杂步骤，再进行高剂量的源极/漏极掺杂步骤，可使低剂量的源极/漏极掺杂步骤的离子608注入基板600时如同注入晶体上，而具有通道效应。如此一来，可顺利地使掺杂区610与掺杂区612具有倾斜面。因此，可达到降低结电容的目的，进而提升元件性能。
如本领域的技术的人员所了解的，以上所述仅为本发明的优选实施例，并非用以限定本发明的权利要求；凡其它未脱离本发明所揭示的精神下所完成的等效改变或修饰，均应包含在下述的权利要求内。

Claims (3)

1.一种集成电路的制造方法，至少包括如下步骤：
提供一基板，其中该基板上至少已形成一栅极结构，且该栅极结构至少包括依序堆迭的一介电层以及一导电层；
对该基板进行一口袋掺杂步骤，以将多个第一离子斜向注入该基材中；
于该口袋掺杂步骤后，在该栅极结构的侧壁上形成一偏移间隙壁；以及
于形成该偏移间隙壁的步骤后，对该基板进行一延伸掺杂步骤。
2.如权利要求1所述的集成电路的制造方法，其中形成该偏移间隙壁的步骤还至少包括进行一沉积步骤，且该沉积步骤的反应温度介于350℃至750℃之间，而该沉积步骤的反应时间介于5秒至600分钟之间。
3.如权利要求1所述的集成电路的制造方法，其中该延伸掺杂步骤将多个第二离子斜向注入该基材中。
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