ATE455366T1 - Verfahren zur herstellung eines halbleitersubstrats mit einer schichtstruktur von aktivierten dotierungsstoffen - Google Patents

Verfahren zur herstellung eines halbleitersubstrats mit einer schichtstruktur von aktivierten dotierungsstoffen

Info

Publication number
ATE455366T1
ATE455366T1 AT03447259T AT03447259T ATE455366T1 AT E455366 T1 ATE455366 T1 AT E455366T1 AT 03447259 T AT03447259 T AT 03447259T AT 03447259 T AT03447259 T AT 03447259T AT E455366 T1 ATE455366 T1 AT E455366T1
Authority
AT
Austria
Prior art keywords
dopant
region
semiconductor substrate
thin layer
producing
Prior art date
Application number
AT03447259T
Other languages
English (en)
Inventor
Radu C Surdeanu
Original Assignee
Imec
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imec, Nxp Bv filed Critical Imec
Application granted granted Critical
Publication of ATE455366T1 publication Critical patent/ATE455366T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/916—Autodoping control or utilization

Landscapes

  • Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Optics & Photonics (AREA)
  • Electromagnetism (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT03447259T 2003-10-17 2003-10-17 Verfahren zur herstellung eines halbleitersubstrats mit einer schichtstruktur von aktivierten dotierungsstoffen ATE455366T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03447259A EP1524684B1 (de) 2003-10-17 2003-10-17 Verfahren zur Herstellung eines Halbleitersubstrats mit einer Schichtstruktur von aktivierten Dotierungsstoffen

Publications (1)

Publication Number Publication Date
ATE455366T1 true ATE455366T1 (de) 2010-01-15

Family

ID=34354656

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03447259T ATE455366T1 (de) 2003-10-17 2003-10-17 Verfahren zur herstellung eines halbleitersubstrats mit einer schichtstruktur von aktivierten dotierungsstoffen

Country Status (7)

Country Link
US (2) US7214592B2 (de)
EP (1) EP1524684B1 (de)
JP (1) JP4750400B2 (de)
CN (1) CN100442444C (de)
AT (1) ATE455366T1 (de)
DE (1) DE60330965D1 (de)
TW (1) TWI256079B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060113591A1 (en) * 2004-11-30 2006-06-01 Chih-Hao Wan High performance CMOS devices and methods for making same
JP2006245338A (ja) * 2005-03-03 2006-09-14 Nec Electronics Corp 電界効果型トランジスタの製造方法
US7786003B1 (en) * 2005-05-25 2010-08-31 Advanced Micro Devices, Inc. Buried silicide local interconnect with sidewall spacers and method for making the same
US20070037326A1 (en) * 2005-08-09 2007-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Shallow source/drain regions for CMOS transistors
US20070212861A1 (en) * 2006-03-07 2007-09-13 International Business Machines Corporation Laser surface annealing of antimony doped amorphized semiconductor region
US7569463B2 (en) 2006-03-08 2009-08-04 Applied Materials, Inc. Method of thermal processing structures formed on a substrate
JP5558006B2 (ja) * 2006-03-08 2014-07-23 アプライド マテリアルズ インコーポレイテッド 基板に形成された熱処理構造用の方法および装置
JP2008041988A (ja) * 2006-08-08 2008-02-21 Hiroshima Univ ゲルマニウム（Ｇｅ）半導体デバイス製造方法。
KR100806791B1 (ko) * 2006-09-01 2008-02-27 동부일렉트로닉스 주식회사 두 단계 포켓 임플란트를 이용한 반도체 소자의 제조 방법
US7718513B2 (en) * 2007-04-13 2010-05-18 International Business Machines Corporation Forming silicided gate and contacts from polysilicon germanium and structure formed
US8198547B2 (en) 2009-07-23 2012-06-12 Lexmark International, Inc. Z-directed pass-through components for printed circuit boards
US8012843B2 (en) * 2009-08-07 2011-09-06 Varian Semiconductor Equipment Associates, Inc. Optimized halo or pocket cold implants
US9009954B2 (en) 2011-08-31 2015-04-21 Lexmark International, Inc. Process for manufacturing a Z-directed component for a printed circuit board using a sacrificial constraining material
US8943684B2 (en) 2011-08-31 2015-02-03 Lexmark International, Inc. Continuous extrusion process for manufacturing a Z-directed component for a printed circuit board
US9078374B2 (en) * 2011-08-31 2015-07-07 Lexmark International, Inc. Screening process for manufacturing a Z-directed component for a printed circuit board
CN107068753B (zh) * 2011-12-19 2020-09-04 英特尔公司 通过部分熔化升高的源极-漏极的晶体管的脉冲激光退火工艺

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159723A (ja) * 1984-08-30 1986-03-27 Fujitsu Ltd 半導体装置の製造方法
US4659392A (en) * 1985-03-21 1987-04-21 Hughes Aircraft Company Selective area double epitaxial process for fabricating silicon-on-insulator structures for use with MOS devices and integrated circuits
JPH03131020A (ja) * 1989-10-16 1991-06-04 Sanyo Electric Co Ltd 半導体装置の製造方法
JPH0492477A (ja) * 1990-08-08 1992-03-25 Hitachi Ltd 可変容量ダイオードの製造方法
US5171700A (en) * 1991-04-01 1992-12-15 Sgs-Thomson Microelectronics, Inc. Field effect transistor structure and method
JPH07321313A (ja) * 1994-05-24 1995-12-08 Sanyo Electric Co Ltd 半導体デバイスの製造方法
KR0146525B1 (ko) * 1995-05-09 1998-11-02 김주용 반도체 소자의 트랜지스터 제조방법
KR100232206B1 (ko) * 1996-12-26 1999-12-01 김영환 반도체 소자의 제조방법
KR100260044B1 (ko) * 1997-11-25 2000-07-01 윤종용 고속/고성능 모스 트랜지스터 및 그 제조방법
US6521502B1 (en) * 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
US6891235B1 (en) * 2000-11-15 2005-05-10 International Business Machines Corporation FET with T-shaped gate
DE10058031B4 (de) * 2000-11-23 2007-11-22 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Bildung leicht dotierter Halogebiete und Erweiterungsgebiete in einem Halbleiterbauelement
US20020086502A1 (en) * 2000-12-29 2002-07-04 Liu Mark Y. Method of forming a doped region in a semiconductor material
JP3904936B2 (ja) * 2001-03-02 2007-04-11 富士通株式会社 半導体装置の製造方法
JP2003086798A (ja) * 2001-09-13 2003-03-20 Nec Corp 半導体装置およびその製造方法
US20030096490A1 (en) * 2001-11-16 2003-05-22 John Borland Method of forming ultra shallow junctions
US6555439B1 (en) * 2001-12-18 2003-04-29 Advanced Micro Devices, Inc. Partial recrystallization of source/drain region before laser thermal annealing
US6682980B2 (en) * 2002-05-06 2004-01-27 Texas Instruments Incorporated Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant
US6680250B1 (en) * 2002-05-16 2004-01-20 Advanced Micro Devices, Inc. Formation of deep amorphous region to separate junction from end-of-range defects
US6689671B1 (en) * 2002-05-22 2004-02-10 Advanced Micro Devices, Inc. Low temperature solid-phase epitaxy fabrication process for MOS devices built on strained semiconductor substrate
JP2003347422A (ja) * 2002-05-28 2003-12-05 Fujitsu Ltd 半導体装置の製造方法
US7307273B2 (en) * 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US6699771B1 (en) * 2002-08-06 2004-03-02 Texas Instruments Incorporated Process for optimizing junctions formed by solid phase epitaxy
DE10260613B8 (de) * 2002-12-23 2010-03-04 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Herstellen eines Feldeffekttransistors
JP4207591B2 (ja) * 2003-02-10 2009-01-14 日本電気株式会社 浅い拡散層を有する半導体装置の製造方法
US6989302B2 (en) * 2003-05-05 2006-01-24 Texas Instruments Incorporated Method for fabricating a p-type shallow junction using diatomic arsenic
JP2004363355A (ja) * 2003-06-05 2004-12-24 Hitachi Ltd 半導体装置及びその製造方法
US6908822B2 (en) * 2003-09-15 2005-06-21 Freescale Semiconductor, Inc. Semiconductor device having an insulating layer and method for forming
US7112499B2 (en) * 2004-01-16 2006-09-26 Chartered Semiconductor Manufacturing Ltd. Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal
US7169675B2 (en) * 2004-07-07 2007-01-30 Chartered Semiconductor Manufacturing, Ltd Material architecture for the fabrication of low temperature transistor
US7091097B1 (en) * 2004-09-03 2006-08-15 Advanced Micro Devices, Inc. End-of-range defect minimization in semiconductor device

Also Published As

Publication number Publication date
CN1645568A (zh) 2005-07-27
TWI256079B (en) 2006-06-01
CN100442444C (zh) 2008-12-10
DE60330965D1 (de) 2010-03-04
US7214592B2 (en) 2007-05-08
US20050112831A1 (en) 2005-05-26
TW200515489A (en) 2005-05-01
US20070267660A1 (en) 2007-11-22
JP2005129930A (ja) 2005-05-19
EP1524684A1 (de) 2005-04-20
EP1524684B1 (de) 2010-01-13
JP4750400B2 (ja) 2011-08-17

Similar Documents

Publication Publication Date Title
ATE455366T1 (de) Verfahren zur herstellung eines halbleitersubstrats mit einer schichtstruktur von aktivierten dotierungsstoffen
JP4696127B2 (ja) 半導体基板上にエピタキシャル層を形成する方法およびこの方法によって形成するデバイス
CN102097298B (zh) 薄soi器件的制造方法
ATE453211T1 (de) Verfahren zur herstellung eines photovoltaischen elements mit stabilem wirkungsgrad
TW200618120A (en) A microelectronic device and method of fabricating the same
ATE404991T1 (de) Verfahren zur dotierung mit hilfe von diffusion, oberflächenoxidation und rückätzung sowie verfahren zur herstellung von solarzellen
WO2006086644A3 (en) Back-illuminated imaging device and method of fabricating same
JP2006506821A5 (de)
CN1818155A (zh) 低缺陷密度的改变取向的Si及其产品
DE58909669D1 (de) Verfahren zur Herstellung einer Siliziummenbran mit kontrollierter Spannung
TW200603294A (en) Method of making transistor with strained source/drain
US20140284769A1 (en) Method of forming a strained silicon layer
WO2007038164A3 (en) Methods for nanostructure doping
JP2005026681A (ja) シリコンの酸化による欠陥低減
WO2002059945A3 (en) Oxidized film structure and method of making epitaxial metal oxide structure
US20170012113A1 (en) Method for preparing substrate using germanium condensation process and method for manufacturing semiconductor device using same
ATE438196T1 (de) Verfahren zur herstellung einer relaxierten sige- schicht
ATE535020T1 (de) Verfahren zur herstellung einer halbleiteranordnung mit übergang
WO2004081987A3 (en) Sige rectification process
WO2009013531A3 (en) A method of manufacturing a semiconductor device, and a semiconductor device
JP2003158250A (ja) ＳｉＧｅ／ＳＯＩのＣＭＯＳおよびその製造方法
ATE538494T1 (de) Verfahren zur herstellung eines ssoi-substrats
US6793731B2 (en) Method for recrystallizing an amorphized silicon germanium film overlying silicon
EP2019155A3 (de) Galliumnitridsubstrat und Verfahren zur Ablagerung eines Galliumnitridfilms
CN106531682A (zh) GeOI结构以及制备方法

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties