CN105429618B - 上电体偏置电路和方法 - Google Patents

上电体偏置电路和方法 Download PDF

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CN105429618B
CN105429618B CN201510446073.8A CN201510446073A CN105429618B CN 105429618 B CN105429618 B CN 105429618B CN 201510446073 A CN201510446073 A CN 201510446073A CN 105429618 B CN105429618 B CN 105429618B
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E·J·博林
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Triple Fujitsu Semiconductor Co Ltd
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Abstract

一种上电体偏置电路和方法，其中该装置可包括：至少第一体偏置电路，被配置为生成第一体偏置电压，该第一体偏置电压不同于集成电路装置的电源电压；至少第一偏置控制电路，被配置为将第一体偏置节点设置为第一电源电压，并且随后使得所述第一体偏置节点被设置为所述第一体偏置电压；以及多个第一晶体管，具有连接至所述第一体偏置节点的本体。采用本公开的装置和方法，可以比传统方法更有效地生成体偏置电压。

Description

上电体偏置电路和方法
技术领域
本发明大致涉及用于集成电路装置的晶体管体偏置电路，特别涉及用于在这类装置上电后建立体偏置电压的体偏置电路。
背景技术
集成电路(IC)装置可包括多个晶体管，例如绝缘栅场效应晶体管(下文称为MOS型晶体管，但并不暗示任何特定的栅极或栅极绝缘材料)。MOS型晶体管可包括栅极、漏极、源极和本体。在某些IC装置或具有IC装置的某些电路中，晶体管的本体固定连接至电源电压。例如，p沟道MOS晶体管的本体连接至高电源电压(例如，VDD)，而n沟道晶体管的本体连接至低电源电压(例如，VSS)
然而，在其他IC装置或具有IC装置的电路中，晶体管的本体可被偏置为不同于电源电压的电势。这样的体偏置可有利地改变晶体管的性能。例如，较大的反向体偏置(即，偏置到高于VDD的电压的p沟道体偏置或者偏置到低于VSS的电压的n沟道体偏置)可降低晶体管电流泄漏。较大的正向体偏置(即，偏置到低于VDD的电压的p沟道体偏置或者偏置到高于VSS的电压的n沟道体偏置)可提高晶体管切换速度。在某些情况下，IC装置可包括生成所需体偏置电压的一个或多个体偏置电压生成电路，生成的体偏置电压随后被施加到目标晶体管的本体。
实施体偏置电路的缺点是，在对IC装置进行加电的瞬态期间需要对体电压进行严格控制。如果未严格控制体电压电平，则由晶体管本体形成的p-n结会正向偏置，这会牵引大量的电流，从而可能损坏IC装置。而且，晶体管本体的初始浮置状态可导致闩锁情况(寄生双极结型晶体管的激活)。
发明内容
针对现有技术中存在的问题，本申请提供一种集成电路装置及方法。
根据本申请的一个方案，一种集成电路装置，包括：
至少一第一体偏置电路，被配置为生成第一体偏置电压，所述第一体偏置电压不同于所述IC装置的电源电压；
至少一第一偏置控制电路，被配置为将第一体偏置节点设置为第一电源电压，并且随后使得所述第一体偏置节点被设置为所述第一体偏置电压；以及
多个第一晶体管，具有连接至所述第一体偏置节点的本体。
根据本申请的第二方案，提供了一种方法，包括：
将第一电源电压施加至集成电路装置；
一开始将至少第一体偏置节点钳制在所述第一电源电压；
以所述第一电源电压生成至少第一体偏置电压；以及
随后使所述第一体偏置节点由所述第一体偏置电压驱动；其中
所述第一体偏置节点将所述第一体偏置电压提供给多个第一晶体管的本体。
根据本申请的第三方案，提供了一种集成电路装置，包括：
第一电源连接部，被配置为接收第一电源电压；
第二电源连接部，被配置为接收大于所述第一电源电压的第二电源电压；
至少以第一体偏置生成电路，被耦接以在生成器电源节点处接收电力，并且被配置为生成第一体偏置电压；
开关电路，被配置为将所述第一电源连接部或所述第二电源连接部耦接至所述生成器电源节点；以及
多个第一晶体管，具有被耦接以接收所述第一体偏置电压的本体。
采用本申请的装置和方法，避免了可能正偏p-n结和/或导致闩锁的情况，并且与传统方法相比更有效地生成体偏置电压。
附图说明
图1是根据一实施例的体偏置电路的示意框图。
图2A是根据另一实施例的体偏置电路的示意框图。
图2B是示出与图2A中电路类似的电路的上电操作的时序图。
图3A是根据另一实施例的体偏置电路的示意框图。
图3B是示出与图3A中电路类似的电路的上电操作的时序图。
图4A是可以包括在实施例中的钳位装置的示意图。
图4B是可以包括在图4A的装置中的钳位晶体管的侧剖面图。
图5A是可以包括在实施例中的另一钳位装置的示意图。
图5B是可以包括在图5A的装置中的钳位晶体管的侧剖面图。
图6A是可以包括在实施例中的另一钳位装置的示意图。
图6B是可以包括在图6A的装置中的钳位晶体管的侧剖面图。
图7A是可以包括在实施例中的另一钳位装置的示意图。
图7B是可以包括在图7A的装置中的钳位晶体管的侧剖面图。
图8是示出常规集成电路(IC)装置的上电操作的模拟结果的图。
图9是示出根据一实施例的IC装置的上电操作的模拟结果的图。
图10是根据一实施例的钳位电路的示意图。
图11A到图11C是可以包括在实施例中的深度耗尽沟道(DDC)晶体管的侧剖面图。
图12A是根据一实施例的具有体偏置的电路的图示。
图12B是示出与图12A中所表示的IC装置类似的IC装置的上电操作的时序图。
图13A是常规体偏置布置的示意框图。
图13B是示出与图13A中装置类似的装置的上电操作的时序图。
具体实施方式
下面将结合多个附图对本发明各实施例进行描述。实施例示出了能够减少电流尖峰和/或闩锁效应的用于在上电操作期间控制体偏置电压的电路、集成电路(IC)装置和方法。上电操作可包括当电源电压开始升高时(包括当装置开始上电、复位、遭遇电力中断事件或出于节约用电目的而动态上电和掉电时，当然这些只不过是例举几个例子而已)的那些操作。
在以下实施例中，类似项目由相同的附图标记指代，最开始的数字对应于图号。
图12A是IC装置中的体偏置互补MOS晶体管的图形表示。IC装置1200可包括具有连接至高电源电压(VDD)的源极的p沟道晶体管P120以及接收p沟道体偏置电压(VBP)的本体。类似地，n沟道晶体管N120可具有连接至低电源电压(VSS)的源极以及接收n沟道体偏置电压(VBN)的本体。图12A还示出了晶体管栅电压Vgate(该电压示出为施加在比如晶体管P120和N120上)。
图12B是示出用于类似于图12A中所表示的IC装置的上电操作的时序图。图12B示出了VDD、VBP、VBN和上图12A中提到的Vgate。在上电操作期间，VDD从VSS(在本示例中为0V)增加至期望电平(VDD_opt)。然而，在此期间，体偏置电路并未激活。因此，晶体管的体电压(VBP和VBN)可浮动。相应地，由于电阻和/或电容耦合，该体偏置电压可能变化。如果VBN上升到超过VSS足够数量或者VBP低于VDD足够数量，则由晶体管本体形成的p-n结会正偏，从而牵引大量电流。这样的浮动本体也会造成闩锁情况。
仍然参见图12B，一旦VDD达到稳定电平，体偏置电路就会被激活。这如时刻ta所示，在该时间处VBP被驱动至VBP_opt，VBN被驱动至VBN_opt。
图13A和13B示出在上电操作期间处理体(即，阱)偏置的一种常规方式。在图13A和13B的常规方式中，假设IC装置具有高于VDD的输入/输出电源电压(VDDIO)。而且，VDDIO先于VDD首先被上电。图13A示出了具有由VDDIO供电的体偏置电路的一种常规体偏置布置。特别地，p沟道体偏置生成电路1301可由VDDIO生成VBP，n沟道体偏置生成电路1303可由VDDIO生成VBN。
如图13B所示，体偏置电路1301/1302能够在VDD升高之前建立体偏置电压VBP/VBN。这能大幅度减少上电时的电流消耗(current draw)，并且能防止和/或大幅度降低出现闩锁的可能性。
值得注意的是，该体偏置方法的效率局限于：
其中，Vout是VBP或VBN。例如，假设VBN＝-0.6V且VDDIO＝2.5V，则效率将不大于24％。
图1是根据第一实施例的体偏置电路100的示意框图。假设体偏置电路100被包括在集成电路装置中，该集成电路装置具有第一高电源电压(VDD)和第二高电源电压(VDDIO)。在某些实施例中，第二电源电压可高于第一高电源电压(即，VDDIO>VDD)。在某些实施例中，VDDIO可大于1.5V，比如可以是1.8V，或大于2.0V，可为2.5V左右，甚至更高，比如约为3.3V。在某些实施例中，VDD可小于2.5V，或小于2.0V，甚至小于1.5V。在一个非常具体的实施例中，VDDIO可以是大约2.5V，VDD可以是大约1.2V。在上电操作期间，VDDIO电压首先上升。体偏置电压最初可基于VDDIO电压而生成。一旦体偏置电压达到所需的电平，则另一个电源电压VDD就可以上升。在具体实施例中，VDDIO可以是向IC装置的输入/输出驱动器提供电力的输入/输出电源电压。
在所示的实施例中，体偏置电路100可在第一电源输入108-0接收第一电源电压(VDD)，在第二电源输入108-1接收第二电源电压(VDDIO)，并且可在体偏置节点110生成体偏置电压(VBx)。体偏置电路100可包括体偏置生成电路102、开关电路104和调压器106。调压器106可接收VDDIO，并对其进行调节使之达到预定电平VDD_Reg(可以是VDD的预期最终电平)。
开关电路104可包括第一开关输入112-0、第二开关输入112-1和开关输出112-2。第一开关输入112-0可接收基于VDDIO生成的电压VDD_Reg。第二开关输入112-1可接收电压VDD。开关电路104可由上电电路(未示出)生成的控制信号CTRL来控制。上电时，CTRL具有第一值，该第一值导致第一开关输入112-0连接至开关输出112-2并且第二开关输入112-1与开关输出112-2隔离开。然后CTRL变为第二值，该第二值导致第一开关输入112-0与开关输出112-2隔离开并且第二开关输入112-1连接至开关输出112-2。在一些实施例中，控制信号CTRL可基于VDD上电复位(POR)型电路等。
体偏置生成电路102可从开关输出112-2接收电源电压VDDIn。响应于VDDIn，体偏置生成电路102可生成体偏置电压VBx。应当理解，VBx可以是n沟道体偏置电压或p沟道体偏置电压。
仍然参见图1，在操作中，假设VDDIO先于VDD上升。进一步而言，当VDD达到稳定电平后，信号CTRL从第一值切换为第二值。相应地，在上电操作中，VDDIO首先上升，导致调压器106将VDD_Reg提供给开关电路104。CTRL具有第一值，故VDD_Reg被作为VDDIn提供给体偏置生成电路102。体偏置生成电路102生成体偏置电压VBx，从而为晶体管建立所需的体偏置。随后，当晶体管体偏置建立后，VDD就可上升，避免了可能正偏p-n结和/或导致闩锁的情况，这是由于体偏置生成电路102驱动这些本体达到所需电压之故。一旦VDD达到所需电平和/或稳定后，信号CTRL可切换到第二值，将VDD作为VDDIn施加到体偏置生成电路102。由于VDD<VDDIO，能更加有效地生成体偏置电压。
应当理解的是，IC装置可包括多个如图1所示的体偏置电路，以生成各种体偏置电压，包括正体偏置电压和负体偏置电压。进一步地，生成的体偏置电压可以是反向体偏置(即，大于p沟道装置的VDD，或小于n沟道装置的VSS)，或者是正向体偏置(即，小于p沟道装置的VDD，或大于n沟道装置的VSS，除正偏p-n结本体的电压之外)。在特别具体的实施例中，p沟道装置的反向体偏置电压(VBP)的范围在大于VDD约0.1V到大于VDD约1V之间。类似地，n沟道晶体管的反向体偏置电压(VBN)的范围可以在小于VSS约0.1V到小于VSS约1V之间。正向VBP的极限取决于掺杂情况，在具体实施例中可以不超过比VDD小0.6V。同样地，正向VBN的极限取决于掺杂情况，但在具体实施例中可以不超过比VSS大0.6V。
虽然实施例可包括将电源电压切换至体偏置生成电路的布置，然而其他实施例也可以上电后将晶体管本体维持(例如，钳位)在“安全”电压。随后，一旦建立体偏置电压后，晶体管本体可从钳位电压切换到所需的体偏置电压。现在将对这样实施例的实例进行描述。
图2A是根据另一实施例的体偏置电路200的示意框图。和在图1中一样，在图2A中，假设体偏置电路200被包括在IC装置中，该IC装置具有先于第一电源电压VDD上升的较高的第二电源电压(VDDIO)。VDD和VDDIO的特定值及其之间的关系可包括以上描述的那些以及等效值(关系)。
在所示的实施例中，体偏置电路200可利用首先上升的电源电压(例如VDDIO)使得钳位电路将体偏置节点钳制在其他电源电压(例如VDD、VSS)。这样，当装置上电时，晶体管本体被钳制在这样的电源电压(例如VDD、VSS)。一旦较低的电源电压(VDD)稳定后，体偏置生成电路就能生成体偏置电压。然后体偏置节点可从电源电压“松开(unclamp)”并连接至体偏置电压。
在所示的具体实施例中，体偏置电路200可包括p沟道晶体管体偏置(PBB)生成电路202-0、n沟道晶体管体管体偏置(NBB)生成电路202-1、第一钳位电路204-0、第二钳位电路204-1和钳位控制电路214。PBB生成电路202-0可以生成用于p沟道晶体管的体偏置电压VBP_Gen。类似地，NBB生成电路202-1可以生成用于n沟道晶体管的体偏置电压VBN_Gen。PBB和NBB生成电路(202-0/1)这二者都可由第一电源电压(VDD)供电，第一电源电压可理解为在第二电源电压(VDDIO)后上升。因此，在上电操作的初始部分，在VDD上升之前，PBB和NBB生成电路(202-0/1)并未激活，故不生成其各自的体偏置电压VBP_Gen和VBN_Gen。
电源电压VDD可作为第一输入从高电源输入208-0提供到第一钳位电路204-0。第一钳位电路204-0可从PBB生成电路202-0接收VBP_Gen作为第二输入。第一钳位电路204-0的输出210-0可以在p沟道体偏置节点210-0为一些p沟道体晶体管设置体偏置电压VBP。第一钳位电路204-0可由钳位使能信号(Clamp_EnableP)和钳位禁用信号(Clamp_DisableP)来控制。钳位使能信号(Clamp_EnableP)可从VDDIO激活(或可以对应于VDDIO)。因此，VDDIO的初始上升能激活Clamp_EnableP。当Clamp_EnableP激活时，钳位电路204-0可将p沟道体偏置节点210-0钳制为VDD。相反，钳位禁用信号(Clamp_DisableP)可由钳位控制电路214激活。当激活时，信号Clamp_DisableP将覆盖信号Clamp_EnableP，导致p沟道体偏置节点210-0被连接至VBP_Gen。
以类似于第一钳位电路204-0的方式，第二钳位电路204-1可从低压电源输入208-2接收VSS，从NBB生成电路202-1接收VBN_Gen，并且可在n沟道体偏置节点210-1设置针对一些n沟道晶体管的体偏置电压VBN。第二钳位电路204-1可以与第一钳位电路204-0相同的方式来运行。通过基于VDDIO的钳位使能信号(Clamp_EnableN)的操作，可以将n沟道体偏置节点210-1钳制为VSS。响应于由钳位控制电路214提供的钳位禁用信号(Clamp_DisableN)可以禁用这样的钳位，这会导致n沟道体偏置节点210-1被连接以接收VBN_Gen。
钳位控制电路214可根据VDD来运行。换言之，一旦VDD达到所需电平，或在一段时间之后，钳位控制电路会激活钳位禁用信号(Clamp_DisableP和Clamp_DisableN)。
结合图2B将对图2A的体偏置电路的一特定上电操作进行描述。图2B是示出上述VDDIO、VDD、VBP、VBN和VSS的时序图。
参见图2A和图2B，在时刻t0，VDDIO可上升。由于电阻/电容耦合，VBN/VBP可能会有一些变化。
大约在时刻t1，VDDIO达到使能钳位电路204-0/1的电平。结果是，VBP被钳制到VDD，VBN被钳制到VSS(在所示实施例中为零)。
大约在时刻t2，VDD可上升。由于钳位电路204-0/1被使能，VBP可保持钳制到VDD。因此，VBP随着VDD上升，防止p沟道本体p-n结的任何正偏和/或防止可能的闩锁情况。类似地，VBN保持钳制到VSS，也能防止n沟道本体结的正偏和/或减少闩锁情况。一旦VDD达到足够的电平，则体偏置电路(例如，202-0/1)可被激活，从而生成VBP和VBN电压。
大约在时刻t3，VDD达到预定电平长达预定时间量。结果是，钳位控制电路214可激活钳位禁用信号，导致钳位电路204-0/1使VBP连接至VBP_Gen，或被动地使能VBP至VBP_Gen的连接，并且使VBN连接至VBN_Gen，或被动地使能VBN连接至VBN_Gen的连接。现在IC可通过具有所需体偏置电压的晶体管运行。
虽然图2B显示的是以反向体偏置电压(相对于VDD_opt和VSS电平)运行的晶体管，然而应当理解的是，针对给定应用，体偏置电压可以具有任意合适的值。进一步地，一旦建立体偏置电压后，体偏置电压可以以动态的方式变化。体偏置电压(VBP、VBN)可具有本文具体实施例所描述的关系和/或范围以及等效关系和/或范围。
如本文实施例所示，以VDD而不是VDDIO生成体偏置电压(例如，VBP和VBN)，比传统方法的效率更高。在与图13A和图13B有关的如上所述中，以2.5V的VDDIO生成-0.6V的VBN具有的最高效率为24％。然而，如果VDD是0.9V，则生成相同VBN可以以最高效率67％来完成，在效率上具有明显提高。
图3A是根据另一实施例的体偏置电路300的示意框图。在所示的实施例中，体偏置电路300可包括钳位电路，该钳位电路在无施加电力的情况下运行，或者无需稳定的电力供应就能运行。通过使用这样的“零偏置”钳位电路，加电后，晶体管本体可被钳制为电源电压(例如，VDD、VSS)。一旦电源电压稳定后，体偏置生成电路就能生成体偏置电压。然后体偏置节点可从电源电压“松开”并连接至体偏置电压。
体偏置电路300可包括和图2A中类似的部件，包括PBB生成电路302-0、NBB生成电路302-1、第一钳位电路304-0、第二钳位电路304-1以及钳位控制电路314。PBB和NBB生成电路(302-0/1)可以像图2A中那样运行，一旦第一电源电压VDD稳定后，可以生成用于p沟道晶体管的体偏置电压VBP_Gen以及用于n沟道晶体管的体偏置电压VBN_Gen。类似地，一旦VDD达到所需电平，或在一段时间之后，钳位控制电路314可激活钳位禁用信号(Clamp_DisableP、Clamp_DisableN)。
然而，与图2A的实施例不同的是，钳位电路304-0/1没有以响应于第二电源电压VDDIO而运行。更确切地说，如上所述，在没有VDD或稳定的VDD电平时，第一钳位电路304-0可将p沟道体偏置节点310-0钳制为VDD，而第二钳位电路304-1可将n沟道体偏置节点310-1钳制为VSS。响应于钳位禁用信号Clamp_DisableP，第一钳位电路304-0可使p沟道体偏置节点310-0连接至由PBB生成电路302-0生成的体偏置电压VBP_Gen。类似地，响应于钳位禁用信号Clamp_DisableN，第二钳位电路304-1可使n沟道体偏置节点310-1连接至由NBB生成电路302-1生成的体偏置电压VBN_Gen。
在非常具体的实施例中，钳位电路304-0/1可利用耗尽型MOS晶体管。因此，在没有栅电压的情况下，这样的晶体管可提供钳位连接(即，源-漏路径将VBN连接至VSS和/或将VBP连接至VDD)。随后，栅电压可关闭这样的耗尽型晶体管，使VBN连接至VBN_Gen并使VBP连接至VBP_Gen。
结合图3B将对图3A的体偏置电路的一特定上电操作进行描述。图3B是示出上述VDD、VBP、VBN和VSS的时序图。
参见图3A和图3B在时刻t0，VDD可能开始上升。在常规装置中，由于电容/电阻耦合，这样的操作可导致体偏置电平(VBP和VBN)变化。然而，通过第一和第二钳位电路(304-0/1)的“零偏置”操作，VBP(p沟道晶体管的体偏置)保持钳制为VDD，而VBN(n沟道晶体管的体偏置)保持钳制为VSS。因此，可以防止基于本体的p-n结正偏和/或闩锁引起的情况。
大约在时刻t1，VDD达到所需电平长达预定时间量。结果是，钳位控制电路314可激活钳位禁用信号，导致钳位电路304-0/1将VBP连接至VBP_Gen并将VBN连接至VBN_Gen。现在IC可通过具有所需体偏置电压的晶体管运行。
在本公开其他实施例中，体偏置电压(VBN_Gen、VBP_Gen)可以是反向体偏置电压、正向体偏置电压以及动态切换的体偏置电压。在具体实施例中，电源电压(VDD)和体偏置电压(VBP、VBN)可具有本文具体实施例所描述的关系和/或范围以及等效关系和/或范围。
图4A是根据一实施例的钳位装置416的示意图。钳位装置416可包括耗尽型n沟道MOS型晶体管N40、电容C40和电流源电路418。晶体管N40可具有连接至第一电源(VDD)输入408-0的源极、连接至p沟道体偏置节点410-0的漏极以及连接至电流源电路418的栅极。晶体管N40的本体可连接至其源极VDD(或可选地连接至低电源电压VSS)。电容C40可连接在晶体管N40的源极和栅极之间。
电流源电路418可连接在晶体管N40的栅极和低电源连接部408-2之间。电流源电路418可以响应于VDD电平而运行。换言之，一开始，当VDD上升时，电流源电路418可能并不牵引电流。然而，一旦VDD达到预定电平或者稳定了长达预定时间后，电流源电路418就可牵引电流。
在运行中，在上电后VDD可开始上升至所需电平。此时，可禁用电流源电路418。通过电容C40的操作，N40的栅极处的电压可追随其源极(即，追随VDD)。由于N40是耗尽型装置，其在这种状态下导通，并且p沟道体偏置节点410-0(即VBP)可被钳位至VDD。
随后，一旦VDD达到合适的电平或者稳定了合适的时间量，就可使能电流源电路418。结果是，N40的栅极可被朝向VSS牵引，N40关闭。这样，p沟道体偏置节点410-0可从钳制为VDD的状态释放出来，并被驱动至体偏置电压，例如由体偏置生成电路生成的体偏置电压(例如，VBP_Gen)。
图4B是钳位晶体管420(例如，在图4A中示出为N40的晶体管)的侧剖面图示意。钳位晶体管420可形成在p型阱(p阱)422内，p阱422形成在深n型阱(n阱)424内，而n阱424形成在p型衬底426内。第一电源(VDD)输入408-0可连接至深n阱接头(tap)428-0、p阱接头428-1以及钳位晶体管420的源极430。电容C40可连接在源极430和栅极432之间。漏极434可连接至p沟道体偏置节点410-0。在一些实施例中，沟道区436可掺杂有n型掺杂剂以在耗尽模式中提供期望的响应。
在具体实施例中，电源电压(VDD)和体偏置电压(VBP)可具有本文具体实施例中描述的关系和/或范围以及等效关系和/或范围。
图5A是根据另一实施例的钳位装置516的示意图。钳位装置516可包括耗尽型p沟道MOS型晶体管P50、电容C50和电流源电路518。晶体管P50可具有连接至低压电源(VSS)输入508-2的源极、连接至n沟道体偏置节点510-1的漏极、连接至电流源电路518的栅极以及连接至其源极VSS(或者可选地连接至VDD)的本体。
电容C50可连接在晶体管P50的源极和栅极之间。电流源电路518可连接在晶体管P50的栅极和高电源(VDD)连接部508-0之间。电流源电路518可以以和图4A中所示电流源电路418相同的方式运行。
钳位装置516可以以和图4A中所示的相同的方式运行。简言之，当VDD上升时，VBN可由耗尽型晶体管P50钳制为VSS。一旦VDD达到一定电平或者稳定了预定时间量后，就可使能电流源电路518，将P50的栅极驱动至VDD，从而关闭晶体管P50。
图5B是钳位晶体管520(例如图5A中示出为P50的晶体管)的侧剖面图示意。钳位晶体管520可形成在n阱524内，n阱524形成在p型衬底526内。低电源(VSS)输入508-2可连接至n阱接头528-0以及钳位晶体管520的源极530。电容C50可连接在P50的源极530和栅极532之间。漏极534可连接至n沟道体偏置节点510-1。在一些实施例中，沟道区536可掺杂有p型掺杂剂以在耗尽模式中提供期望的响应。
在具体实施例中，电源电压(VSS)和体偏置电压(VBN)可具有本文具体实施例中描述的关系和/或范围以及等效关系和/或范围。
图6A是根据又一实施例的钳位装置616的示意图。钳位装置616可包括n沟道结型场效应晶体管(JFET)N60、电容C60和电流源电路618。JFETN60可具有连接至第一电源(VDD)输入608-0的源极、连接至p沟道体偏置节点610-0的漏极以及连接至电流源电路618的栅极。
电容C60可连接在晶体管N60的源极和栅极之间。电流源电路618可连接在晶体管N60的栅极和低电源(VSS)接头608-2之间。电流源电路618可以以和图4A中所示电流源电路418相同的方式运行。
钳位装置616可以以和图4A中所示的相同的方式运行。随着VDD上升，VBP可由JFETP60钳制为VDD。一旦VDD达到一定电平或者稳定了预定时间量之后，就可使能电流源电路618，将N60的栅极驱动至VSS，从而关闭晶体管N60。
图6B是钳位晶体管620(例如图6A中示出为P60的晶体管)的侧剖面图示意。钳位晶体管620可形成在p阱622内，p阱622形成在深n阱624内，而n阱624形成在p型衬底626内。第一电源(VDD)输入608-0可连接至深n阱接头628-0以及钳位晶体管620的源极630。栅极632可包括驱动p阱622的p阱接头628-1。电容C60可连接在源极630和栅极632之间。漏极634可连接至p沟道体偏置节点610-0。在一些实施例中，沟道区636可掺杂有n型掺杂剂以提供期望的响应。
在具体实施例中，电源电压(VDD)和体偏置电压(VBP)可具有本文具体实施例中描述的关系和/或范围以及等效关系和/或范围。
图7A是根据又一实施例的钳位装置716的示意图。钳位装置716可包括p沟道JFETP70、电容C70和电流源电路718。JFET P70可具有连接至低电源(VSS)输入708-2的源极、连接至n沟道体偏置节点710-1的漏极以及连接至电流源电路718的栅极。
电容C70可连接在JFET P70的源极和栅极之间。电流源电路718可连接在JFET P70的栅极和高电源(VDD)接头708-0之间。电流源电路718可以以和图4A中所示电流源电路418相同的方式运行。
钳位装置716可以以和图4A中所示的相同的方式运行。随着VDD上升，VBN可由JFETP70钳制为VSS。一旦VDD达到一定电平或者稳定了预定时间量之后，就可使能电流源电路718，将P70的栅极驱动至VDD，从而关闭晶体管JFET P70。
图7B是钳位晶体管720(例如在图7A中示出为P70的晶体管)的侧剖面图示意。钳位晶体管720可形成在n阱724内，n阱724形成在p型衬底726内。低电源(VSS)输入708-2可连接至钳位晶体管720的源极730。栅极732可包括驱动n阱724的n阱接头728-0。电容C70可连接在源极730和栅极732之间。漏极734可连接至n沟道体偏置节点710-1。在一些实施例中，沟道区736可掺杂有p型掺杂剂以提供期望的响应。
在具体实施例中，电源电压(VSS)和体偏置电压(VBN)可具有本文具体实施例中描述的关系和/或范围以及等效关系和/或范围。
应当理解的是，图4A至图7B中所示的钳位装置和晶体管仅仅是提出了可包括在实施例中的电路和装置的若干可能的实例。
图8是示出典型上电操作的模拟结果的曲线图。图8包括上电后上升的电源电压VDD的波形、p沟道体偏置电压VBP的波形、n沟道体偏置电压VBN的波形以及信号VPumpEN的波形，该信号VPumpEN表明体偏置电压生成电路(例如，电荷泵)的激活。
在时刻t0，VDD开始从0V上升至1.2V。由于电容和电阻耦合，VBP和VBN随着VDD上升。这样的响应可导致p-n结正偏和/或闩锁情况。
在大约时刻t1，VDD达到所需的电平1.2V，而VPB和VBN仍保持在升高的电平。
在大约时刻t2，VPumpEN达到激活电平(在本示例中是高电平)。VBN和VBP然后被驱动至所需的体偏置电压(在图8中示出可能的体偏置电压的各种实例)。
图9是示出根据一实施例的上电操作的模拟结果的曲线图。图9包括类似于图8中的波形，包括VDD的波形、VBP的波形、VBN的波形和VPumpEN的波形。此外，图9包括第二电源电压VDDIO的波形和钳位使能信号VClampEN的波形。VDDIO大于VDD且先于VDD上升。响应于激活的(在该示例中是高电平)VClampEN信号，如在文本实施例或等效实施例所述，VBP可被钳制为VDD而VBN可被钳制为VSS。
在时刻t0，VDDIO开始从0V上升至2.5V。
在时刻t1，当VDDIO达到2.5V后，VClampEN可以被激活。结果是，VBP被钳制到VDD，而VBN被钳制到VSS。在时刻t1之后，VDD开始从0V上升至1.2V。然而，与图8不同的是，由于钳位操作，VBP追随VDD，VBN紧密追随VSS。因此，可以防止基于本体的p-n结正向体偏置和闩锁情况。
在时刻t2，VDD达到其目标值1.2V。
在时刻t3，当VDD达到稳定值后，VClampEN可返回到非激活电平。因此，VBP和VBN分别从被钳制到VDD和VSS的状态释放出来。
在时刻t4，VPumpEN可以是激活的，导致VBP和VBN被驱动至所需的体偏置电压。
图10是根据一具体实施例的钳位电路1000的示意图。在图10中的实施例中，响应于钳位使能信号(VClampEN)处于激活，钳位电路1000可将p沟道体偏置节点(VBP)钳制到高电源电压(VDD)并将n沟道体偏置节点(VBN)钳制到低电源电压(VSS)。响应于钳位使能信号(VClampEN)处于非激活，钳位电路1000可将VBP与VDD隔离开，并将VBN与VSS隔离开。
在所示的具体实施例中，钳位电路1000包括第一钳位装置1016-0、第二钳位装置1016-1和控制部1040。第一钳位装置1016-0可包括具有n沟道MOS型晶体管N100，该晶体管具有连接到VDD的源极和本体、连接到VBP的漏极以及连接为接收VClampEN的栅极。
控制部1040可包括由p沟道晶体管P100/P101/P102形成的电流镜像电路、电阻器R100和n沟道MOS型晶体管N101。晶体管P100可具有连接至第二电源电压VDDIO的源极以及彼此连接的栅极和漏极。VDDIO可先于VDD上升且大于VDD。晶体管P101/P102可形成电流镜，具有通常连接至P100的栅-漏极的源极。晶体管P101的漏极连接至它的栅极。晶体管P102可具有连接到P101栅极的栅极以及连接到控制节点1042的漏极。电阻器R100可连接在晶体管P101的栅-漏极和晶体管N101的漏极之间。晶体管N101可具有接收VClampEN的栅极以及连接至VSS的本体和源极。
控制部1040还可包括由n沟道MOS型晶体管N102/N103/N104形成的禁用电路。晶体管N102和N103可具有通常连接至控制节点1042的漏极和栅极。晶体管N102可具有连接至晶体管N104漏极的源极。晶体管N103可具有连接至n沟道体偏置节点VBN的源极。晶体管N102/N104的本体通常可彼此连接。晶体管N104可具有连接至VSS的源极。
第二钳位装置1016-1可包括n沟道MOS型晶体管N105，该晶体管具有连接到VSS的漏极、连接到VBN的源极以及连接到N103本体的本体。
在运行中，VDDIO可上升到高电平，从而使能控制部1040。
随后，VClampEN可被激活(例如，驱动至VDDIO)。结果是，第一钳位装置1016-0可将VBP钳制到VDD。此外，VClampEN可启动晶体管N101，将电流镜的一个臂牵引到低电平。这会导致控制节点1042被驱动至高电平。结果是，第二钳位装置1016-1可被启动，从而将VBN钳制到VSS。
然后VDD可升高，VBP和VBN现在可分别被钳制到VDD和VSS。
当VClampEN返回到非激活电平(例如，VSS)时，第一钳位装置1016-0可以被关闭，从而将VBP从VDD隔离开。这会使VBP被驱动至所需的体偏置电压。此外，电流镜电路内的晶体管N101关闭。结果是，控制节点1042可降压，而关闭第二钳位装置1016-1以将VBN从VSS隔离开。这会使VBN被驱动至所需的体偏置电平。即使当VBN被驱动至低于VSS时，禁用电路N102/N103/N104也能确保第二钳位装置1016-1保持关闭。
虽然实施例可包括在具有常规MOS型晶体管的IC装置中，然而在一些实施例中，集成电路装置中的全部或部分晶体管可以是具有比常规晶体管增强的体效应的“深度耗尽沟道”(DDC)晶体管。因此，施加在DDC晶体管上的体偏置电压能够用来比常规MOS型晶体管更有效地调节晶体管响应。
在一些实施例中，具有驱动体偏置电压的晶体管可以是DDC晶体管。换言之，DDC晶体管的本体可在本文所述实施例或等效实施例中上电后被钳制。此外或者可选地，组成体偏置电路的晶体管可以是DDC晶体管。因此，应当理解的是，本文实施例所述的任一MOS型晶体管都可以是DDC晶体管。
图11A示出可包括在本文实施例中的DDC型晶体管1171。DDC晶体管1171可被配置为具有增强的体系数以及以更高的精度设置阈值电压(Vt)的能力。DDC晶体管1171可包括栅极1173、源极1175、漏极1177和位于基本上未掺杂沟道1181之上的栅极介电部1179。可选的轻掺杂源漏扩展(SDE)1183分别设置为临近源极1175和临近漏极1177。该扩展1183可彼此朝对方扩展，减少基本上未掺杂沟道1181的有效长度。在所示实施例中，绝缘侧壁1193可形成在栅极1173的侧面。
在图11A中，DDC晶体管1171显示为具有由n型掺杂材料制成的源极1175和漏极1177的n沟道晶体管，其形成在一衬底上，例如p型掺杂硅衬底，其可以是p阱1185。体偏置电压VBN可通过接头1191施加至p阱1185。当然，从图11A应当可以理解出p沟道晶体管(即，具有反向掺杂型)。
在一些实施例中，DDC晶体管1171、高掺杂屏蔽区1187以及可选的阈值电压设置区1189可用具有和本体(即，图11A中的p型掺杂材料)相同导电类型的掺杂剂制成。在某些实施例中，屏蔽区1187可具有的掺杂浓度约在5×1018到1×1020掺杂剂原子/cm3范围之间，而选定的掺杂浓度取决于期望的阈值电压以及其他期望的晶体管特性。在某些实施例中，基本上未掺杂沟道区1181可具有的深度范围大约在5-25nm之间，而选定的厚度基于期望的晶体管阈值电压。
在名称为“电子装置和系统及其制造和使用方法”的专利号为8,273,617的美国专利中可找到关于DDC晶体管以及DDC晶体管的示例性制造工艺和其他方面的更多信息。
图11B示出根据实施例的可接收体偏置电压的FinFET型晶体管1171-B。FinFET晶体管1171-B可包括栅极1173-B和围绕基本上未掺杂的沟道1181-B的相对侧的栅极介电部1179-B。图11B是沿着沟道长度截取的视图。因此，应当理解的是，源极和漏极区可扩展进所示视图或从该视图扩展出来。体偏置VBB可通过连接部施加在衬底1197上。
图11C示出根据实施例可接收体偏置电压的具有屏蔽区1187-C的FinFET型晶体管1171-C。和在图11A中一样，FinFET晶体管1171-C具有可配置为具有增强体系数以及以更高的精度设置Vt的能力的高掺杂区。晶体管1171-C包括栅极1173-C和形成在基本上未掺杂沟道1181-C的相对侧之上的栅极介电部1179-C。然而，与图11B不同的是，高掺杂屏蔽区1187-C可形成在基本上未掺杂的沟道1181-C之下的衬底1197内，基本上未掺杂的沟道1181-C立体地向上攀升。可选地，Vt设置区1189-C可形成在屏蔽区1187-C和基本上未掺杂沟道1181-C之间。
和在图11B中一样，图11C是沿沟道长度截取的视图，源极和漏极区可扩展进所示视图或从该视图扩展出来，并通过基本上未掺杂沟道1181-C的部分与屏蔽区1187-C隔离开。体偏置VBB可通过连接部施加至衬底1197。在名称为“具有鳍状结构的半导体器件及其制造方法”的国际申请号为PCT/US12/49531的专利中可找到关于具有高掺杂区的FinFET晶体管的更多信息。
应当理解的是，在本发明示例性实施例的前述描述中，本发明的各种特征有时组合在单个实施例、附图或其描述中，目的是对本公开内容进行组织以辅助理解各种发明方案中的一个或多个方案。然而，本公开内容中的方法不应当被理解为体现出要求保护的发明需要比在每个权利要求中明确记载的特征更多的特征这一意图。实际上，如随后的权利要求中所反映的，本发明的方案需要的特征比所公开的单个前述实施例的所有特征要少。因此，在详细描述之后的权利要求明确并入到详细描述中，每个权利要求本身就是本发明的一个单独的实施例。
还应当理解，本发明的实施例可以在不具有明确公开的元件和/或步骤的情况下实现。也就是说，本发明的创造性特征可以是元件的省略。
因此，虽然本文已经详细描述了具体实施例的各个方面，然而在不脱离本发明的精神和范围的情况下还可以对本发明进行各种变化、替换和修改。

Claims (17)

1.一种集成电路装置，包括：
至少一第一体偏置电路，接收第一电源电压，所述第一体偏置电路被配置为生成第一体偏置电压，所述第一体偏置电压不同于所述集成电路装置的所述第一电源电压；
至少一钳位控制电路，接收所述第一电源电压，并当所述钳位控制电路检测到所述第一电源电压饱和时生成钳位信号；
至少一第一偏置控制电路，接收所述第一电源电压、所述第一体偏置电压和所述钳位信号，所述第一偏置控制电路被配置为在所述第一电源电压形成并且直到所述第一电源电压完成形成时将第一体偏置节点设置为所述第一电源电压，并且随后在所述第一电源电压达到稳定电平并且饱和之后根据所述钳位信号使得所述第一体偏置节点被设置为所述第一体偏置电压；以及
多个第一晶体管，具有连接至所述第一体偏置节点的本体。
2.根据权利要求1所述的集成电路装置，其中：
所述第一偏置控制电路包括耗尽型晶体管，所述耗尽型晶体管具有耦接在所述第一电源电压和所述第一体偏置节点之间的源-漏路径。
3.根据权利要求1所述的集成电路装置，还包括：
第二体偏置电路，接收所述第一电源电压，所述第二体偏置电路被配置为生成第二体偏置电压，所述第二体偏置电压不同于所述集成电路装置的所述第一电源电压和所述第一体偏置电压；
第二偏置控制电路，接收第二电源电压、所述第二体偏置电压和所述钳位信号，所述第二偏置控制电路被配置为在所述第一电源电压形成时将第二体偏置节点设置为所述第二电源电压，并且随后在所述第一电源电压达到稳定电平并且饱和之后根据所述钳位信号将所述第二体偏置节点设置为所述第二体偏置电压；以及
多个第二晶体管，具有连接至所述第二体偏置节点的本体。
4.根据权利要求3所述的集成电路装置，其中：
所述第一晶体管是n沟道晶体管，而所述第二晶体管是p沟道晶体管。
5.根据权利要求1所述的集成电路装置，其中：
所述集成电路装置接收第一高电源电压、大于所述第一高电源电压的第二高电源电压、以及低电源电压；
所述第一偏置控制电路由所述第二高电源电压来供电，且被配置为响应于所述第二高电源电压将所述第一体偏置节点设置为所述第一电源电压，并响应于所述第一高电源电压达到预定电平而将所述第一体偏置节点设置为所述第一体偏置电压。
6.根据权利要求5所述的集成电路装置，其中：
所述第一高电源电压小于1.5V，而所述第二高电源电压大于1.5V。
7.根据权利要求1所述的集成电路装置，其中：
所述第一偏置控制电路包括：
钳位晶体管，具有耦接在所述第一电源电压和所述第一体偏置节点之间的源-漏路径；以及
栅极控制电路，被配置为在所述第一体偏置电路形成所述第一体偏置电压期间使能所述钳位晶体管，并在所述第一体偏置电压被建立时禁用所述钳位晶体管；其中
所述钳位晶体管是从绝缘栅场效应晶体管和结型场效应晶体管的组中选择的。
8.根据权利要求1所述的集成电路装置，还包括：
所述多个第一晶体管的至少一部分包括深度耗尽沟道晶体管，每一深度耗尽沟道晶体管具有形成在基本上未掺杂沟道下方的屏蔽区，所述屏蔽区包括：
不少于1×1018掺杂剂原子/cm3的掺杂剂浓度，其中掺杂剂的导电类型与所述深度耗尽沟道晶体管的源极和漏极的导电类型相反。
9.一种方法，包括：
将第一电源电压施加至集成电路装置；
一开始在所述第一电源电压形成并且直到所述第一电源电压完成形成时将至少第一体偏置节点钳制在所述第一电源电压；
以所述第一电源电压生成至少第一体偏置电压；以及
随后在检测到所述第一电源电压饱和时使所述第一体偏置节点由所述第一体偏置电压驱动；其中
所述第一体偏置节点将所述第一体偏置电压提供给多个第一晶体管的本体。
10.根据权利要求9所述的方法，其中：
在以所述第一电源电压生成第一体偏置之前，以大于所述第一电源电压的第三电源电压生成钳位使能信号；其中
响应于所述钳位使能信号，所述第一体偏置节点被钳制在所述第一电源电压。
11.根据权利要求9所述的方法，还包括：
在所述第一电源电压形成期间一开始将所述第一体偏置节点钳制在所述第一电源电压；
以所述第一电源电压生成第二体偏置电压；以及
随后在检测到所述第一电源电压饱和时使所述第二体偏置节点由所述第二体偏置电压驱动；其中
所述第二体偏置节点将所述第二体偏置电压提供给多个第二 晶体管的本体。
12.根据权利要求9所述的方法，其中：
所述第一体偏置电压是从以下电压组成的组中选择的反向体偏置电压：大于所述第一电源电压的反向p沟道体偏置电压，以及低于低电源电压的反向n沟道体偏置电压。
13.根据权利要求12所述的方法，其中：
所述反向p沟道体偏置电压的范围为比所述第一电源电压大0.1V到1.0V，而所述反向p沟道体偏置电压的范围为比所述低电源电压低0.1V到1.0V。
14.根据权利要求9所述的方法，其中：
所述多个第一晶体管的至少一部分包括多个深度耗尽沟道晶体管，每一深度耗尽沟道晶体管具有形成在基本上未掺杂沟道下方的屏蔽区，所述屏蔽区包括：
不少于1×1018掺杂剂原子/cm3的掺杂剂浓度，其中掺杂剂的导电类型与所述深度耗尽沟道晶体管的源极和漏极的导电类型相反。
15.一种集成电路装置，包括：
第一电源连接部，被配置为接收第一电源电压；
第二电源连接部，被配置为接收大于所述第一电源电压的第二电源电压；
至少一第一体偏置生成电路，被耦接以在生成器电源节点处接收电力，并且被配置为生成第一体偏置电压；
开关电路，被配置为在所述第一电源电压形成并且直到所述第一电源电压完成形成时将所述第二电源连接部耦接至所述生成器电源节点，并在检测到所述第一电源电压饱和之后随后使得所述第一电源连接部耦接至所述生成器电源节点；以及
多个第一晶体管，具有被耦接以接收所述第一体偏置电压的本体。
16.根据权利要求15所述的集成电路装置，还包括：
调压器，被配置为接收所述第二电源电压并且调节所述第二电源电压以达到所述体偏置电压。
17.根据权利要求15所述的集成电路装置，其中：
所述多个第一晶体管的至少一部分包括多个深度耗尽沟道晶体管，每一深度耗尽沟道晶体管具有形成在基本上未掺杂沟道下方的屏蔽区，所述屏蔽区包括：
不少于1×1018掺杂剂原子/cm3的掺杂剂浓度，其中掺杂剂的导电类型与所述深度耗尽沟道晶体管的源极和漏极的导电类型相反。
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