JP4551811B2 - 半導体装置の製造方法 - Google Patents
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66818—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the channel being thinned after patterning, e.g. sacrificial oxidation on fin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Description
Masaki Kondo et al., "A FinFET Design Based on Three-Dimensional Process and Device Simulations", Toshiba Corporation, IEEE, 2003.
図1は、本発明の第1の実施形態に係る半導体装置の主要部を示す斜視図である。図2は、図1に示した半導体装置を示す平面図である。図3は、図2に示したB−B´線に沿った断面図である。
第2の実施形態は、N型半導体基板を用い、このN型半導体基板に形成されたフィンに砒素をイオン注入してパンチスルーストッパー層を形成するようにしている。
第3の実施形態は、フィン14内に2つのパンチスルーストッパー層を設けるようにしたものである。以下に、本発明の第3の実施形態に係る半導体装置の製造方法を説明する。図10までの製造工程は、第1の実施形態と同じである。
第4の実施形態は、不純物の加速電圧を調節してフィン14内に2つのパンチスルーストッパー層を形成するようにしたものである。以下に、本発明の第4の実施形態に係る半導体装置の製造方法を説明する。図11までの製造工程は、第1の実施形態と同じである。
第5の実施形態は、半導体基板としてSOI(Silicon On Insulator)構造を有する基板を用いてFinFETを形成したものである。
第6の実施形態は、エクステンション領域の不純物プロファイルを均一にするための製造方法について示している。第1の実施形態では、ゲート電極18の両側面にオフセットスペーサ20A,20Bを形成した後、半導体基板11に垂直方向(Y方向)からエクステンション領域形成のためのイオン注入を行っている。
上記各実施形態は、ダブルゲート構造を有するFinFETに本発明を適用した例を示している。しかし、これに限定されるものではなく、他のゲート構造を有するFinFETに適用してもかまわない。以下に、他のゲート構造を有するFinFETについて説明する。
Claims (4)
- 第1導電型の半導体基板上にマスク層を形成する工程と、
前記半導体基板を前記マスク層をマスクとしてエッチングし、前記半導体基板に凸状半導体層を形成する工程と、
前記半導体基板上に、前記凸状半導体層の側面に接するように絶縁層を形成する工程と、
導入される不純物が前記マスク層を介して前記凸状半導体層に到達しない厚さの前記マスク層をマスクとして、導入される不純物のピーク濃度の位置が前記半導体基板の上面と前記凸状半導体層の上面との間の絶縁層内になるように、前記絶縁層内に前記半導体基板に対して垂直方向に第1導電型の不純物を導入し、前記絶縁層内に導入された不純物が前記凸状半導体層内に移動して、前記凸状半導体層内に前記絶縁層内の不純物のピーク濃度の位置と略同じ位置に不純物のピーク濃度を有する高濃度層を形成する工程と、
前記凸状半導体層の側面にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の側面にゲート電極を形成する工程と、
を具備することを特徴とする半導体装置の製造方法。 - 第1導電型の半導体基板上にマスク層を形成する工程と、
前記半導体基板を前記マスク層をマスクとしてエッチングし、前記半導体基板に凸状半導体層を形成する工程と、
前記半導体基板上に、前記凸状半導体層の側面に接するように絶縁層を形成する工程と、
前記マスク層をマスクとして、導入される不純物のピーク濃度の位置が前記半導体基板の上面と前記凸状半導体層の上面との間の絶縁層内になるように、前記絶縁層内に前記半導体基板に対して垂直方向に第1導電型の不純物を導入し、前記絶縁層内に導入された不純物が前記凸状半導体層内に移動して、前記凸状半導体層内に前記絶縁層内の不純物のピーク濃度の位置と略同じ位置に不純物のピーク濃度を有する第1高濃度層を形成する工程と、
前記マスク層を通過した不純物が前記凸状半導体層の上部に到達して、前記凸状半導体層の上部に第2高濃度層を形成する工程と、
前記凸状半導体層の側面にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の側面にゲート電極を形成する工程と、
を具備することを特徴とする半導体装置の製造方法。 - 前記高濃度層を形成する工程の後に、前記絶縁層および前記凸状半導体層を熱処理する工程をさらに具備することを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記高濃度層は、前記凸状半導体層のチャネル領域の下部に形成されることを特徴とする請求項1乃至3のいずれかに記載の半導体装置の製造方法。
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JP2005129608A JP4551811B2 (ja) | 2005-04-27 | 2005-04-27 | 半導体装置の製造方法 |
US11/203,425 US7662679B2 (en) | 2005-04-27 | 2005-08-15 | Semiconductor manufacturing method and semiconductor device |
US12/613,143 US8043904B2 (en) | 2005-04-27 | 2009-11-05 | Semiconductor manufacturing method and semiconductor device |
US13/099,587 US8148217B2 (en) | 2005-04-27 | 2011-05-03 | Semiconductor manufacturing method and semiconductor device |
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