CN102007584B - 半导体装置结构及其相关工艺 - Google Patents

半导体装置结构及其相关工艺 Download PDF

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CN102007584B
CN102007584B CN2009801131055A CN200980113105A CN102007584B CN 102007584 B CN102007584 B CN 102007584B CN 2009801131055 A CN2009801131055 A CN 2009801131055A CN 200980113105 A CN200980113105 A CN 200980113105A CN 102007584 B CN102007584 B CN 102007584B
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曾军
穆罕默德·恩·达维希
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MaxPower Semiconductor Inc
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Abstract

本发明揭示一种改良式高可靠性功率凹陷场板(RFP)结构以及其制造工艺和操作处理。该结构包括位于这些RFP沟槽底下的复数个局部化掺杂物浓度区域，其浮动或延伸并且与MOSFET的本体层汇合，或通过竖直掺杂区域与该源极层连接。此局部掺杂物区降低该装置中本体二极管的少数载流子注入效率，并且改变该本体二极管反向恢复期间的该电场分布。

Description

半导体装置结构及其相关工艺
与相关申请的互相参引
本申请要求2008年2月14日提交的序号为61/065,759的美国临时申请的优先权，在此通过参引并入其全部内容。
技术领域
本发明涉及场效应晶体管及方法，尤其涉及具有凹陷场板(RFP，Recessed Field Plate)以及相关技术的高可靠功率绝缘栅极场效应晶体管(MOSFET)。
背景技术
功率MOSFET广泛用来作为许多电子应用当中的切换装置。为了让传导功率损耗降至最少，所以MOSFET要具有低特定接通电阻，其定义为接通电阻面积乘积(Ron*A)，其中Ron为MOSFET位于接通状态时的MOSFET电阻，A为MOSFET的面积。沟槽MOSFET提供低特定接通电阻，尤其是在10-100电压的范围内。随着单位密度增加，任何相关电容量像栅极至源极电容量Cgs、栅极至漏极电容量Cgd及/或漏极至源极电容量Cds这些也增加。在许多切换应用比如移动产品内的同步降压型DC-DC转换器当中，具备30V击穿电压的MOSFET通常以接近1MHz的较高速度来运作。因此，我们想要将这些电容量引起的切换或动态功率损失降至最低。这些电容量的幅度直接与栅极电荷Qg、栅极-漏极电荷Qgd以及输出电荷Qoss成比例。更进一步，针对在第三象限内运作的装置(即是漏极-本体结变成正向偏压时)，少数电荷于正向传导时储存在装置内。此储存的电荷导致从传导至非传导的切换延迟。为了克服此延迟，所以想要具有快速反向恢复的本体二极管。不过，快速复原本体二极管通常引起高电磁干扰(EMI，ElectromagneticInterference)，这表示在二极管复原期间，负前进波形(ta)与正前进波形(tb)之间的比例必须在软恢复时小于一，避免EMI问题。
随着对于新应用切换速度的需求提高至1MHz并且更高，最先进技术的功率MOSFET逐渐无法在这种高速下进行满意的效率运作。所以想要有一种除了有低特定接通电阻(Ron*A)还有低电荷Qg、Qgd、Qoss和Qrr的功率MOS晶体管。
目前有两种常用技术来改善功率MOSFET的切换性能，第一种就是具有厚底部氧化物的沟栅式MOSFET，如图1中所示(美国专利第6,849,898号)，第二种就是分裂多晶栅式MOSFET结构，其中第一多晶栅极与源电极进行电气短路(美国专利第5,998,833、6,683,346号)，如图2中所示。
如图3中所示，最近Darwish提出的美国专利申请第2008/0073707号揭示一种功率MOSFET，具有凹陷场板(RFP)结构，实现非常短的沟道区域(～0.25um)，用以进一步减少栅极-源极电容量以及栅极-漏极电容量，因此减少总栅极电荷(Qg)和“米勒(Miller)”电荷(Qgd)。由于提供额外电流路径和由RFP感应的漂移区域的增强耗尽，使得RFP结构可附加地改善本体二极管反向恢复速度。
发明内容
本申请揭示对于具有凹陷场板(RFP)以及类似结构的功率绝缘栅极场效晶体管的改良。发明人已经认识到，通过进行补偿植入到RFP沟槽可以改善RFP型功率MOSFET的性能。此补偿植入有助于在切断状态下形成耗尽区的边界，并因而有助于避免穿通。因为这样，局部增强还可增加至漂移或扩展区域内沟道与漏极之间的掺杂当中。这就提供一种增效的结合(Synergistic Combination)，其中接通电阻可在不恶化击穿电压的情况下得到改善。
在各种实施例中，所揭示的创新方案提供一或多个至少下列优点。不过，并非所有这些优点都由所揭示的每一个创新方案带来，列出的这些优点不限定要求保护的各种发明。
●改善的(降低的)接通电阻；
●改善的(增加的)击穿电压；
●降低RFP沟槽底部上任一介电层之上的电应力；
●较高的可靠度以及较长的操作寿命；以及/或
●提高增加漂移区域内的局部掺杂浓度的能力。
附图说明
图1为现有技术具有厚底部氧化物结构的有沟槽栅极的MOSFET截面图。
图2为具有分裂多晶栅结构的现有技术MOSFET截面图。
图3为具有与栅极沟槽平行的RFP的现有技术MOSFET截面图。
图4(a)为包含具有浮动深补偿区的MOSFET结构的RFP截面图。
图4(b)为包含具有延伸至并连接至源电极的深补偿区的MOSFET结构的RFP截面图。
图4(c)为包含具有延伸至P本体区域的深补偿区的MOSFET结构的RFP截面图。
图5显示现有RFP-MOSFET结构与包含深补偿区的MOSFET之间的二维电压仿真比较。
图6-18显示用于制作图4(a)中描绘的样本结构的样本工艺中的连续步骤。
图19A为包含具有深补偿区以及延伸超过P-N结并进入N漂移区域的P+植入区域的MOSFET结构的RFP截面图。
图19B为包含具有深补偿区以及延伸超过P-N结并进入N漂移区域的P+植入区域的MOSFET结构的RFP截面图，其中该深补偿区是轻微掺杂p区域。
图19C为包含具有深补偿区以及延伸超过P-N结并进入N漂移区域的P+植入区域的MOSFET结构的RFP截面图，其中该深补偿区是轻微掺杂n区域。
图20为包含具有深补偿区以及延伸超过P-N结并进入N漂移区域和完全下凹的N++源区域的MOSFET结构的RFP截面图。
图21-23显示在RFP沟槽内具有分裂多晶层结构的分裂多晶栅极结构中实施的图4(a)结构的一个实施例的制造工艺。
图24A、24B、24C、25A、25B和25C显示包含具有深补偿区(在图24B和25B中是轻微掺杂p区域以及在图24C和25C中是轻微掺杂n区域)的MOSFET结构的RFP实施截面图，MOSFET结构在RFP沟槽内具有单一多晶硅层结构的分裂多晶栅极结构。
图26显示图4(a)中实施例的俯视图，其中RFP区域为水平方向的连续带。
图27显示图4(a)中实施例的俯视图，其中RFP区域在水平方向分成几列。
图28显示样本制造工艺的示意流程图。
具体实施方式
在此将特别参考目前优选实施例(当成范例，不是限制性的)，来描述本申请的许多创新方案。本申请描述几个实施例，不过下面的陈述一般不应当作为对权利要求的限定。
为了图示说明的简化与清晰起见，附图图示说明了一般的构建方式，并且省略总所周知的特征与技术的描述与细节，以避免使本发明不必要地模糊不清。此外，附图中的组件并不需要依照比例绘制，某些区域或组件可扩大，有助于对本发明实施例进一步理解。
在说明书和权利要求书中“第一”、“第二”、“第三”、“第四”等词(若有的话)可以用于分辨相似的组件，不需要用于描述特定先后顺序或时间顺序。将了解的是，这些词可互换使用。更进一步，“包含”、“包括”、“具有”和这些词的任何变形意图都是涵盖非排他性包含，使包含一列组件的工艺、方法、物品、设备或组成不需要受限于这些组件，而可以包括未明确列入这种处理、方法、物品、设备或组成的或者它们所固有的其它组件。
我们考虑并想要该设计同时适用于n型与p型MOSFET；为了清晰起见，基于n沟道MOSFET结构给出范例，但是本领域普通技术人员会知道，可对该设计进行许多修改来制作类似的p沟道装置。
本申请揭示对于具有凹陷场板(RFP)以及类似结构的功率绝缘栅极场效应晶体管的改良。发明人已经认识到，通过进行补偿植入到RFP沟槽可以改善RFP型功率MOSFET的性能。此补偿植入有助于在切断状态下耗尽区的边界，并因而有助于避免穿通。因为这样，局部增强还可增加至漂移或扩展区域内沟道与漏极之间的掺杂当中。这就提供一种增效的结合，其中接通电阻可在不恶化击穿电压之的情况下得到改善。
在一个范例实施例中，包含MOSFET的RFP具有浮动在RFP沟槽底下N本体区域内的嵌埋深补偿区。在施加高的漏极-源极电压时，深补偿区降低RFP与N-外延层之间介电层的电压。
在一个范例实施例中，包含MOSFET的RFP具有浮动在RFP沟槽底下N本体区域内的嵌埋深补偿区，以及对N外延层内漂移或扩展区域内沟道与漏极间之掺杂的局部增强。
在一个实施例中，包含MOSFET的RFP还具有P本体内的深P+区域，与从P本体延伸进入N外延层的RFP沟槽壁接触。
在一个实施例中，RFP沟槽底下的深补偿区延伸至并连接至源电极。
在一个实施例中，RFP沟槽底下的深补偿区延伸至与RFP沟槽的侧壁接触的P本体区。
在一个实施例中，深补偿区为非常轻度掺杂的p区域，而在另一实施例中，深补偿区为非常轻度掺杂的n区域。
此时参阅图4(a)，半导体装置结构100包含栅极102，此栅极位于第一沟槽104内，此处也称为栅极沟槽104。包含栅极102的第一沟槽104可为半导体装置结构100内许多栅极沟槽中的一个。半导体装置结构100电容耦合来控制具有第一导电类型的垂直传导，与第一沟槽104相邻，从源极区域106通过半导体材料108。
如图4(a)中所示，栅极102具有栅电极，其包含宽度近似等于栅极沟槽104宽度的栅极导电材料。将了解的是，虽然栅电极宽度可以近似等于栅极沟槽104的宽度，但是还可使用更宽的栅极沟槽和更小的栅电极来接触栅电极，使栅极沟槽得以与栅极导体绝缘。
半导体装置结构100还包括凹陷场板110，其位于半导体材料108附近并且电容耦合至该材料。凹陷场板110位于各个第二沟槽112内，在此还描述为RFP沟槽112。每一个沟槽(即各个第二沟槽112和栅极沟槽)都具有沟槽壁，上面涂上像是二氧化硅(SiO2)这类绝缘材料。RFP沟槽112包含绝缘材料，该材料的击穿电压优选超过半导体装置结构100的击穿电压。栅极沟槽104优选包含上至p本体漏极结处的绝缘材料，将(连接至栅极102的)栅电极与漏极或漂移区域的任何重叠减至最小。
在一个实施例中，栅极沟槽包含像是二氧化硅这类厚底绝缘介电材料。在另一实施例中，RFP沟槽及/或栅极沟槽104内的绝缘材料具有阶式厚度。提供阶式厚度可有助于形成沟道，并且可有助于控制“热”电子效应。
像是n型掺杂多晶硅这类导电材料，形成利用绝缘材料与栅极沟槽104电分隔的栅电极。导电材料可以硅化来降低其电阻。导电材料也填入RFP沟槽112，利用绝缘材料与栅极沟槽104电分隔，并且延伸至RFP沟槽之上来形成复数个RFP电极。虽然RFP电极比栅电极还深，并且独立偏压或连接至源电极(即源极106)，并且源极区域(包括源电极)可在栅极106与RFP沟槽112之间延伸，但是可以每个沟槽深度基本相等或深度不同，并且可以利用在相同工艺步骤上蚀刻而自行校准。
在一个具体实施例中，一致掺杂n-外延漂移区域。在另一实施例中，不一致地掺杂n-外延漂移区域。具体来说，掺杂缓变成与底层118基板接触面处掺杂浓度较高，并且朝着表面下降。漏极漂移区域的不一致掺杂允许形成较大的沟道和控制“热”电子接合。
源极区域可掺杂n+。栅极沟槽104和RFP沟槽可具有薄的绝缘材料层，其降低接通电阻，或厚的绝缘材料层，其提供较大的电绝缘来提高反向偏置击穿电压。在描绘的实施例中，RFP电极具有一致深度。在另一实施例中，RFP电极中至少一个向上延伸并且接触源极106。
优点是，半导体装置结构100还包括至少部分位于个自RFP沟槽112底下的p型或n型深补偿区114。深补偿区114可为RFP沟槽底下N-漂移区域内的p型掺杂浓度区域(如图4a中所示)或轻度掺杂的n型掺杂浓度区域的浮动岛。图式显示此补偿区114已经完全反掺杂时的边界，但是普通技术人员将了解，可类似地想到使用例如单一掺杂种类的浓度周线(ConcentrationContours)来补偿而不是反掺杂区域的边界。
在施加高的漏极-源极电压时，深补偿区114也降低RFP与N-外延层之间介电层的电压。
如图4(b)中所示，装置100还包含深p本体区域116，其与RFP沟槽112的侧壁接触。具有边界116a的深p本体区域116可与源电极连接，并且也可与深补偿区114连接。边缘终端上的深P-N结可以通过深补偿植入及其相关退火来形成而不需添加新掩模。因此，揭示的结构可提供更可靠的边缘端点。
另外，如图4(c)中所示，深补偿区114可垂直延伸并且与p本体区域汇合。
图5中显示的二维电压仿真揭露了在相同的偏压条件下，图3中所示结构的常规装置显示RFP与N-外延层之间的底部介电层大约19V，而图4(a)至4(c)的实施例显示由于深补偿区114的保护，所以RFP与N外延层之间的底部介电层只有7V。
随着RFP与漏极之间底部介电层上的电应力显著降低，图4(a)至4(c)的装置结构将提供较高可靠度以及较长操作寿命。此外，深补偿区114增强了N-外延层的横向与竖直耗尽，如此为外延层内较高局部掺杂浓度提供空间，而不降低装置击穿电压。
外延层内局部掺杂浓度的增加进一步降低漂移区域的接通电阻。通过适当调整N-外延层内P与N区域的掺杂浓度，装置的总接通电阻可以下降而不降低击穿电压。更进一步，局部掺杂增强的N层也降低装置中本体二极管的少数载流子注入效率，并且改变本体二极管反向恢复期间的电场分布。如此，改善本体二极管的反向恢复，导致装置具有较低反向恢复电荷以及软恢复特征。
既然掺杂增强只发生在活性区中，已改善的装置边缘结终端区域的终止效率将不会下降。
凹陷场板110可分别位于多个沟槽112内，这些沟槽与栅极沟槽104分隔。因此，半导体装置结构100可为例如n-沟道MOSFET，其具有在重度掺杂N+基板上生长的N型外延层上形成的凹陷场板(RFP)沟槽112和栅极沟槽104。
在第三象限操作时，其中漏极118相对于源极本体电极(即源极106)负向偏压，并且其中扩散电流导致少数载流子注入以及高的反向恢复电荷Qrr，复数个RFP电极形成除了常规结构中栅电极所提供的以外的从漏极到源极的多数载子沟道电流路径。RFP电极与栅电极的组合效果是既降低少数载流子扩散电流又降低恢复电荷Qrr。因此，在第三象限操作时，RFP电极作为额外栅极，而无任何加入栅极-漏极电容量Cgd的不利后果。
在反向偏压操作时，RFP还降低沟道区域内的任何电场。因此，可缩短沟道长度，而无穿通击穿的重大风险，进一步降低Ron*A和Qg。以切断状态下漏极-源极电压VDS提高的较高速率，栅极沟槽104、RFP沟槽112和漏极区域之间的电容耦合进一步耗尽漏极漂移区域。低Cgd及其快速下降速率，结合提高的漏极-源极电压VDS，提供较低栅极-漏极电荷。
半导体装置结构100可具有准竖直或横向组态。确定半导体装置结构100具有准竖直或横向组态可有助于形成沟道，并且可降低热电子效应。
可以使用栅极导体与RFP导体的各种变型。Darwish提出的第2008/0073707A1号美国专利申请中显示了各种组合，将其全部内容通过参引在此并入。多晶硅可用来作为导电材料。栅极导体与RFP导体结构设计上的范例变型包括分裂多晶组态和单一多晶组态(图21-25)，厚底氧化物、台阶形底部氧化物以及许多形式的组合。
参阅图26，每一前述实施例都可在单一组态、多带组态、蜂巢式布局组态或前述组合中实施。再者，正负极性与导电类型可以反向。
参阅图27，每一前述实施例RFP还可以用中断方式实施，其中RFP沟槽与导体在装置的源极-本体-漏极层中形成列。运用此中断法，可提供更多N++表面积、减少N++电阻并且降低总接通电阻。
图6-18中详述所述实施例的制造工艺。在图6中，以N++基板201开始，生长N-外延层203之后接着形成氧化硅层205的薄层。基板201可以掺杂磷或砷。氧化物层205的优选厚度可为例如
Figure BPA00001237988500091
在图7中，施加沟槽掩模207来形成用于沟槽蚀刻的硬掩模，并且蚀刻氧化物层。
然后，执行标准的硅蚀刻步骤，以根据掩模形成复数个沟槽209。在图8中，将磷离子211(例如P31)毯覆式植入整个装置可执行，以局部增加N-外延层的掺杂浓度。最好在倾斜0度时执行植入。边缘终端区或栅极总线区周围的沟槽掩模(附图中未显示)防止磷掺杂物进入这些区域。因此，只有装置的活性区域接收掺杂增强植入。
植入之后，使用含氧环境中的高温处理进行退火并扩散磷掺杂物。结果，在N-外延层里面形成掺杂增强N层213，如图9中所示。然后可以先使用牺牲氧化来氧化沟槽壁。在移除牺牲氧化层之后，沿着沟槽侧壁再生衬垫氧化物。在图10中，沟槽填充高密度氧化物217。氧化物217可包括二氧化硅或其它类型的沉积氧化物，像是LTO或TEOS或高密度等离子体(HDP，High Density Plasma)氧化物。然后如图11中所示，使用等离子体干法蚀刻或CMP技术将氧化物变薄以对氧化物表面219进行平坦化。
在图12中，在施加活性掩模223而在沟槽222上有开口之后，进一步向下蚀刻氧化物进入沟槽，形成沟槽底部氧化物层(BOX，Bottom Oxide Layer)221。然后在图13中，使用BOX掩模保护活性栅极沟槽225和边缘端端区(未显示)。执行氧化物去除步骤，将RFP沟槽里面的BOX完全蚀刻掉。在去除BOX掩模之前，硼-11离子229通过RFP沟槽底部231植入N/N-外延层，形成P层或绝缘区237，如图14中所示。
在一个实施例中，若要实施图4(c)中所示的结构，使用倾斜角植入来沿着RFP侧壁导入硼。在去除BOX光致抗蚀剂233之后，采用可选的高温退火来扩散硼，在N-外延区域里面形成P层或绝缘区237。然后沿着图14中的沟槽侧壁生长栅极氧化物235。
图15至图17中所示其余的处理步骤类似于第2008/0073707号美国专利申请中图14-17中所述的步骤，通过参引将其在此并入。图18中显示最终的装置结构。必须指出，通过适当选择RFP多晶凹陷深度结合P+植入的植入能量，可使P+区域比P本体深，如图19A中所示。根据P屏蔽区域(或绝缘区)的掺杂浓度，P屏蔽区为图19C中所示的“π”区域260(非常轻度掺杂的P区域)或图19B中所示的“ν”区域250(非常轻度掺杂的n区域)。在此想要有较深的P+区域，以便改善装置粗糙度并且将嵌埋的P区域连接至源电极。此外，N++源极区域也可完全凹陷，如图20中所示，以使N++源极光学掩模步骤可消除。
更进一步，本发明中提出的技术也可使用分裂多晶栅极式装置结构来实施。图21至图23中简略地演示一种实施法。该工艺包括将第一多晶层沉积在沟槽内、多晶回蚀刻以及氧化物去除、栅极氧化、第二多晶层沉积、以及CMP和/或多晶回蚀刻。使用图21-23中显示的分裂栅极式双层多晶组态，来取代图18中所示的活性沟槽栅极与RFP沟槽内的单一多晶层。在此情况下，RFP沟槽内的多晶底层和多晶上层都与源极金属电气短路。此外，图23中装置的RFP区域内的分裂多晶层可以由图24A和图25A所演示的单一RFP多晶层直接取代。根据P屏蔽区域(或绝缘区)的掺杂浓度，在非常轻的浓度之下，P屏蔽区为“π”区域(非常轻度掺杂的p区域)或“ν”区域(非常轻度掺杂的n区域)，如图24B、24C、25B和25C中所示。
图28为描绘根据本发明一个实施例用于制作MOSFET的制造工艺的流程图。该制造工艺包括在N+基板上生长302N-外延层。该制造工艺还包括局部增加304N-外延层内的掺杂浓度。局部增加304N-外延层内的掺杂浓度包括毯覆式植入磷。磷的毯覆式植入可在零度倾斜角度上执行，或可在其它倾斜角度上执行。局部增加304N-外延层内的掺杂浓度还包括从边缘终端区和/或栅极总线区排除磷掺杂物，包括将氧化物留在边缘终端区或栅极总线区。
制作MOSFET的制造工艺还包括在N-外延层里面创建306掺杂增强N层，包括在氧气环境中使用高温热处理来退火并扩展磷掺杂物。制作MOSFET的制造工艺还包括对沟槽的沟槽表面进行平滑化308，并且降低沟槽硅蚀刻期间引起的沟槽表面粗糙度，包括氧化沟槽侧壁、去除310牺牲氧化物层以及沿着沟槽侧壁再生312衬垫氧化物。
制作MOSFET的制造工艺还包括用高密度氧化物填充314沟槽、对氧化物表面进行平坦化316，包括回蚀刻氧化物、形成底部氧化物层(BOX)，包括使用活性掩模进一步向下蚀刻进入沟槽，并且使用BOX掩模保护318活性栅极沟槽和边缘终端。制作MOSFET的制造工艺还包括将硼(B11)通过凹陷场板沟槽底部植入320N-外延层，包括以倾斜角度沿着凹陷场板侧壁导入硼、完全蚀刻掉322凹陷场板沟槽里面的BOX，包括去除氧化物、可选地驱动324形成P层的硼进入N-外延层，包括高温退火并沿着沟槽侧壁生长324栅极氧化物。
针对样本40V的实施例而言，优选参数如下。不过必须了解的是，这些参数可缩放用于不同操作电压，当然也可调整用于许多其它工艺。在此样本实施例中，沟槽宽度为0.3微米，深度大约1.0微米，并且相隔一微米(既然存在两种沟槽，那么原细胞相隔二微米)。在此样本实施例内，开始材料为0.35欧姆-厘米n-on-n+外延层(epi)，大约5.5微米厚。执行毯覆式n增强植入，例如用3E12/cm2(即3x1012cm-2)的磷。然后蚀刻沟槽。在牺牲氧化与沟槽填充之后(优选使用沉积的氧化物加上氧化处理)，优选执行回蚀刻来清除沟槽至大约一半深度。然后将光致抗蚀剂形成图样，以露出RFP沟槽但不露出栅极沟槽，并且从RFP沟槽中去除氧化物塞。然后执行P型植入来形成P绝缘区域；在此范例中为两次硼植入的组合，30keV时2.5E12/cm2的一个加上120keV时2E12的另一个。这将产生低于RFP沟槽大约0.7微米深的被反掺杂或补偿的绝缘区域114。然后以常规方式继续进行其余的处理步骤，形成栅极、本体、源极、触点等等。
如上所述，在上述各种实施例中，将栅极连接至漏极的局部增强n掺杂降低了接通电阻。不过，正是由促成此增强的n掺杂的该新添加的绝缘区域提供了改良的切断状态行为。
在替代实施例中，绝缘区域的深度可为从例如0.25微米到2.5微米，并因此被缩放用于除40V之外的操作电压。类似地，在替代实施例中，绝缘植入可使用在20-320keV上从2E12cm-2至1E13的剂量，或甚至更高或更低剂量和/或能量，加上允许缩放量。
容易了解的是，上述仅为本发明某些特定示出和示范的实施例的描述，不应当认为是对本发明范围内全部实施例的描述。
根据各种实施例，提供：半导体装置结构，包含位于第一沟槽内的栅极，并电容耦合来控制从第一导电类型的源极通过与所述沟槽相邻的半导体材料的竖直传导；凹陷场板，其位于所述半导体材料附近并电容耦合至该材料；所述凹陷场板位于各个第二沟槽内；以及至少部分位于所述的各个第二沟槽底下的第二导电类型的扩散。
根据各种实施例，提供：半导体装置结构，包含半导体层；栅极，其位于所述半导体层内的第一沟槽内，并电容耦合来控制从第一导电类型的源极通过所述沟槽附近的所述层的第二导电类型部分的竖直传导；凹陷场板，其位于所述半导体材料附近并电容耦合至该材料；所述凹陷场板位于各个第二沟槽内；至少部分位于所述各个第二沟槽底下的第二导电类型的扩散组件；由此所述扩散组件减少在切断状态下所述层的所述第二导电类型部分的耗尽。
根据各种实施例，提供：半导体装置结构，包含半导体层；栅极，其位于所述半导体层内的第一沟槽内，并电容耦合来控制从第一导电类型的源极通过所述沟槽附近所述层的第二导电类型部分的竖直传导；凹陷场板，其位于所述半导体材料附近并电容耦合至该材料；所述凹陷场板位于各个第二沟槽内；至少部分位于所述各个第二沟槽底下的第二导电类型的第一额外扩散组件；以及至少部分位于所述层的所述第二导电类型部分内的所述第一传导类型的第二额外扩散组件；由此所述第一额外扩散组件减少在切断状态下所述层的所述第二传导类型部分的耗尽；以及由此所述第二额外扩散组件减少在接通状态下该装置的该接通电阻。
根据各种实施例，提供：改良的RFP晶体管结构，其具有(a)低的总接通电阻，(b)减少的(本体二极管的)少数载流子注入效率，(c)改良的(本体二极管的)反向恢复，(c)降低的反向恢复电荷，(d)软恢复特性，(e)作为可靠的边缘终端，既不降低击穿电压也不降低装置边缘结终端区域的终端效率，该改善的结构包含：RFP晶体管结构，其包括与一或多个凹陷场板沟槽相邻的至少一或多个栅极沟槽；以及位于所述凹陷场板沟槽底下的各个深补偿区。
根据各种实施例，提供：一种操作半导体装置结构的方法，包含：使用位于第一沟槽内的栅电极，控制第一与第二源/漏电极之间通过半导体材料内的沟道位置的传导，以提供至少接通与切断状态；以及使用位于所述半导体材料附近并且电容耦合至该材料的一或多个凹陷场板，来避免穿通所述沟道位置；所述凹陷场板位于各个第二沟槽内，并且一或多个第二导电类型的扩散组件至少部分位于所述各个第二沟槽底下；由此所述扩散组件降低在该切断状态下的耗尽扩展。
根据各种实施例，提供：用于制作MOSFET的制造工艺，包含顺序如下的动作：a)提供n型半导体层；b)在所述层内形成p型本体；c)在所述层内形成n型源极，其由所述本体绝缘；d)在所述层内形成绝缘栅极沟槽；以及在所述栅极沟槽内形成栅电极；所述栅电极电容耦合至所述本体的至少一部分；e)在所述层内形成第二绝缘沟槽，在所述沟槽之下提供额外剂量的受体掺杂物，以及在所述第二沟槽内形成凹陷场板电极；以及f)在所述本体的所述部分内提供额外剂量的施体掺杂物原子，由此减小该接通电阻。
根据各种实施例，提供：改良的高可靠性功率RFP结构以及制造与操作工艺。该结构包括RFP沟槽底下的复数个局部化掺杂物浓度区，其浮动或延伸并与MOSFET的本体层汇合，或通过竖直掺杂区域与该源极层相连。此局部掺杂区降低该装置中该本体二极管的少数载流子注入效率，并且改变该本体二极管反向恢复期间的电场分布。
修改与变型
本领域技术人员将会了解，本申请书内描述的创新概念可在广大应用范围上修改与变化，因此申请专利的主题的范围并不受限于给出的任何特定范例方案。意图是包含落入所附权利要求的精神和广阔范围内的所有这些替换、修改以及改变。
该装置可以各种布局制造，包括“直条状”与“蜂巢状”布局。源极、本体与漏极区域各层可设置成竖直、半竖直以及横向。外延漂移区域可一致或不一致掺杂。虽然上述实施例包括在基板上生长的外延层，但是在某些应用当中可省略该外延层。不同实施例的许多特征针对各种应用可结合与重新结合。
例如，沟道与漏极之间的区域不必一致掺杂，也不必竖直或横向掺杂。本发明所提供漂移或扩展区域掺杂的改善可与各种各样的其它装置改善与特征相结合。
另一个例子，RFP和栅极沟槽不必宽度相同。
该设计适用于IGBT或包括双极性传导的其它装置。该栅极沟槽的底部可用掺杂物修改；该设计也可在该源极结构与该漏极结构上改变并且可使用替代本体结构；可先产生触点沟槽，然后切削栅极沟槽并且建构该源极与漏极结构。
当然，硅内的n型掺杂物可为磷、锑或砷或这些材料的组合。适当的施体掺杂物可用于其它半导体材料中。
随所揭示处理缩放至其它操作电压，我们预期尺寸与掺杂物的预测缩放可遵照相同的增效，例如，在200V实施例中，发明人预计沟槽深度会稍微深一点(例如1.5至2.5微米)，并且补偿植入能量与剂量会大约相同。当然外延(epi)层掺杂会基本上较少并且外延(epi)层厚度较厚，如普通技术人员都了解的。n增强掺杂(优选为与终端的连通被阻挡)可具有一种分布，在驱动进入之后，到达补偿植入的上边界，但优选的是不到达补偿植入的下边界。
下列申请包含额外信息以及替代修改：律师案卷号MXP-14P、序号61/125,892，04/29/2008提出；律师案卷号MXP-15P、序号61/058,069，6/2/2008提出并且标题为“Edge Termination for Devices Containing PermanentCharge”；律师案卷号MXP-16P、序号61/060,488，6/11/2008提出并且标题为“MOSFET Switch”；律师案卷号MXP-17P、序号61/074,162，6/20/2008提出并且标题为“MOSFET Switch”；律师案卷号MXP-18P、序号61/076,767，6/30/2008提出并且标题为“Trench-Gate Power Device”；律师案卷号MXP-19P、序号61/080,702，7/15/2008提出并且标题为“A MOSFET Switch”；律师案卷号MXP-20P、序号61/084,639，7/30/2008提出并且标题为“LateralDevices Containing Permanent Charge”；律师案卷号MXP-21P、序号61/084,642，7/30/2008提出并且标题为“Silicon on Insulator DevicesContaining Permanent Charge”；律师案卷号MXP-22P、序号61/027,699，2/11/2008提出并且标题为“Use of Permanent Charge in Trench Sidewalls toFabricate Un-Gated Current Sources，Gate Current Sources，and SchottkyDiodes”；律师案卷号MXP-23P、序号61/028,790，2/14/2008提出并且标题为“Trench MOSFET Structure and Fabrication Technique that UsesImplantation Through the Trench Sidewall to Form the Active Body Region andthe Source Region”；律师案卷号MXP-24P、序号61/028,783，2/14/2008提出并且标题为“Techniques for Introducing and Adjusting the DopantDistribution in a Trench MOSFET to Obtain Improved Device Characteristics”；律师案卷号MXP-25P、序号61/091,442，8/25/2008提出并且标题为“DevicesContaining Permanent Charge”；律师案卷号MXP-27P、序号61/118,664，12/1/2008提出并且标题为“An Improved Power MOSFET and Its EdgeTermination”以及律师案卷号MXP-28P、序号61/122,794，12/16/2008提出并且标题为“A Power MOSFET Transistor”。
不应当将本申请中的描述看待为暗示任何特定组件、步骤或功能为必须包含在权利要求范围内的必要项：申请专利的主题的范围只由所允许的权利要求书所限定。再者，除非有“装置用于”加上分词的确切字眼，否则这些权利要求无唤起35美国法典(USC)第112节第六段的意图。
所提交的权利要求书意图在于尽可能全面，无任何主题要撤回、独占或放弃。

Claims (31)

1.一种半导体装置结构，包含：
栅极，其位于第一沟槽内，电容耦合来控制从第一导电类型的源极通过与所述沟槽相邻的半导体材料的竖直传导；该栅极具有分裂多晶组态；
凹陷场板，其位于所述半导体材料附近并电容耦合至该材料；所述凹陷场板位于各个第二沟槽内；以及
至少部分位于所述各个第二沟槽底下的第二导电类型的扩散组件。
2.如权利要求1的半导体装置结构，其中所述装置还包括一层第二导电类型的掺杂物浓度区域，其从源极层延伸到所述扩散组件的至少其中之一。
3.如权利要求1的半导体装置结构，其中所述扩散组件的至少其中之一竖直延伸，并且与第二导电类型的本体层汇合。
4.如权利要求1的半导体装置结构，其中所述装置还包括一层第二导电类型的掺杂物浓度区域，其从源极层延伸到所述扩散组件的至少其中之一，并且所述扩散组件的至少其中之一竖直延伸，并与第二导电类型的本体层汇合。
5.如权利要求1的半导体装置结构，其中这些凹陷场板的至少其中之一具有分裂多晶组态。
6.如权利要求1的半导体装置结构，其中该栅极与这些凹陷场板的至少其中之一具有分裂多晶组态。
7.如权利要求1的半导体装置结构，其中所述第一导电类型为n型。
8.如权利要求1的半导体装置结构，其中所述栅极电容耦合来控制向所述第一导电类型的漏极扩散组件的竖直传导。
9.一种半导体装置结构，包含：
半导体层；
栅极，其位于所述半导体层内的第一沟槽内，电容耦合来控制从一第一导电类型的源极通过所述沟槽附近所述层的第二导电类型部分的竖直传导；所述栅极具有分裂多晶组态；
凹陷场板，其位于所述半导体材料附近并电容耦合至该材料；所述凹陷场板位于各个第二沟槽内；
至少部分位于所述各个第二沟槽底下的第二导电类型的扩散组件；
由此所述扩散组件减少在切断状态下所述层的所述第二导电类型部分的耗尽。
10.如权利要求9的半导体装置结构，其中所述凹陷场板的至少其中之一具有分裂多晶组态。
11.如权利要求9的半导体装置结构，其中该栅极与这些凹陷场板的至少其中之一具有分裂多晶组态。。
12.如权利要求9的半导体装置结构，其中所述扩散组件浓度高得足以局部反掺杂所述半导体层并由此产生低于该第二沟槽的第二导电类型区域。
13.如权利要求9的半导体装置结构，其中所述半导体层是外延层。
14.一种半导体装置结构，包含：
半导体层；
栅极，其位于所述半导体层内的第一沟槽内，电容耦合来控制从第一导电类型的源极通过所述沟槽附近所述层的第二导电类型部分的竖直传导；
凹陷场板，其位于所述半导体材料附近并电容耦合至该材料；所述凹陷场板位于各个第二沟槽内；
至少部分位于所述各个第二沟槽底下的第二导电类型的第一额外扩散组件；以及
至少部分位于所述层的所述第二传导类型部分内的所述第一导电类型的第二额外扩散组件；
由此所述第一额外扩散组件减少在切断状态下所述层的所述第二导电类型部分的耗尽；
以及由此所述第二额外扩散组件减少在接通状态下该装置的该接通电阻。
15.如权利要求14的半导体装置结构，其中所述栅极具有分裂多晶组态。
16.如权利要求14的半导体装置结构，其中所述凹陷场板的至少其中之一具有分裂多晶组态。
17.如权利要求14的半导体装置结构，其中该栅极与这些凹陷场板的至少其中之一具有分裂多晶组态。
18.如权利要求14的半导体装置结构，其中所述扩散组件浓度高得足以局部反掺杂所述半导体层，由此产生低于所述第二沟槽的第二导电类型区域。
19.如权利要求14的半导体装置结构，其中所述半导体层是外延层。
20.一种改良式RFP晶体管结构，其具有低的总接通电阻，降低的本体二极管的少数载流子注入效率，改良的本体二极管的反向恢复，减少的反向恢复电荷，软恢复特性，作为可靠的边缘终端，既不降低击穿电压又不降低装置边缘节终端区域的终端效率，该改善的结构包含：
RFP晶体管结构，包括与一或多个凹陷场板沟槽相邻的至少一或多个栅极沟槽；以及
位于所述凹陷场板沟槽底下的各个深补偿区。
21.如权利要求20的改良式RFP晶体管结构，其中位于该凹陷场板区域底下的该嵌埋绝缘区在浮动。
22.如权利要求20的改良式RFP晶体管结构，其中位于该凹陷场板区域底下的该嵌埋绝缘区由深P区域连接至该源电极。
23.如权利要求20的改良式RFP晶体管结构，其中位于该凹陷场板区域底下的该嵌埋绝缘区竖直延伸并且与该P本体区域汇合。
24.一种操作半导体装置结构的方法，包含：
使用位于第一沟槽内的栅电极，控制第一与第二源/漏电极之间通过半导体材料内的沟道位置的传导，以提供至少接通与切断状态；以及
使用位于所述半导体材料附近并且电容耦合至该材料的一或多个凹陷场板，避免穿通所述沟道位置；所述凹陷场板位于各个第二沟槽内，并且
第二导电类型的一或多个扩散组件至少部分位于所述各个第二沟槽底下；
由此所述扩散组件降低该切断状态下的耗尽扩展。
25.如权利要求24的方法，其中所述装置还包括一层第二导电类型的掺杂物浓度区域，其从源极层延伸到所述扩散组件的至少一个位置。
26.如权利要求24的方法，其中该栅极具有分裂多晶组态。
27.如权利要求24的方法，其中这些凹陷场板的至少其中之一具有分裂多晶组态。
28.如权利要求24的方法，其中该栅极与这些凹陷场板的至少其中之一具有分裂多晶组态。
29.如权利要求24的方法，其中所述第一导电类型为n型。
30.如权利要求24的方法，其中所述栅极电容耦合来控制向所述第一导电类型的漏极扩散的竖直传导。
31.一种用于制作MOSFET的制造工艺，包含顺序如下的动作：
a)提供n型半导体层；
b)在所述层内形成p型本体；
c)在所述层内形成n型源极，其由所述本体绝缘；
d)在所述层内形成绝缘栅极沟槽，以及在所述栅极沟槽内形成栅电极；所述栅电极电容耦合至所述本体的至少一部分；
e)在所述层内形成第二绝缘沟槽，在所述沟槽之下提供额外剂量的受体掺杂物，以及在所述第二沟槽内形成凹陷场板电极；以及
f)在所述本体的所述部分内提供额外剂量的施体掺杂物原子，由此减小该接通电阻。
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