CN106206738B - 一种积累型功率dmos器件 - Google Patents
一种积累型功率dmos器件 Download PDFInfo
- Publication number
- CN106206738B CN106206738B CN201610705710.3A CN201610705710A CN106206738B CN 106206738 B CN106206738 B CN 106206738B CN 201610705710 A CN201610705710 A CN 201610705710A CN 106206738 B CN106206738 B CN 106206738B
- Authority
- CN
- China
- Prior art keywords
- lightly doped
- groove
- metal
- oxide layer
- type lightly
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000009825 accumulation Methods 0.000 title claims abstract description 33
- 239000002184 metal Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000005036 potential barrier Methods 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000011084 recovery Methods 0.000 abstract description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000004888 barrier function Effects 0.000 abstract description 3
- 238000011982 device technology Methods 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 238000001727 in vivo Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本发明涉及功率半导体器件技术领域，具体涉及到一种积累型DMOS。本发明提出的一种积累型功率DMOS器件新结构，利用肖特基结的势垒区耗尽栅下的半导体区，从而解决常规积累型功率DMOS为常开型器件的问题。本发明提出的积累型功率DMOS除了是一种常关型器件，还具有阈值电压较低、导通电阻较小、体二极管反向恢复特性好、不存在寄生三极管等优点。
Description
技术领域
本发明涉及功率半导体器件技术领域，具体涉及到一种积累型功率DMOS(双扩散金属氧化物半导体场效应晶体管)。
背景技术
功率DMOS开关速度快，开关损耗小；输入阻抗高，驱动功率小；频率特性好；跨导高度线性。大电流时它具有负的温度系数，没有双极功率器件的二次击穿问题，安全工作区大。功率DMOS器件的发展是在MOS器件自身优点的基础上，努力提高耐压和降低损耗的过程。
功率DMOS的导通电阻包括：源区电阻、沟道电阻、积累电阻、JFET电阻、漂移区电阻和漏区电阻。对于低压DMOS来说，沟道电阻在总导通电阻中也占有较重要的比重。为了降低功率DMOS的沟道电阻，以适应低功耗场合的应用，研究者提出了积累型的功率DMOS器件，即用与衬底相同掺杂的积累型沟道替代传统的反型层沟道。但是，积累型功率DMOS由于在栅上不加电压时始终处于导通状态，是一种常开型器件，因此具有较大的静态功耗。
发明内容
本发明的目的是提供一种积累型功率DMOS，解决常规积累型功率DMOS为常开型器件的问题。本发明提出的积累型功率DMOS除了是一种常关型器件，还具有阈值电压较低、导通电阻较小、体二极管反向恢复特性好、不存在寄生三极管等优点。
本发明所采用的技术方案：一种积累型功率DMOS，包括从下至上依次层叠设置的金属化漏极1、N+衬底2、N漂移区3和金属化源极10；所述N漂移区3上层具有N-型轻掺杂区8；所述N-型轻掺杂区8正上方具有N+重掺杂区9；所述N+重掺杂区9的上表面与金属化源极10接触；所述N漂移区3内部还具有第一沟槽和第二沟槽；所述第一沟槽沿N+重掺杂区9上表面中部垂直向下依次贯穿N+重掺杂区9和N-型轻掺杂区8后延伸入N漂移区3中；所述第二沟槽位于第一沟槽两侧，第二沟槽沿N+重掺杂区9上表面垂直向下依次贯穿N+重掺杂区9和N-型轻掺杂区8后延伸入N漂移区3中；所述第一沟槽中具有多晶硅栅电极4和厚氧化层51，所述多晶硅栅电极4位于厚氧化层51的正上方，所述多晶硅栅电极4两侧具有栅氧化层53，所述多晶硅栅电极4正上方具有隔离氧化层54；所述第二沟槽的上部填充金属7，所述金属7的顶部与金属化源极10直接接触，所述金属7的正下方具有多晶硅场板6和氧化层52，所述多晶硅场板6的侧面及底部被氧化层52包围；所述金属7与N-型轻掺杂区8形成肖特基接触，金属7与N+重掺杂区9形成欧姆接触；所述N-型轻掺杂区8的宽度等于或小于金属7与N-型轻掺杂区8形成的肖特基结在不加偏置时的势垒区宽度；所述N-型轻掺杂区8下表面的深度大于金属7的下表面的深度，N-型轻掺杂区8下表面的深度小于多晶硅栅电极4下表面的深度。
进一步的，所述氧化层5为二氧化硅或者二氧化硅和氮化硅的复合材料。
进一步的，在氧化层52和厚栅氧化层51下方，注入了P型埋层11。
进一步的，所述多晶硅栅电极4的下表面延长到与多晶硅场板6下表面平齐。
本发明的有益效果为，本发明所提供一种积累型功率DMOS，解决常规积累型功率DMOS为常开型器件的问题。本发明提出的积累型功率DMOS除了是一种常关型器件，还具有阈值电压较低、导通电阻较小、体二极管反向恢复特性好、不存在寄生三极管等优点。
附图说明
图1是本发明实施例1所提供的积累型功率DMOS的剖面结构示意图；
图2是本发明实施例2所提供的积累型功率DMOS剖面结构示意图；
图3是本发明实施例3所提供的积累型功率DMOS剖面结构示意图；
图4是本发明实施例4所提供的积累型功率DMOS剖面结构示意图。
具体实施方式
下面结合附图，详细描述本发明的技术方案：
实施例1
如图1所示一种积累型功率DMOS，包括从下至上依次层叠设置的金属化漏极1、N+衬底2、N漂移区3和金属化源极10；所述N漂移区3上层具有N-型轻掺杂区8；所述N-型轻掺杂区8正上方具有N+重掺杂区9；所述N+重掺杂区9的上表面与金属化源极10接触；所述N漂移区3内部还具有第一沟槽和第二沟槽；所述第一沟槽沿N+重掺杂区9上表面中部垂直向下依次贯穿N+重掺杂区9和N-型轻掺杂区8后延伸入N漂移区3中；所述第二沟槽位于第一沟槽两侧，第二沟槽沿N+重掺杂区9上表面垂直向下依次贯穿N+重掺杂区9和N-型轻掺杂区8后延伸入N漂移区3中；所述第一沟槽中具有多晶硅栅电极4和厚氧化层51，所述多晶硅栅电极4位于厚氧化层51的正上方，所述多晶硅栅电极4两侧具有栅氧化层53，所述多晶硅栅电极4正上方具有隔离氧化层54；所述第二沟槽的上部填充金属7，所述金属7的顶部与金属化源极10直接接触，所述金属7的正下方具有多晶硅场板6和氧化层52，所述多晶硅场板6的侧面及底部被氧化层52包围；所述金属7与N-型轻掺杂区8形成肖特基接触，金属7与N+重掺杂区9形成欧姆接触；所述N-型轻掺杂区8的宽度等于或小于金属7与N-型轻掺杂区8形成的肖特基结在不加偏置时的势垒区宽度；所述N-型轻掺杂区8下表面的深度大于金属7的下表面的深度，N-型轻掺杂区8下表面的深度小于多晶硅栅电极4下表面的深度。
本发明的工作原理为：
(1)器件的正向导通
本发明所提供的积累型功率DMOS，其正向导通时的电极连接方式为：槽型栅电极4接正电位，金属化漏极1接正电位，金属化源极10接零电位。当槽型栅电极4为零电压或所加正电压非常小时，由于金属7和N-型轻掺杂区8形成的肖特基结存在势垒区，同时栅电极4和N-型轻掺杂区8存在功函数差，且N-型轻掺杂区8非常窄，故造成N-型轻掺杂区8完全耗尽，电子通道被阻断，此时积累型功率DMOS仍处于关闭状态。因此，该器件为常关型器件。
随着槽型栅电极4所加正电压的增加，N-型轻掺杂区8内的耗尽区逐渐缩小，器件由关断状态向开启状态转换。由于采用N-型轻掺杂区8代替了常规功率MOS中的P型体区，器件更容易开启，从而降低了阈值电压。当槽型栅电极4所加正电压等于或大于开启电压之后，由于栅氧化层53侧面处的N-型轻掺杂区8内产生多子电子的积累层，这为多子电流的流动提供了一条低阻通路，导通电阻从而得到降低，此时积累型功率DMOS导通，多子电子在金属化漏极1正电位的作用下从N+重掺杂区9流向金属化漏极1。由于本发明采取了更高的漂移区3掺杂浓度，有利于进一步降低导通电阻。另外，由于槽型栅电极4底部的栅氧化层51采取厚氧工艺，所以栅漏电容Cgd得到较大的改善。
(2)器件的反向阻断
本发明所提供的积累型功率DMOS，其反向阻断时的电极连接方式为：槽型栅电极4和金属化源极10短接且接零电位，金属化漏极1接正电位。
由于零偏压时金属7和栅氧化层53之间的N-型轻掺杂区8已经被完全耗尽，多子电子的导电通路被夹断。增大反向电压时，金属7和N-型轻掺杂区8形成的肖特基结反向偏置，势垒区展宽，N漂移区3开始承受反向耐压，由于体内场板6和厚栅氧化层51的存在，使N漂移区中形成横向电场，可以辅助N漂移区3耗尽，使漂移区电场接近矩形分布，因此可以提高击穿电压，减小肖特基结的漏电。
(3)体二极管反向恢复特性
由于本发明所提供的积累型功率DMOS的寄生体二极管不是PN结，而是肖特基结，在体二极管正向导通时，漂移区不存在过剩的少数载流子，因此体二极管的反向恢复时间短，反向恢复特性好。
此外，由于本发明所提供的积累型功率DMOS不存在P型体区，也就不存在寄生双极型晶体管，故没有寄生双极型晶体管开启带来的一系列可靠性问题。
实施例2
如图2所示，本例的结构为在实施例1的基础上，在体内场板6和厚栅氧化层5底部，注入了P型埋层11，这样在器件反向阻断时，P型埋层11和N漂移区3形成横向电场，进一步的增加了器件的击穿电压。
实施例3
如图3所示，本例的结构为在实施例1的基础上，没有在栅电极4下做厚氧化层，虽然这样器件的Cgd增加，但是电流路径得到了拓宽，有利于降低导通电阻。
实施例4
如图4所示，本例的结构为在实施例1的基础上，增加了栅电极4的长度。这样在N漂移区也形成电子积累层，增加了器件导通时漂移区电子的浓度，使器件的导通电阻降低。
制作器件时，还可用碳化硅、砷化镓或锗硅等半导体材料替代硅。
Claims (2)
1.一种积累型功率DMOS，包括从下至上依次层叠设置的金属化漏极(1)、N+衬底(2)、N漂移区(3)和金属化源极(10)；所述N漂移区(3)上层具有N-型轻掺杂区(8)；所述N-型轻掺杂区(8)正上方具有N+重掺杂区(9)；所述N+重掺杂区(9)的上表面与金属化源极(10)接触；所述N漂移区(3)内部还具有第一沟槽和第二沟槽；所述第一沟槽沿N+重掺杂区(9)上表面中部垂直向下依次贯穿N+重掺杂区(9)和N-型轻掺杂区(8)后延伸入N漂移区(3)中；所述第二沟槽位于第一沟槽两侧，第二沟槽沿N+重掺杂区(9)上表面垂直向下依次贯穿N+重掺杂区(9)和N-型轻掺杂区(8)后延伸入N漂移区(3)中；所述第一沟槽中具有多晶硅栅电极(4)和厚氧化层(51)，所述多晶硅栅电极(4)位于厚氧化层(51)的正上方，所述多晶硅栅电极(4)两侧具有栅氧化层(53)，所述多晶硅栅电极(4)正上方具有隔离氧化层(54)；所述第二沟槽的上部填充金属(7)，所述金属(7)的顶部与金属化源极(10)直接接触，所述金属(7)的正下方具有多晶硅场板(6)和氧化层(52)，所述多晶硅场板(6)的侧面及底部被氧化层(52)包围；所述金属(7)与N-型轻掺杂区(8)形成肖特基接触，金属(7)与N+重掺杂区(9)形成欧姆接触；所述N-型轻掺杂区(8)的宽度等于或小于金属(7)与N-型轻掺杂区(8)形成的肖特基结在不加偏置时的势垒区宽度；所述N-型轻掺杂区(8)下表面的深度大于金属(7)的下表面的深度，N-型轻掺杂区(8)下表面的深度小于多晶硅栅电极(4)下表面的深度；
所述氧化层(5)为二氧化硅或者二氧化硅和氮化硅的复合材料；在氧化层(52)和厚栅氧化层(51)下方，注入了P型埋层(11)。
2.根据权利要求1所述的一种积累型功率DMOS，其特征在于，所述多晶硅栅电极(4)的下表面延长到与多晶硅场板(6)下表面平齐。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610705710.3A CN106206738B (zh) | 2016-08-22 | 2016-08-22 | 一种积累型功率dmos器件 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610705710.3A CN106206738B (zh) | 2016-08-22 | 2016-08-22 | 一种积累型功率dmos器件 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106206738A CN106206738A (zh) | 2016-12-07 |
| CN106206738B true CN106206738B (zh) | 2019-09-27 |
Family
ID=57524194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610705710.3A Expired - Fee Related CN106206738B (zh) | 2016-08-22 | 2016-08-22 | 一种积累型功率dmos器件 |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106206738B (zh) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109103259A (zh) * | 2018-08-21 | 2018-12-28 | 电子科技大学 | 一种积累型dmos器件 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101185169A (zh) * | 2005-04-06 | 2008-05-21 | 飞兆半导体公司 | 沟栅场效应晶体管及其形成方法 |
| CN102007584A (zh) * | 2008-02-14 | 2011-04-06 | 马克斯半导体股份有限公司 | 半导体装置结构及其相关工艺 |
| CN103441148A (zh) * | 2013-08-13 | 2013-12-11 | 电子科技大学 | 一种集成肖特基二极管的槽栅vdmos器件 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101375035B1 (ko) * | 2006-09-27 | 2014-03-14 | 맥스파워 세미컨덕터 인크. | Ｍｏｓｆｅｔ 및 그 제조 방법 |
-
2016
- 2016-08-22 CN CN201610705710.3A patent/CN106206738B/zh not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101185169A (zh) * | 2005-04-06 | 2008-05-21 | 飞兆半导体公司 | 沟栅场效应晶体管及其形成方法 |
| CN102007584A (zh) * | 2008-02-14 | 2011-04-06 | 马克斯半导体股份有限公司 | 半导体装置结构及其相关工艺 |
| CN103441148A (zh) * | 2013-08-13 | 2013-12-11 | 电子科技大学 | 一种集成肖特基二极管的槽栅vdmos器件 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106206738A (zh) | 2016-12-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104201206B (zh) | 一种横向soi功率ldmos器件 | |
| CN110148629B (zh) | 一种沟槽型碳化硅mosfet器件及其制备方法 | |
| CN106067480B (zh) | 一种双通道rc-ligbt器件及其制备方法 | |
| CN108198851A (zh) | 一种具有增强载流子存储效应的超结igbt | |
| CN108389902B (zh) | 一种含有背面槽栅的逆导型igbt | |
| CN103794647B (zh) | 一种双向igbt器件及其制作方法 | |
| US11211485B2 (en) | Trench power transistor | |
| CN109904155B (zh) | 一种集成高速反向续流二极管的碳化硅mosfet器件 | |
| CN108899370A (zh) | 集成电阻区的vdmos器件 | |
| CN108511528A (zh) | 具有深漏区的横向双扩散金属氧化物复合半导体场效应管及其制作方法 | |
| CN106057868A (zh) | 一种纵向超结增强型mis hemt器件 | |
| WO2019085850A1 (zh) | Igbt功率器件 | |
| CN113471290B (zh) | 隧穿辅助导通的硅/碳化硅异质结mosfet功率器件 | |
| CN110400840A (zh) | 一种抑制电压回折现象的rc-ligbt器件 | |
| CN112420694A (zh) | 集成反向肖特基续流二极管的可逆导碳化硅jfet功率器件 | |
| CN109166923B (zh) | 一种屏蔽栅mosfet | |
| CN109860303A (zh) | 一种积累型沟道的绝缘栅功率器件 | |
| CN109103240A (zh) | 一种低导通功耗绝缘体上硅横向绝缘栅双极型晶体管 | |
| CN109103259A (zh) | 一种积累型dmos器件 | |
| CN106098764B (zh) | 一种双通道rc-ligbt器件及其制备方法 | |
| CN109755310A (zh) | 一种分栅结构的功率晶体管 | |
| CN102194864B (zh) | 一种具有体电极的沟槽栅型绝缘栅双极型晶体管 | |
| CN110164975A (zh) | 一种积累型碳化硅功率mosfet器件 | |
| CN113948578A (zh) | 一种集成了mps二极管的碳化硅mosfet | |
| CN103441151B (zh) | 一种低正向压降的二极管 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20190927 |