CN113517331A - 一种具有浮岛耦合垂直场板保护的SiC基槽栅MOSFET结构 - Google Patents
一种具有浮岛耦合垂直场板保护的SiC基槽栅MOSFET结构 Download PDFInfo
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Abstract
一种具有浮岛耦合垂直场板保护的SiC基槽栅MOSFET结构涉及功率半导体器件技术领域，在普通MOSFET结构基础上设置了深槽，深槽外边到栅槽内边间距均匀相等且控制在1‑3微米之间，深槽深度比栅槽深2‑10微米且与浅槽平行相似，相邻深槽间距设置在2.5‑5微米，深槽内填充的多晶硅与源电极相连，在器件阻断态时，起垂直偏置场板作用，可以有效降低栅槽角隅处的电场强度，改善栅可靠性，同时在深槽下方包裹一掺杂类型与漂移区相反的掺杂浮岛，一方面来屏蔽指向深槽氧化层的电场线，保护深槽角隅，另一方面也可以通过承担一部分压降改善耗尽区电场分布保护槽栅角隅，提高器件可靠性。第一导电类型碳化硅半导体漂移区掺杂浓度控制在1‑5×1016cm‑3厚度在8‑10微米范围内厚度与深槽深度相同。
Description
技术领域
本发明涉及功率半导体器件技术领域，尤其涉及一种功率半导体器件
背景技术
随着社会的发展，各种电子设备的更新换代，对槽栅碳化硅功率器件等功率半导体器件的性能指标要求越来越高，功率器件大多数工作在大功率场景，随着性能的提升，器件的可靠性问题便显得尤为重要，为了提高槽栅功率器件工作时的可靠性和稳定性，就需要对这些器件进行技术更新。
相比于槽栅MOSFET,传统的VDMOSFET在元胞间距小于10um时,击穿电压以15％的比例上升,并且由于其本身固有的寄生JFET效应限制了导通电阻的进一步降低。为进一步降低功率MOSFET的导通电阻Ron,D.Ueda于1985年提出了槽栅MOSFET结构。该结构与前者相比有许多性能优点。如更低的导通电阻,低栅漏电荷密度。随着SiC等宽禁带半导体的应用，相比于硅基器件，SiC材料拥有着卓越的耐压性能，可以使器件工作很高的电压之下，然而在SiC槽栅MOSFET器件中，当器件处在阻断态，由于曲率效应的影响导致槽栅角隅处的电场非常集中，很容易使栅氧化层击穿，降低器件工作时的可靠性和稳定性。
为了解决这个问题，一种沟底部具有P屏蔽区的沟结构被J.Tan等人提出，但这导致Ron的明显增加。因此一种源沟下具有P型区域的双沟结构(DT-MOS)被提出来用以改善槽栅底部附近的电场分布。尽管有显著的屏蔽效应，但槽栅角隅附近的峰值电场仍然很难降低到4MV/厘米以下。之后Q.Song等人又提出了一种L形栅(LSG-MOS)的沟槽器件结构，以降低槽栅角隅处的电场，这又不能对沟槽底部中部处的电场进行有效屏蔽。
发明内容
本发明的目的在于提出一种新的MOSFET结构，使用这种结构，在不增加器件制备难度的基础上，可以改善栅可靠性。
本发明主要通过浮岛耦合深槽结构群的设计，利用浮岛和垂直偏置场板共同作用以此对电场进行改善，降低栅槽角隅处的电场强度。
为解决上述技术问题，本发明提供以下技术方案：
新型SiC基槽栅MOSFET结构特征在于：增设了槽栅网络包围的浮岛耦合深槽结构群，栅槽周侧均设置了浮岛耦合深槽结构，所述浮岛耦合垂直场板结构自下而上包括第二导电类型浮岛(101)，深槽绝缘介质层(104)和深槽多晶硅(105)，金属化电极。深槽下方包裹一掺杂类型与漂移区相反的掺杂浮岛，深槽外边到栅槽内边间距(109)均匀相等且控制在1-3微米之间，深槽深度比栅槽(205)深2-10微米且与浅槽平行相似，相邻深槽间距设置在2.5-5微米，深槽内填充的多晶硅与源电极相连。
深槽经过热氧化和化学气相沉积，形成厚度为0.2微米至1微米的二氧化硅介质层；通过常规工艺形成掺杂多晶硅(105)，掺杂多晶硅(105)与源电极相连，形成垂直场板；第二导电类型浮岛(101)通过离子注入耦合到深槽下面。所述外延层分两层，第一导电类型碳化硅漂移外延层(102)掺杂浓度控制在1-5×1016cm-3厚度与深槽深度相同。第一导电类型碳化硅耐压外延层(103)掺杂浓度和厚度与阻断电压有关，对于1200V耐压要求掺杂浓度在1-2×1016cm-3范围内，厚度在8-10微米范围内。第一导电类型碳化硅耐压外延层(103)和第一导电类型碳化硅漂移外延层(102)的总厚度为15-17微米.第二导电类型浮岛(101)掺杂浓度控制3×1017cm-3到3×1019cm-3范围内。
进一步,对于P型沟道碳化硅槽栅mosfet器件,所述第一导电类型碳化硅半导体的掺杂类型为P型时,第二导电类型碳化硅半导体的掺杂类型为N型；
对于N型沟道碳化硅槽栅mosfet器件,所述第一导电类型宽禁带半导体的掺杂类型为N型时,第二导电类型宽禁带半导体的掺杂类型为P型。
本发明采用栅槽网络包围浮岛耦合垂直场板结构方案，不仅适用于矩形元胞，也适用于圆形、椭圆形等多种形状的元胞结构。
本发明的有益效果为本发明在槽栅周侧引入浮岛耦合垂直场板结构，通过深槽和浮岛的共同作用来改变第一类导电类型碳化硅漂移区的耗尽区，从而改善槽栅角隅处发生的电场聚集效应,改善电场分布以此保护栅极角隅。并通过在第一导电类型碳化硅漂移区中引入第二导电类型浮岛结构,屏蔽指向深槽氧化层的电场线，提高器件的可靠性，从而提高进一步碳化硅槽栅mosfet器件的可靠性.
附图说明
图1为本发明的三维截面结构示意图。
图中：101——浮岛；102——第一导电类型碳化硅外延层；103——第一导电类型碳化硅外延层；104——深槽绝缘介质层；105——深槽多晶硅；106——第二导电类型碳化硅体区；107——第二导电类型碳化硅源接触区；108——重掺杂第一导电类型碳化硅衬底；203——第一导电类型碳化硅源接触区；204——深槽绝缘介质层；205——浅槽多晶硅；
具体实施方式
为了使本发明的目的与优点更加清晰突出,下面结合具体附图和实施例对本发明作进一步说明。此处所描述的具体实施例仅用于解释本发明,并不用于限定本发明。
本实施例是一款具有垂直场板保护的1200V碳化硅基槽栅MOSFET。本发明与普通槽栅MOSFET结构最大的区别是增加了浮岛耦合垂直场板结构其他与常规槽栅MOSFET器件结构相同，见附图1。自下而上依次为漏极金属化电极层，重掺杂第一导电类型碳化硅衬底(108)，其具体参数为具有约400微米的厚度和约1019cm-3的掺杂浓度；与衬底层邻接的是第一导电类型碳化硅耐压外延层(103)，它的厚度厚度约为8微米或者10微米，掺杂浓度为1×1016cm-3。邻接第一导电类型碳化硅耐压外延层(103)的是具有浮岛耦合垂直场板群和槽栅MOS结构的第一导电类型碳化硅漂移外延层(102)，该外延层的掺杂浓度为5×1016cm-3，厚度为7微米，厚度与深槽深度相同，深槽形貌与元胞相同为正方形，正方形边长2.5微米。通过离子注入在垂直场板下方形成第二导电类型浮岛(101)，第二导电类型浮岛(101)的掺杂浓度为3×1017cm-3。通过热氧化生成500埃氧化层，之后再通过化学气相沉积工艺，形成一层总厚度为1微米的二氧化硅介质层。掺杂多晶填充按常规工艺制备。碳化硅表面槽栅MOS结构由第二导电类型碳化硅体区(106)，第一导电类型碳化硅源接触区(203)，第二导电类型碳化硅源接触区(107)，浅槽多晶硅(205)，浅槽绝缘介质层(204)组成，浅槽与深槽同轴并且形状相似也为矩形，深槽外边-栅槽内边间距(109)均匀相等，为1.5微米。深槽内掺杂多晶与源电极相连，构成垂直场板。栅槽网络结构为厚度为700埃的绝缘栅介质层(104)、浅槽多晶硅(105)，按常规槽栅工艺制备。浅槽多晶网络，在栅焊盘处通过栅极金属引出电极。
本实施例的实现方法与常规槽栅MOSFET制备技术基本相同，包括衬底外延(1次两层)、深槽光刻与刻蚀、牺牲氧化1、牺牲氧化层去除、深槽氧化、深槽二氧化硅沉积、深槽多晶淀积，栅槽光刻与刻蚀、牺牲氧化2、牺牲氧化层2去除、栅氧化、多晶填充与回刻、p型体区注入与扩散、N型源区注入与扩散、隔离氧沉积、引线孔光刻与刻蚀、溅射源极金属、金属反刻、沉积钝化层、刻压焊盘背面金属溅射、合金等。
按照该工艺制备的样品，在漏极加压1000V，栅极加压15V的条件下，开关冲击2500次，器件正常，阈值电压和栅漏电流无明显退化，槽栅角隅和深槽角隅未出现损毁。
本具体实施例的原理在于槽栅周侧引入浮岛耦合垂直场板结构，通过深槽和浮岛的共同作用来改变第一类导电类型碳化硅漂移区的耗尽区，从而改善槽栅角隅处发生的电场聚集效应,改善电场分布以此保护栅极角隅。并通过在第一导电类型碳化硅漂移区中引入第二导电类型浮岛结构,屏蔽指向深槽氧化层的电场线，提高器件的可靠性，从而提高进一步碳化硅槽栅MOSFET器件的可靠性.
虽然本发明公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所述技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，本发明的保护范围并不局限于文中公开的特定实施例，而是包括落入权利要求范围内的所有技术方案。
Claims (2)
1.一种具有浮岛耦合垂直场板保护的SiC基槽栅MOSFET结构，其特征在于包括：浅槽多晶硅(205)，浅槽绝缘介质层(204)，深槽多晶硅(105)，深槽绝缘介质层(104)，第二导电类型浮岛(101)，第一导电类型碳化硅漂移外延层(102)，第一导电类型碳化硅耐压外延层(103)，重掺杂第一导电类型碳化硅衬底(108)，第二导电类型碳化硅体区(106)，第一导电类型碳化硅源接触区(203)，第二导电类型碳化硅源接触区(107)；新型SiC基槽栅MOSFET结构特征在于：栅槽周侧均设置了浮岛耦合垂直场板结构，所述浮岛耦合垂直场板结构自下而上包括第二导电类型浮岛(101)，深槽绝缘介质层(104)和深槽多晶硅(105)，金属化电极；深槽下方包裹一掺杂类型与漂移区相反的掺杂浮岛，深槽外边到栅槽内边间距(109)均匀相等且控制在1-3微米之间，深槽深度比栅槽205深2-10微米且与浅槽平行相似，相邻深槽间距设置在2.5-5微米，深槽内填充的多晶硅与源电极相连；
深槽经过热氧化和化学气相沉积，形成厚度为0.2微米至1微米的二氧化硅介质层；通过常规工艺形成掺杂多晶硅(105)，掺杂多晶硅(105)与源电极相连，形成垂直场板；第二导电类型浮岛(101)通过离子注入耦合到深槽下面；第一导电类型碳化硅漂移外延层(102)掺杂浓度控制在1-5×1016cm-3厚度与深槽深度相同；第一导电类型碳化硅耐压外延层(103)掺杂浓度和厚度与阻断电压有关，对于1200V耐压要求掺杂浓度在1-2×1016cm-3范围内，厚度在8-10微米范围内；第一导电类型碳化硅漂移外延层(102)和第一导电类型碳化硅耐压外延层(103)的总厚度为15-17微米；第二导电类型浮岛(101)掺杂浓度控制在3×1017cm-3到3×1019cm-3范围内。
2.根据权利要求1所述的一种具有浮岛耦合垂直场板保护的SiC基槽栅MOSFET结构，其特征在于：对于P型沟道碳化硅槽栅MOSFET器件,所述第一导电类型碳化硅半导体的掺杂类型为P型时,第二导电类型碳化硅半导体的掺杂类型为N型；
对于N型沟道碳化硅槽栅MOSFET器件,所述第一导电类型碳化硅半导体的掺杂类型为N型时,第二导电类型碳化硅半导体的掺杂类型为P型。
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