CN102148159B - 自对准电荷平衡的功率双扩散金属氧化物半导体制备方法 - Google Patents

自对准电荷平衡的功率双扩散金属氧化物半导体制备方法 Download PDF

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CN102148159B
CN102148159B CN201010620244.1A CN201010620244A CN102148159B CN 102148159 B CN102148159 B CN 102148159B CN 201010620244 A CN201010620244 A CN 201010620244A CN 102148159 B CN102148159 B CN 102148159B
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planar gate
semiconductor substrate
insulating barrier
substrate
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CN102148159A (zh
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陈军
李亦衡
管灵鹏
何佩天
马国荣
安荷·叭剌
哈姆扎·依玛兹
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

本发明提出了自对准电荷平衡的半导体器件以及制备这种器件的方法。一个或多个平面栅极形成在第一导电类型的半导体衬底上方。刻蚀半导体中的一个或多个深沟槽，自对准到平面栅极。用第二导电类型的半导体材料填充沟槽，使深沟槽与半导体衬底的邻近区域达到电荷平衡。该工艺可以制备单元间距小于12微米的自对准电荷平衡的器件。

Description

自对准电荷平衡的功率双扩散金属氧化物半导体制备方法
技术领域
本发明主要涉及金属氧化物半导体场效应管(MOSFETs)，更确切地说，是一种自对准电荷平衡的功率双扩散金属氧化物半导体场效应管(DMOSFET)的制备方法。
背景技术
功率MOSFETs典型应用于需要功率转换和功率放大的器件中。对于功率转换器件来说，市场上可买到的代表性的器件就是双扩散MOSFETs(DMOSFETs)。在一个典型的晶体管中，大部分的击穿电压BV都由漂流区承载，为了提供较高的击穿电压BV，漂流区要低掺杂。然而，低掺杂的漂流区会产生高导通电阻Rds-on。对于一个典型的晶体管而言，Rds-on与BV2.5成正比。因此，对于传统的晶体管，随着击穿电压BV的增加，Rds-on也急剧增大。
超级结是一种众所周知的半导体器件。超级结晶体管提供了一种可以在维持很高的断开状态击穿电压(BV)的同时，获得很低的导通电阻(Rds-on)的方法。超级结器件含有形成在漂流区中的交替的P-型和N-型掺杂立柱。在MOSFET的断开状态时，在相对很低的电压下，立柱就完全耗尽，从而能够维持很高的击穿电压(立柱横向耗尽，因此整个p和n立柱耗尽)。对于超级结，导通电阻Rds-on的增加与击穿电压BV成正比，比传统的半导体结构增加得更加缓慢。因此，对于相同的高击穿电压(BV)，超级结器件比传统的MOSFET器件具有更低的Rds-on(或者，相反地，对于特定的Rds-on，超级结器件比传统的MOSFET具有更高的BV)。
美国专利号为4,754,310的专利提出了一种用于二极管或晶体管的半导体器件，包含一个具有耗尽层的半导体本体，例如通过反向偏压整流结，耗尽层形成在至少器件的高电压运作模式下的整个部分中。耗尽的本体部分含有一个交错导电类型的第一和第二区的交错式结构，能够承载整个耗尽的本体部分上的高电压。设置每个第一和第二区的厚度和掺杂浓度，使得形成在每个区域中单位面积上所消耗的空间电荷达到平衡，至少使由任何不平衡所产生的电场都小于临界电场强度。在达到临界电场强度时会在本体部分中发生雪崩击穿。至少一个运作模式下的第一区，可提供穿过本体部分的并联电流通路。
美国专利号为6,818,513的专利，Marchant提出了一种超级结沟槽栅极场效应管器件的制备方法。图1A表示Marchant的超级结沟槽栅极场效应管器件的剖面图。在Marchant方法中，具有第二导电类型的阱区形成在半导体衬底29中，半导体衬底29具有主表面、N-外延部分32以及漏极区31，并且半导体衬底29由第一导电类型(例如N-型)制成。第一导电类型的源极区36形成在阱区中，沟槽栅极电极43形成在源极区附近。所形成的P-条纹沟槽35，从半导体衬底29的主表面开始，延伸到半导体衬底中，达到预设深度。第二导电类型(例如P-型)的半导体材料沉积在条纹沟槽35中。每个N+源极区36都在其中一个栅极结构45附近，并形成在多个P-阱区34中，P-阱区34也形成在半导体衬底29中。每个P-阱区34都沉积在其中一个栅极结构45附近。源极区36的接头41位于半导体衬底29的主表面28上。由于耗尽区32从相邻条纹35的侧面延伸，因此，条纹35之间的区域快速耗尽电荷载流子。图1B表示Marchant的另一种沟槽栅极超级结场效应管器件的侧剖面图。如图中所示，条纹35包含一个P-层35(a)和一个内层介电材料35(b)，可以通过氧化P-层35(a)或二氧化硅等材料或空气，制备内层介电材料。然而，Marchant的方法刻蚀和填充条纹沟槽的步骤繁多，增加了含有利用Marchant方法制成的超级结晶体管器件的成本。另外，条纹沟槽35不是自对准的，有源单元间距(即从器件沟槽到器件沟槽)也不能小于12μm至16μm。
正是在这一前提下，提出了本发明的各种实施例。
发明内容
本发明提供了一种自对准电荷平衡的功率DMOS的制备方法，允许较高的单元密度、较好的工艺控制，并且使用较少的光致抗蚀剂掩膜。所用的掩膜较少，可以降低制造成本。
为实现上述目的，本发明提供了一种自对准电荷平衡的功率DMOS的制备方法，该方法包含以下步骤：
a在第一导电类型的半导体衬底上方，制备一个或多个平面栅极；
b在半导体中刻蚀一个或多个深沟槽，自对准到平面栅极上；
c用第二导电类型的半导体材料填充所述的深沟槽，使深沟槽与半导体衬底的邻近区域达到电荷平衡。
一种依据上述的方法制备的自对准电荷平衡的半导体器件，其中相邻的器件沟槽之间的单元间距小于12微米。
一种自对准电荷平衡的半导体器件，该半导体器件包含：一个第一导电类型的半导体衬底，具有两个或多个器件单元形成在上面，其中每个单元都含有用第二导电类型的半导体插塞填充的自对准沟槽、形成在半导体衬底中最接近自对准沟槽的源极区和本体区、最接近源极区并与源极区电绝缘的平面栅极、位于栅极上方的一个或多个绝缘层，以及位于一个或多个绝缘层上方与半导体插塞电接触的一个导电层，其中半导体插塞的导电类型与半导体衬底的导电类型相反，并与半导体衬底的相邻部分达到电荷平衡，其中一个指定的一个或多个器件单元的沟槽，与其相邻的单元沟槽之间的间距小于12微米。
本发明自对准电荷平衡的功率DMOS的制备方法和现有技术相比，其优点在于，本发明获得的单元密度更大。因此，使用了超级结晶体管的器件，在提升器件性能的同时，还可以减少制备时间和成本。
附图说明
阅读以下详细说明并参照以下附图之后，本发明的其他特征和优势将显而易见：
图1A-1B表示原有技术的超级结场效应管器件的剖面图。
图2A-2M表示依据本发明的一个实施例，一种自对准电荷平衡的功率双扩散金属氧化物半导体场效应管(DMOSFET)的制备方法的剖面图。
图3表示依据本发明的一个实施例，一种超级结场效应管的剖面图。
具体实施方式
尽管为了进行阐释，以下详细说明包含了许多具体细节，但是本领域的任何技术人员都应理解基于以下细节的多种变化和修正都属本发明的范围。因此，本发明的典型实施例的提出，对于请求保护的发明没有任何一般性的损失，而且不附加任何限制。
在本发明的实施例中，超级结晶体管可以自对准的方式制备，允许较高的单元密度、较好的工艺控制，并且使用较少的光致抗蚀剂掩膜。所用的掩膜较少，可以降低制造成本。
图2A-2M表示依据本发明的一个实施例，制备超级结的一个示例。
如图2A所示，制备首先将半导体衬底202作为一种初始材料。半导体衬底202包含一个外延层，通过标准工艺生长、沉积或以其他方式，形成在较重掺杂的半导体底部衬底上，这仅作为示例，不作为局限。例如，半导体衬底202可以由硅(Si)材料制成。第一绝缘层204(例如一个氧化层)可以通过生长、沉积或以其他方式，形成在衬底202上方。第一绝缘层204的厚度约为至第二绝缘层206可以由硬掩膜材料制成，硬掩膜材料可以抵御刻蚀第一绝缘层204的刻蚀过程。例如，如果第一绝缘层204为一种氧化物(例如二氧化硅)，那么第二绝缘层206可以是一种氮化物(例如氮化硅)。第二绝缘层206的厚度约为至
例如通过光致抗蚀剂掩膜，可以形成第二绝缘层206的图案，以确定器件区201和终止区203。例如，如图2B所示，第一场掩膜(图中没有表示出)可以沉积在第二绝缘层206上方。终止区203处的第二绝缘层206的一部分，可以通过场掩膜刻蚀。与衬底202的掺杂物的导电类型相反的掺杂物，可以植入到终止区203中，以形成结终止延伸(JTE)区，一直到线L1。JTE是一种晶片终止结构的设计类型，通过将掺杂物植入到衬底中，形成一个从主器件区开始延伸到终止区内的P-N结，用于降低电场拥挤。然后，可以除去第一场掩膜。在JTE区上方的终止区203的上方，可以生长第三绝缘层208(例如一个场氧化层)。第三绝缘层208的厚度约为至
如图2C所示，可以除去器件区域201处的第二绝缘层206的剩余部分。可以将与衬底202中的掺杂物的导电类型相反的掺杂物掺杂到器件区域201中，进行全面的结型场效应管(JFET)植入，以便控制通道掺杂浓度及其导电性。还可选择，在衬底202的顶部进行本体植入。设计JFET植入和JTE植入的参数，使它们的深度和浓度可以分别调整。
如图2D所示，可以除去器件区域201处的第一绝缘层204的裸露部分，一直到衬底202的表面。然后，可以在器件区域201处的衬底202的裸露部分上方，生长一个栅极绝缘体210(例如栅极氧化物)。在栅极绝缘层210上方，沉积一个导电层，作为栅极电极212，在此也可称为栅极。作为示例，导电层可以是一层多晶硅。构成栅极212的导电材料的厚度约为至可以除去用于构成栅极212所选的那部分导电层，以使栅极212的顶面和第三绝缘层208的顶面一样高。第二场掩膜(图中没有表示出)可以在由绝缘层204、206、208、栅极绝缘体210和栅极212所构成的结构上方形成图案，这仅作为示例，不作为局限。还可选择，通过CMP(化学机械抛光)，使多晶硅平整到第三绝缘层208的顶面。通过场掩膜中的开口，刻蚀所选的那部分多晶硅，刻蚀结束后，可以除去场掩膜。
参见图2E，可以在第三绝缘层208和栅极212的上方沉积第四绝缘层214(例如一个氧化层)。然后在该结构上方，形成一个光致抗蚀剂掩膜(图中没有表示出)并形成图案。可以将所选的那部分第四绝缘层214、以及构成栅极212和栅极绝缘层210的导电层，一直向下刻蚀到半导体衬底202，以便形成第一开口216。还可以将第四绝缘层214、第三绝缘层208以及第一绝缘层204，刻蚀到半导体衬底202，以便形成第二开口218。第一开口216的深度可以很深，以便将衬底202的下表面裸露出来，这仅作为示例，不作为局限。刻蚀结束后，可以除去光致抗蚀剂掩膜。在这个阶段，例如通过开口216、218植入合适的掺杂离子，可以形成源极和本体区。然而，源极和本体区也可以在稍后的工艺中制备，例如参见下文所述的图2J。形成开口216、218之后，导电层212、栅极氧化物210以及绝缘层214的剩余部分，可以作为接下来深沟槽刻蚀的硬掩膜。导电层212的剩余部分，形成最终的功率器件的平面栅极。因此，平面栅极结构在接下来深沟槽刻蚀的过程中，起硬掩膜的作用。
形成开口216、218之后，可以选择氧化导电层212在开口216以内的裸露部分。如图2F所示，由耐腐蚀材料(例如氮化物)制成的薄绝缘层219，可以沉积或形成内衬在硬掩膜开口216和218的底部和侧壁上。薄绝缘层219的厚度约为这仅作为示例，不作为局限。如图2G所示，在由绝缘层204、208、214、栅极绝缘物210和导电层212以及薄绝缘层219所构成的结构上方，以及硬掩膜开口216和218的底部上的薄绝缘层219的水平部分，可以对其进行各向异性地刻蚀，以便利用在硬掩膜开口侧壁上的那部分薄绝缘层219，构成侧壁垫片220。如下所述，氧化栅极电极212的裸露部分，并形成侧壁垫片220，可以在刻蚀深沟槽以及在深沟槽中生长外延层时，保护栅极电极。
然后，将衬底202刻蚀到预设的深度，以便在对应硬掩膜开口216和218的地方，分别形成深沟槽222和224。因此，深沟槽222自对准到平面栅极212。沟槽的深度取决于器件的设计方式，最深可达到约100μm，这仅作为示例，不作为局限。对于制备硬掩膜开口216、218的刻蚀过程，刻蚀材料最好选用衬底材料，而不是构成侧壁垫片220或第四绝缘物214的材料。在刻蚀衬底202的过程中，侧壁垫片220为制备衬底的自对准提供补偿。更确切地说，侧壁垫片220为深沟槽222和栅极电极212之间提供补偿。由于自对准到平面栅极结构212，无需使用光致抗蚀剂掩膜，就可以在衬底中制备沟槽。另外，自对准获得的相邻单元之间的间距，比利用非自对准的掩膜，进行沟槽刻蚀时可能获得的间距更小。
形成沟槽222、224之后，如图2H所示，可以选择沉积、生长或形成半导体插塞226和228，填充沟槽222和224。通过选择性的外延生长，可以选用半导体插塞226、228形成在沟槽222或224中，这仅作为示例，不作为局限。例如，通过在氢气环境中退火，可以对该结构进行预调节。生长一个选择性的外延生长(SEG)层。该SEG层可以是硅(Si)。SEG层也可选用锗化硅SixGey，例如含有1-20％的Ge。生长SixGey的优势在于，其掺杂剂量可以比硅的掺杂剂量大十倍。例如，一般对于Si而言，掺杂浓度约为1018-1019cm-3，对于SixGey而言，掺杂浓度约为1020-1021cm-3。另外，Si和SixGey之间在侧壁处的晶格失配所带来的应变，实际上提高了电荷载流子的迁移率，例如可以高达50％。要注意的是，外延层仅仅生长在裸露的半导体材料上。因此，无需使用掩膜，半导体插塞226、228就可以选择性地形成在沟槽222、224中。叠加有第四绝缘层214的平面栅极212在SEG过程中，起硬掩膜的作用。氮化物侧壁220有助于阻止在平面栅极212的侧壁上进行外延生长。所形成的半导体插塞226、228的导电类型与衬底202的导电类型相反。如果半导体衬底202为第一导电类型，那么半导体插塞226、228就构成第二导电类型的立柱，适当地配置这些立柱的掺杂浓度和宽度，使它们都与半导体衬底202的相邻部分达到电荷平衡。这些立柱还自对准到平面栅极212上。
参见图2I，可以回刻硅插塞226和228，使它们与衬底202的表面在同一水平线上。然后除去垫片220。
如图2J所示，将覆盖着终止区的本体掩膜(图中没有表示出)使用在结构上方，然后通过本体植入，形成本体区230。植入是利用与衬底202呈一定倾斜角的掺杂离子植入进行的。衬底202应当倾斜，使其法线(即垂直于衬底表面所在平面的方向)与离子束方向之间的夹角约为10°-15°，这仅作为示例，不作为局限。尽管衬底202是倾斜的，但是在植入过程中，还可以旋转衬底202。植入后，除去本体掩膜。利用源极掩膜(图中没有表示出)阻挡终止区，并通过源极植入，形成源极区231。源极植入也可以垂直进行，也就是说沿垂直于半导体衬底202表面的离子植入的法线方向。源极植入后，除去源极掩膜。利用热扩散驱入所植入的离子。因此，源极和本体区也自对准到平面栅极212。
如图2K所示，将第五绝缘层232(例如一种氧化物)填充到开口216和218中，以及由绝缘层204、208、214、栅极绝缘物210、导电材料212和半导体插塞226、228所构成的结构上方。在第五绝缘层232的上方使用接触掩膜(图中没有表示出)，以制备本体接头。第五绝缘层232在沟槽216中的那部分，可以通过接触掩膜刻蚀，以形成接触开口234。接触开口234可以略微延伸到半导体插塞226的源极区231中。如图2L所示，通过接触开口234进行本体接触植入，以形成本体接头236，可以同本体区230形成良好的接触。金属238(例如钨)可以沉积在接触开口234中，以便接触源极231和本体接头236。如图2M所示，金属也可以形成在第五绝缘层232的上方，以完成平面栅极功率DMOS器件的制备。在平面栅极212上适当地加载电压时，会形成从源极区231穿过本体区230到达衬底202的导电通路。衬底202作为功率DMOS的漏极。金属层形成在衬底202的底部，作为漏极金属205。半导体衬底202靠近半导体插塞226、228的那部分，作为漏极漂流区，用于承载击穿电压。半导体插塞226、228同相邻的那部分衬底202达到电荷平衡，以便构成一个超级结区，从而在保持低导通电阻Rds的同时，提高器件的击穿电压。自对准结构使单元间距可以很小，从而获得更高的单元密度，进一步改善了Rds。
如图2A-2M所示的制备自对准电荷平衡的平面栅极功率DMOSFET的方法，可以制成单元间距(从器件沟槽到器件沟槽)为12微米或更小(例如8-12微米甚至小于8微米)的功率DMOS器件。
依据本发明的一个实施例，图2A-2M所示的上述制备过程，可用于制备自对准电荷平衡的半导体器件。图3表示具有两个或多个器件单元301A、301B和终止区303的电荷平衡器件300，这仅作为示例，不作为局限。器件单元301A、301B形成在半导体衬底302中。每个器件单元都含有一个用半导体插塞326填充的自对准沟槽。半导体插塞326的导电类型与衬底302的导电类型相反，并同周围的衬底302区域达到电荷平衡。源极区331和本体接头336形成在半导体衬底302中，最接近衬底的表面以及由插塞326填充的自对准沟槽，平面栅极312形成在衬底302上方，最接近源极区331。所形成的本体区330最接近源极区。本体接触区形成在绝缘层332中的开口下方，以便同本体区330形成良好的接触。栅极绝缘物310(例如栅极氧化物)，可以将栅极312同衬底302电绝缘，尤其是同源极区331和本体区330电绝缘。不同器件单元301A、301B的栅极312可以相互电连接。
如果器件单元301A、301B中含有半导体插塞326的沟槽，是利用上述自对准技术制成的，那么一个或多个器件单元301A、301B的单元间距P就可以小于12微米，例如8-12微米甚至小于8微米。
一个或多个绝缘层314、332覆盖着栅极312，并将栅极与位于绝缘层上方的导电层338(例如一个金属层)绝缘。导电层338可以与源极区331和每个器件的本体区330通过绝缘层314、332中的开口电接触，以及与半导体插塞326电接触。通过打开从源极区331到衬底302的平面栅极312下方的本体区330中的平面通道，在每个栅极312上加载电压，就可以控制从导电层338穿过衬底302到达形成在衬底背面的漏极电极305之间的电流。
器件300可以选择包含一个终止区303，具有自对准的沟槽，形成在衬底302中，并用与导电层338电绝缘的半导体插塞328填充。
综上所述，本发明的实施例允许超级结晶体管以自对准的方式形成，比原有技术的制备工艺所获得的单元密度更大。因此，使用了超级结晶体管的器件，在提升器件性能的同时，还可以减少制备时间和成本。
尽管本发明关于某些较佳的版本已经做了详细的叙述，但是仍可能存在其他版本。因此，本发明的范围不应由上述说明决定，与之相反，本发明的范围应参照所附的权利要求书及其全部等效内容。任何可选件(无论首选与否)，都可与其他任何可选件(无论首选与否)组合。在以下权利要求中，除非特别声明，否则不定冠词“一个”或“一种”都指下文内容中的一个或多个项目的数量。除非用“意思是”明确指出限定功能，否则所附的权利要求书并不应认为是意义和功能的局限。

Claims (11)

1.一种用于制备自对准电荷平衡的半导体器件的方法，其特征在于，该方法
包含：
a在第一导电类型的半导体衬底上方，制备一个或多个平面栅极；
b在半导体中刻蚀一个或多个深沟槽，自对准到平面栅极上；
c用第二导电类型的半导体材料填充所述的深沟槽，使深沟槽与半导体衬底的邻近区域达到电荷平衡；
其中步骤b包含：在平面栅极上方制备一个顶部栅极绝缘层，将平面栅极和顶部栅极绝缘层用作刻蚀深沟槽的硬掩膜；
其中步骤b还包含：在刻蚀一个或多个深沟槽之前，在平面栅极的一个或多个对应边处，形成一个或多个侧壁垫片；
还包含在平面栅极附近，半导体衬底的顶面处，进行源极和本体植入，其中在进行源极和本体植入之前，要先除去侧壁垫片。
2.如权利要求1所述的方法，其特征在于，其中衬底包含一个重掺杂的底层和一个相对轻掺杂的外延层，位于底层上方。
3.如权利要求1所述的方法，其特征在于，其中步骤c包含：通过选择性的外延生长SEG沟槽内的第二导电类型的半导体材料，将平面栅极和顶部栅极绝缘层用作硬掩膜，填充所述的深沟槽。
4.如权利要求1所述的方法，其特征在于，其中侧壁垫片由氮化物制成。
5.如权利要求1所述的方法，其特征在于，其中步骤c包含：通过沟槽内外延生长第二导电类型的半导体材料，填充所述的深沟槽。
6.如权利要求1所述的方法，其特征在于，其中所蚀刻进行的源极和本体植入，自对准到平面栅极上。
7.如权利要求1所述的方法，其特征在于，还包含在半导体器件上方，制备一个顶部绝缘层，在顶部绝缘层中刻蚀接触孔，这些接触孔向下延伸到半导体衬底的平面上。
8.如权利要求7所述的方法，其特征在于，还包含在器件上方制备一个源极金属，在半导体衬底的底部制备一个漏极金属。
9.如权利要求1所述的方法，其特征在于，其中步骤a包含：在半导体衬底的表面上制备一个或多个绝缘层，并在一个或多个绝缘层上制备一个或多个平面栅极，从而使平面栅极与半导体衬底电绝缘。
10.如权利要求9所述的方法，其特征在于，其中步骤b包含：通过一个或多个绝缘物制备一个或多个开口，以裸露衬底的表面；在一个或多个开口的一个或多个侧壁上制备一个或多个侧壁垫片；并且利用无掩膜刻蚀工艺，刻蚀衬底，以自对准的方式形成一个或多个沟槽，其中一个或多个侧壁垫片可以抵抗刻蚀过程的侵袭。
11.依据权利要求1所述的方法制备的自对准电荷平衡的半导体器件，其特征在于，其中相邻的器件沟槽之间的单元间距小于12微米。
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