TWI412071B - 自對準電荷平衡的功率雙擴散金屬氧化物半導體製備方法 - Google Patents

自對準電荷平衡的功率雙擴散金屬氧化物半導體製備方法 Download PDF

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TWI412071B
TWI412071B TW099144886A TW99144886A TWI412071B TW I412071 B TWI412071 B TW I412071B TW 099144886 A TW099144886 A TW 099144886A TW 99144886 A TW99144886 A TW 99144886A TW I412071 B TWI412071 B TW I412071B
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TW201123278A (en
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John Chen
Yeeheng Lee
Lingpeng Guan
Moses Ho
Wilson Ma
Anup Bhalla
Hamza Yilmaz
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Alpha & Omega Semiconductor
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Description

自對準電荷平衡的功率雙擴散金屬氧化物半導體製備方法
本發明是有關於一種金屬氧化物半導體場效電晶體(MOSFETs)，特別是有關於一種自對準電荷平衡的功率雙擴散金屬氧化物半導體場效電晶體(DMOSFET)之製備方法。
功率MOSFETs典型應用於需要功率轉換和功率放大的元件中。對於功率轉換元件來說，市場上可買到的代表性的元件就是雙擴散MOSFETs(DMOSFETs)。在一個典型的電晶體中，大部分的擊穿電壓BV都由漂流區承載，為了提供較高的擊穿電壓BV，漂流區要低摻雜。然而，低摻雜的漂流區會產生高導通電阻Rds-on。對於一個典型的電晶體而言，Rds-on與BV2.5成正比。因此，對於傳統的電晶體，隨著擊穿電壓BV的增加，Rds-on也急劇增大。
超接面是一種眾所周知的半導體元件。超接面電晶體提供了一種可以在維持很高的斷開狀態擊穿電壓(BV)的同時，獲得很低的導通電阻(Rds-on)的方法。超接面元件含有形成在漂流區中的交替的P-型和N-型摻雜立柱。在MOSFET的斷開狀態時，在相對很低的電壓下，立柱就完全耗盡，從而能夠維持很高的擊穿電壓( 立柱橫向耗盡，因此整個p和n立柱耗盡)。對於超接面，導通電阻Rds-on的增加與擊穿電壓BV成正比，比傳統的半導體結構增加得更加緩慢。因此，對於相同的高擊穿電壓(BV)，超接面元件比傳統的MOSFET元件具有更低的Rds-on(或者，相反地，對於特定的Rds-on，超接面元件比傳統的MOSFET具有更高的BV)。
美國專利號為4,754,310的專利提出了一種用於二極體或電晶體的半導體元件，包含一個具有耗盡層的半導體本體，例如藉由反向偏壓整流結，耗盡層形成在至少元件的高電壓運作模式下的整個部分中。耗盡的本體部分含有一個交錯導電類型的第一和第二區的交錯式結構，能夠承載整個耗盡的本體部分上的高電壓。設置每個第一和第二區的厚度和摻雜濃度，使得形成在每個區域中單位面積上所消耗的空間電荷達到平衡，至少使由任何不平衡所產生的電場都小於臨界電場強度。在達到臨界電場強度時會在本體部分中發生雪崩擊穿。至少一個運作模式下的第一區，可提供穿過本體部分的並聯電流通路。
美國專利號為6,818,513的專利，Marchant提出了一種超接面溝槽閘極場效電晶體元件的製備方法。第1A圖表示Marchant的超接面溝槽閘極場效電晶體元件的剖面圖。在Marchant方法中，具有第二導電類型的阱區形成在半導體基體29中，半導體基體29具有主表面、N-外延部分32以及汲極區31，並且半導體基體29由第一導電類型(例如N-型)製成。第一導電類型的源極區36形成在阱區中，溝槽閘極電極43形成在源極區附近。所形成的P-條紋溝槽35，從半導體基體29的主表面開始，延伸到半導體基體中，達到 預設深度。第二導電類型(例如P-型)的半導體材料沉積在條紋溝槽35中。每個N+源極區36都在其中一個閘極結構45附近，並形成在多個P-阱區34中，P-阱區34也形成在半導體基體29中。每個P-阱區34都沉積在其中一個閘極結構45附近。源極區36的接頭41位於半導體基體29的主表面28上。由於耗盡區32從相鄰條紋35的側面延伸，因此，條紋35之間的區域快速耗盡電荷載流子。第1B圖表示Marchant的另一種溝槽閘極超接面場效電晶體元件的側剖面圖。如圖中所示，條紋35包含一個P-層35(a)和一個內層介電材料35(b)，可以藉由氧化P-層35(a)或二氧化矽等材料或空氣，製備內層介電材料。然而，Marchant的方法刻蝕和填充條紋溝槽的步驟繁多，增加了含有利用Marchant方法製成的超接面電晶體元件的成本。另外，條紋溝槽35不是自對準的，有源單元間距(即從元件溝槽到元件溝槽)也不能小於12 m至16 m。
正是在這一前提下，提出了本發明的各種實施例。
本發明提供了一種自對準電荷平衡的功率DMOS的製備方法，允許較高的單元密度、較好的技術控制，並且使用較少的光致抗蝕劑掩膜。所用的掩膜較少，可以降低製造成本。
為實現上述目的，本發明提供了一種自對準電荷平衡的功率DMOS的製備方法，該方法包含以下步驟：a 在第一導電類型的半導體基體上方，製備一個或多個平面閘極； b 在半導體中刻蝕一個或多個深溝槽，自對準到平面閘極上；c 用第二導電類型的半導體材料填充深溝槽，使深溝槽與半導體基體的鄰近區域達到電荷平衡。
一種依據上述的方法製備的自對準電荷平衡的半導體元件，其中相鄰的元件溝槽之間的單元間距小於12微米。
一種自對準電荷平衡的半導體元件，該半導體元件包含：一個第一導電類型的半導體基體，具有兩個或多個元件單元形成在上面，其中每個單元都含有用第二導電類型的半導體插塞填充的自對準溝槽、形成在半導體基體中最接近自對準溝槽的源極區和本體區、最接近源極區並與源極區電絕緣的平面閘極、位於閘極上方的一個或多個絕緣層，以及位於一個或多個絕緣層上方與半導體插塞電接觸的一個導電層，其中半導體插塞的導電類型與半導體基體的導電類型相反，並與半導體基體的相鄰部分達到電荷平衡，其中一個指定的一個或多個元件單元的溝槽，與其相鄰的單元溝槽之間的間距小於12微米。
本發明自對準電荷平衡的功率DMOS的製備方法和現有技術相比，其優點在於，本發明獲得的單元密度更大。因此，使用了超接面電晶體的元件，在提升元件性能的同時，還可以減少製備時間和成本。
28‧‧‧主表面
29、202‧‧‧半導體基體
31‧‧‧汲極區
32‧‧‧N-外延部分
34‧‧‧P-阱區
35‧‧‧P-條紋溝槽
43‧‧‧溝槽閘極電極
45‧‧‧閘極結構
41‧‧‧接頭
32‧‧‧耗盡區
35‧‧‧條紋
35(a)‧‧‧P-層
35(b)‧‧‧內層介電材料
36、231、331‧‧‧源極區
201‧‧‧元件區域
203、303‧‧‧終止區
204‧‧‧第一絕緣層
205‧‧‧汲極金屬
206‧‧‧第二絕緣層
208‧‧‧第三絕緣層
210‧‧‧閘極絕緣體
212‧‧‧閘極電極
214‧‧‧第四絕緣層
216‧‧‧第一開口
218‧‧‧第二開口
219‧‧‧薄絕緣層
220‧‧‧側壁墊片
222、224‧‧‧深溝槽
226、228、326、328‧‧‧半導體插塞
230、330‧‧‧本體區
232‧‧‧第五絕緣層
234‧‧‧接觸開口
236、336‧‧‧本體接頭
238‧‧‧金屬
300‧‧‧電荷平衡元件
301A、301B‧‧‧元件單元
302‧‧‧基體
305‧‧‧汲極電極
310‧‧‧閘極絕緣物
312‧‧‧平面閘極
314、332‧‧‧絕緣層
338‧‧‧導電層
L1‧‧‧線
第1A圖至第1B圖 表示習知技術的超接面場效電晶體元件的剖面圖； 第2A圖至第2M圖 表示依據本發明的一個實施例，一種自對準電荷平衡的功率雙擴散金屬氧化物半導體場效電晶體(DMOSFET)的製備方法的剖面圖；以及第3圖 表示依據本發明的一個實施例，一種超接面場效電晶體的剖面圖。
儘管為了進行闡釋，以下詳細說明包含了許多具體細節，但是本領域的任何技術人員都應理解基於以下細節的多種變化和修正都屬本發明的範圍。因此，本發明的典型實施例的提出，對於請求保護的發明沒有任何一般性的損失，而且不附加任何限制。
在本發明的實施例中，超接面電晶體可以自對準的方式製備，允許較高的單元密度、較好的技術控制，並且使用較少的光致抗蝕劑掩膜。所用的掩膜較少，可以降低製造成本。
第2A圖至第2M圖表示依據本發明的一個實施例，製備超接面的一個示例。
參閱第2A圖所示，製備首先將半導體基體202作為一種初始材料。半導體基體202包含一個磊晶層，藉由標準技術生長、沉積或以其他方式，形成在較重摻雜的半導體底部基體上，這僅作為示例，不作為侷限。例如，半導體基體202可以由矽(Si)材料製成。第一絕緣層204(例如一個氧化層)可以藉由生長、沉積或以其他方式，形成在基體202上方。第一絕緣層204的厚度約為100 Å至500 Å。第二絕緣層206可以由硬掩膜材料製成，硬掩膜材料可以抵禦刻蝕第一絕緣層204的刻蝕過程。例如，如果第一 絕緣層204為一種氧化物(例如二氧化矽)，那麼第二絕緣層206可以是一種氮化物(例如氮化矽)。第二絕緣層206的厚度約為1000 Å至3000 Å。
例如藉由光致抗蝕劑掩膜，可以形成第二絕緣層206的圖案，以確定元件區201和終止區203。例如，參閱第2B圖所示，第一場掩膜(圖中沒有表示出)可以沉積在第二絕緣層206上方。終止區203處的第二絕緣層206的一部分，可以藉由場掩膜刻蝕。與基體202的摻雜物的導電類型相反的摻雜物，可以植入到終止區203中，以形成接面終止延伸(JTE)區，一直到線L1。JTE是一種晶片終止結構的設計類型，藉由將摻雜物植入到基體中，形成一個從主元件區開始延伸到終止區內的P-N結，用於降低電場擁擠。然後，可以除去第一場掩膜。在JTE區上方的終止區203的上方，可以生長第三絕緣層208(例如一個場氧化層)。第三絕緣層208的厚度約為3000 Å至6000 Å。
參閱第2C圖所示，可以除去元件區域201處的第二絕緣層206的剩餘部分。可以將與基體202中的摻雜物的導電類型相反的摻雜物摻雜到元件區域201中，進行全面的接面型場效電晶體(JFET)植入，以便控制通道摻雜濃度及其導電性。還可選擇，在基體202的頂部進行本體植入。設計JFET植入和JTE植入的參數，使它們的深度和濃度可以分別調整。
參閱第2D圖所示，可以除去元件區域201處的第一絕緣層204的裸露部分，一直到基體202的表面。然後，可以在元件區域201處的基體202的裸露部分上方，生長一個閘極絕緣體210(例如閘極氧 化物)。在閘極絕緣層210上方，沉積一個導電層，作為閘極電極212，在此也可稱為閘極。作為示例，導電層可以是一層多晶矽。構成閘極212的導電材料的厚度約為4000 Å至6000 Å。可以除去用於構成閘極212所選的那部分導電層，以使閘極212的頂面和第三絕緣層208的頂面一樣高。第二場掩膜(圖中沒有標示出)可以在由絕緣層204、206、208、閘極絕緣體210和閘極212所構成的結構上方形成圖案，這僅作為示例，不作為侷限。還可選擇，藉由CMP(化學機械拋光)，使多晶矽平整到第三絕緣層208的頂面。藉由場掩膜中的開口，刻蝕所選的那部分多晶矽，刻蝕結束後，可以除去場掩膜。
參閱第2E圖，可以在第三絕緣層208和閘極212的上方沉積第四絕緣層214(例如一個氧化層)。然後在該結構上方，形成一個光致抗蝕劑掩膜(圖中沒有標示出)並形成圖案。可以將所選的那部分第四絕緣層214、以及構成閘極212和閘極絕緣層210的導電層，一直向下刻蝕到半導體基體202，以便形成第一開口216。還可以將第四絕緣層214、第三絕緣層208以及第一絕緣層204，刻蝕到半導體基體202，以便形成第二開口218。第一開口216的深度可以很深，以便將基體202的下表面裸露出來，這僅作為示例，不作為侷限。刻蝕結束後，可以除去光致抗蝕劑掩膜。在這個階段，例如藉由開口216、218植入合適的摻雜離子，可以形成源極和本體區。然而，源極和本體區也可以在稍後的技術中製備，例如參閱下文的第2J圖。形成開口216、218之後，導電層212、閘極氧化物210以及絕緣層214的剩餘部分，可以作為接下來深溝 槽刻蝕的硬掩膜。導電層212的剩餘部分，形成最終的功率元件的平面閘極。因此，平面閘極結構在接下來深溝槽刻蝕的過程中，起硬掩膜的作用。
形成開口216、218之後，可以選擇氧化導電層212在開口216以內的裸露部分。參閱第2F圖所示，由耐腐蝕材料(例如氮化物)製成的薄絕緣層219，可以沉積或形成內襯在硬掩膜開口216和218的底部和側壁上。薄絕緣層219的厚度約為1000 Å，這僅作為示例，不作為侷限。如圖2G所示，在由絕緣層204、208、214、閘極絕緣物210和導電層212以及薄絕緣層219所構成的結構上方，以及硬掩膜開口216和218的底部上的薄絕緣層219的水準部分，可以對其進行各向異性地刻蝕，以便利用在硬掩膜開口側壁上的那部分薄絕緣層219，構成側壁墊片220。如下所述，氧化閘極電極212的裸露部分，並形成側壁墊片220，可以在刻蝕深溝槽以及在深溝槽中生長磊晶層時，保護閘極電極。
然後，將基體202刻蝕到預設的深度，以便在對應硬掩膜開口216和218的地方，分別形成深溝槽222和224。因此，深溝槽222自對準到平面閘極212。溝槽的深度取決於元件的設計方式，最深可達到約100μm，這僅作為示例，不作為侷限。對於製備硬掩膜開口216、218的刻蝕過程，刻蝕材料最好選用基體材料，而不是構成側壁墊片220或第四絕緣物214的材料。在刻蝕基體202的過程中，側壁墊片220為製備基體的自對準提供補償。更確切地說，側壁墊片220為深溝槽222和閘極電極212之間提供補償。由於自對準到平面閘極結構212，無需使用光致抗蝕劑掩膜，就可以在 基體中製備溝槽。另外，自對準獲得的相鄰單元之間的間距，比利用非自對準的掩膜，進行溝槽刻蝕時可能獲得的間距更小。
形成溝槽222、224之後，參閱第2H圖所示，可以選擇沉積、生長或形成半導體插塞226和228，填充溝槽222和224。藉由選擇性的磊晶生長，可以選用半導體插塞226、228形成在溝槽222或224中，這僅作為示例，不作為侷限。例如，藉由在氫氣環境中退火，可以對該結構進行預調節。生長一個選擇性的磊晶生長(SEG)層。該SEG層可以是矽(Si)。SEG層也可選用鍺化矽SixGey，例如含有1-20%的Ge。生長SixGey的優勢在於，其摻雜劑量可以比矽的摻雜劑量大十倍。例如，一般對於Si而言，摻雜濃度約為1018-1019 cm-3，對於SixGey而言，摻雜濃度約為1020-1021 cm-3。另外，Si和SixGey之間在側壁處的晶格失配所帶來的應變，實際上提高了電荷載流子的遷移率，例如可以高達50%。要注意的是，磊晶層僅僅生長在裸露的半導體材料上。因此，無需使用掩膜，半導體插塞226、228就可以選擇性地形成在溝槽222、224中。疊加有第四絕緣層214的平面閘極212在SEG過程中，起硬掩膜的作用。氮化物側壁220有助於阻止在平面閘極212的側壁上進行磊晶生長。所形成的半導體插塞226、228的導電類型與基體202的導電類型相反。如果半導體基體202為第一導電類型，那麼半導體插塞226、228就構成第二導電類型的立柱，適當地配置這些立柱的摻雜濃度和寬度，使它們都與半導體基體202的相鄰部分達到電荷平衡。這些立柱還自對準到平面閘極212上。
參閱第2I圖，可以回刻矽插塞226和228，使它們與基體202的表 面在同一水平線上。然後除去墊片220。
參閱第2J圖所示，將覆蓋著終止區的本體掩膜(圖中沒有標示出)使用在結構上方，然後藉由本體植入，形成本體區230。植入是利用與基體202呈一定傾斜角的摻雜離子植入進行的。基體202應當傾斜，使其法線(即垂直於基體表面所在平面的方向)與離子束方向之間的夾角約為10o-15o，這僅作為示例，不作為侷限。儘管基體202是傾斜的，但是在植入過程中，還可以旋轉基體202。植入後，除去本體掩膜。利用源極掩膜(圖中沒有標示出)阻擋終止區，並藉由源極植入，形成源極區231。源極植入也可以垂直進行，也就是說沿垂直於半導體基體202表面的離子植入的法線方向。源極植入後，除去源極掩膜。利用熱擴散驅入所植入的離子。因此，源極和本體區也自對準到平面閘極212。
參閱第2K圖所示，將第五絕緣層232(例如一種氧化物)填充到開口216和218中，以及由絕緣層204、208、214、閘極絕緣物210、導電材料212和半導體插塞226、228所構成的結構上方。在第五絕緣層232的上方使用接觸掩膜(圖中沒有標示出)，以製備本體接頭。第五絕緣層232在溝槽216中的那部分，可以藉由接觸掩膜刻蝕，以形成接觸開口234。接觸開口234可以略微延伸到半導體插塞226的源極區231中。參閱第2L圖所示，藉由接觸開口234進行本體接觸植入，以形成本體接頭236，可以同本體區230形成良好的接觸。金屬238(例如鎢)可以沉積在接觸開口234中，以便接觸源極231和本體接頭236。參閱第2M圖所示，金屬也可以形成在第五絕緣層232的上方，以完成平面閘極功率DMOS元件 的製備。在平面閘極212上適當地載入電壓時，會形成從源極區231穿過本體區230到達基體202的導電通路。基體202作為功率DMOS的汲極。金屬層形成在基體202的底部，作為汲極金屬205。半導體基體202靠近半導體插塞226、228的那部分，作為汲極漂流區，用於承載擊穿電壓。半導體插塞226、228同相鄰的那部分基體202達到電荷平衡，以便構成一個超接面區，從而在保持低導通電阻Rds的同時，提高元件的擊穿電壓。自對準結構使單元間距可以很小，從而獲得更高的單元密度，進一步改善了Rds。
參閱第2A圖至第2M圖所示的製備自對準電荷平衡的平面閘極功率DMOSFET的方法，可以製成單元間距(從元件溝槽到元件溝槽)為12微米或更小(例如8-12微米甚至小於8微米)的功率DMOS元件。
依據本發明的一個實施例，第2A圖至第2M圖所示的上述製備過程，可用於製備自對準電荷平衡的半導體元件。第3圖表示具有兩個或多個元件單元301A、301B和終止區303的電荷平衡元件300，這僅作為示例，不作為侷限。元件單元301A、301B形成在半導體基體302中。每個元件單元都含有一個用半導體插塞326填充的自對準溝槽。半導體插塞326的導電類型與基體302的導電類型相反，並同周圍的基體302區域達到電荷平衡。源極區331和本體接頭336形成在半導體基體302中，最接近基體的表面以及由插塞326填充的自對準溝槽，平面閘極312形成在基體302上方，最接近源極區331。所形成的本體區330最接近源極區。本體接觸區形成在絕緣層332中的開口下方，以便同本體區330形成良好的接觸。閘 極絕緣物310(例如閘極氧化物)，可以將閘極312同基體302電絕緣，尤其是同源極區331和本體區330電絕緣。不同元件單元301A、301B的閘極312可以相互電連接。
如果元件單元301A、301B中含有半導體插塞326的溝槽，是利用上述自對準技術製成的，那麼一個或多個元件單元301A、301B的單元間距P就可以小於12微米，例如8-12微米甚至小於8微米。
一個或多個絕緣層314、332覆蓋著閘極312，並將閘極與位於絕緣層上方的導電層338(例如一個金屬層)絕緣。導電層338可以與源極區331和每個元件的本體區330藉由絕緣層314、332中的開口電接觸，以及與半導體插塞326電接觸。藉由打開從源極區331到基體302的平面閘極312下方的本體區330中的平面通道，在每個閘極312上載入電壓，就可以控制從導電層338穿過基體302到達形成在基體背面的汲極電極305之間的電流。
元件300可以選擇包含一個終止區303，具有自對準的溝槽，形成在基體302中，並用與導電層338電絕緣的半導體插塞328填充。
綜上所述，本發明的實施例允許超接面電晶體以自對準的方式形成，比原有技術的製備技術所獲得的單元密度更大。因此，使用了超接面電晶體的元件，在提升元件性能的同時，還可以減少製備時間和成本。
儘管本發明關於某些較佳的版本已經做了詳細的敍述，但是仍可能存在其他版本。因此，本發明的範圍不應由上述說明決定，與之相反，本發明的範圍應參照所附的權利要求書及其全部等效內 容。任何可選件(無論首選與否)，都可與其他任何可選件(無論首選與否)組合。在以下權利要求中，除非特別聲明，否則不定冠詞「一個」或「一種」都指下文內容中的一個或多個專案的數量。除非用「意思是」明確指出限定功能，否則所附的權利要求書並不應認為是意義和功能的侷限。
300‧‧‧電荷平衡元件
301A、301B‧‧‧元件單元
302‧‧‧基體
305‧‧‧汲極電極
303‧‧‧終止區
310‧‧‧閘極絕緣物
312‧‧‧平面閘極
314、332‧‧‧絕緣層
326、328‧‧‧半導體插塞
330‧‧‧本體區
331‧‧‧源極區
336‧‧‧本體接頭
338‧‧‧導電層

Claims (15)

  1. 一種用於製備自對準電荷平衡的半導體元件的方法，其中，該方法包含：a 在第一導電類型的一半導體基體上方，製備一或複數個平面閘極；b 在刻蝕一或複數個深溝槽之前，在該平面閘極的一或複數個對應邊處，形成一或複數個側壁墊片；在該平面閘極上方製備一頂部閘極絕緣層，將該平面閘極和該頂部閘極絕緣層用作刻蝕深溝槽的硬掩膜，通過該硬掩膜在半導體中刻蝕一或複數個深溝槽，自對準到該平面閘極上；c 用第二導電類型的一半導體材料填充該深溝槽，使該深溝槽與該半導體基體的鄰近區域達到電荷平衡；d 在該平面閘極附近，該半導體基體的頂面處，進行一源極和一本體植入，其中在進行該源極和該本體植入之前，要先除去該側壁墊片。
  2. 如申請專利範圍第1項所述之用於製備自對準電荷平衡的半導體元件的方法，其中該基體更包含一重摻雜的底層和一相對輕摻雜的磊晶層，位於該底層上方。
  3. 如申請專利範圍第1項所述之用於製備自對準電荷平衡的半導體元件的方法，其中步驟c更包含藉由選擇性的磊晶生長SFG溝槽內的第二導電類型的該半導體材料，將該平面閘極和該頂部閘極絕緣層用作硬掩膜，填充該深溝槽。
  4. 如申請專利範圍第1項所述之用於製備自對準電荷平衡的半導體元件的方法，其中該側壁墊片由氮化物製成。
  5. 如申請專利範圍第1項所述之用於製備自對準電荷平衡的半導體元件的方法，其中步驟c更包含藉由溝槽內磊晶生長第二導電類型的該半導體材料，填充該深溝槽。
  6. 如申請專利範圍第1項所述之用於製備自對準電荷平衡的半導體元件的方法，其更包含在該平面閘極附近，該半導體基體的頂面處，進行一源極和一本體植入。
  7. 如申請專利範圍第6項所述之用於製備自對準電荷平衡的半導體元件的方法，其中所蝕刻進行的該源極和該本體植入，自對準到該平面閘極上。
  8. 如申請專利範圍第1項所述之用於製備自對準電荷平衡的半導體元件的方法，其更還包含在該半導體基體中，製備一終止區，該終止區含有一絕緣層，取代了該平面閘極。
  9. 如申請專利範圍第8項所述之用於製備自對準電荷平衡的半導體元件的方法，其中製備該終止區包含在步驟b中製備該深溝槽的同時，在該終止區中製備一深溝槽。
  10. 如申請專利範圍第1項所述之用於製備自對準電荷平衡的半導體元件的方法，其更包含在該半導體元件上方，製備一頂部絕緣層，在該頂部絕緣層中刻蝕接觸孔，這些接觸孔向下延伸到該半導體基體的平面上。
  11. 如申請專利範圍第10項所述之用於製備自對準電荷平衡的半導體元件的方法，其更包含在元件上方製備一源極金屬，在該半導體基體的底部製備一汲極金屬。
  12. 如申請專利範圍第1項所述之用於製備自對準電荷平衡的半導體元件的方法，其中用該半導體材料填充該深溝槽更包含用鍺矽SixGey填充該深溝槽。
  13. 如申請專利範圍第1項所述之用於製備自對準電荷平衡的半導體元件的方法，其中步驟a更包含在該半導體基體的表面上製備一或複數個絕緣層，並在一或複數個絕緣層上製備一或複數個平面閘極，從而使該平面閘極與該半導體基體電絕緣。
  14. 如申請專利範圍第13項所述之用於製備自對準電荷平衡的半導體元件的方法，其中步驟b更包含：藉由一或複數個絕緣物製備一或複數個開口，以裸露基體的表面；在一或複數個開口的一或複數個側壁上製備一或複數個側壁墊片；以及並且利用無掩膜刻蝕技術，刻蝕基體，以自對準的方式形成一或複數個溝槽，其中一或複數個側壁墊片可以抵抗刻蝕過程的侵襲。
  15. 如申請專利範圍第1項所述之用於製備自對準電荷平衡的半導體元件的方法，其中相鄰的元件溝槽之間的單元間距小於12微米。
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