CN111180522A - 具有超结和嵌氧硅层的半导体器件 - Google Patents

具有超结和嵌氧硅层的半导体器件 Download PDF

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Publication number
CN111180522A
CN111180522A CN201911087459.9A CN201911087459A CN111180522A CN 111180522 A CN111180522 A CN 111180522A CN 201911087459 A CN201911087459 A CN 201911087459A CN 111180522 A CN111180522 A CN 111180522A
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silicon
conductivity type
epitaxial layer
region
semiconductor device
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M.珀尔茨尔
黄小秋
R.哈泽
R.K.约希
S.莱奥曼特
马凌
A.迈泽
M.雷施
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

公开了具有超结和嵌氧硅层的半导体器件。半导体器件包括：第一导电类型的源极区和漏极区；在源极区和漏极区之间的第二导电类型的体区；栅极，被配置为控制通过体区的沟道的电流；在体区和漏极区之间的第一导电类型的漂移区带；由多个第二导电类型的区形成的超结结构，所述多个第二导电类型的区被由漂移区带的各间隔区在横向上彼此分隔开；以及沿着超结结构的第二导电类型的区的侧壁部署的扩散阻挡结构。扩散阻挡结构包括交替的硅层和掺杂有氧的硅层以及在交替的硅层和掺杂有氧的硅层上的硅遮盖层。

Description

具有超结和嵌氧硅层的半导体器件
背景技术。
超结功率MOSFET（金属氧化物半导体场效应晶体管）具有p型柱和n型柱的交替区。因为n型柱区的杂质浓度可能增加，所以由Rdson*A给出的导通损耗品质因数（FOM）可能降低，其中Rdson是器件的漏极源极导通电阻并且A是器件面积。由于导通损耗FOM可能降低，因此对于相同的导通电阻而言可能使器件的有源面积更小，由此使得由Rdson*QGD给出的开关损耗FOM也可能被降低，其中QGD是栅极—漏极电荷。
然而，p型掺杂剂物质从p型柱的向外扩散限定了器件的间距，并且因此限定了导通损耗FOM。p型掺杂剂物质从p型柱的向外扩散还限定了用于形成超结结构的外延基础层的厚度和数量，并且因此限定了成本。在用于形成超结结构的多个外延基础层的情况下，典型地同时引入n型掺杂剂和p型掺杂剂，并且在向外扩散期间，快速扩散的掺杂剂限定了一个掺杂区带。在另一个掺杂区带中，快速扩散的掺杂剂充当本底掺杂，并且因此降低载流子迁移率。
因此，更好地控制功率半导体器件的超结区中的掺杂剂向外扩散是合期望的。
发明内容
根据半导体器件的实施例，半导体器件包括：第一导电类型的源极区和漏极区；在源极区和漏极区之间的第二导电类型的体区；栅极，被配置为控制通过体区的沟道的电流；在体区和漏极区之间的第一导电类型的漂移区带；由多个第二导电类型的区形成的超结结构，所述多个第二导电类型的区被由漂移区带的各间隔区在横向上彼此分隔开；以及沿着超结结构的第二导电类型的区的侧壁部署的扩散阻挡结构，所述扩散阻挡结构包括交替的硅层和掺杂有氧的硅层以及在交替的硅层和掺杂有氧的硅层上的硅遮盖层。
扩散阻挡结构也可以被沿着第二导电类型的区的底面部署。
个别地或组合地，漂移区带可以与第二导电类型的区的底面接触。
个别地或组合地，漏极区可以被形成在硅衬底中，漂移区带可以被部署在形成于硅衬底之上的第一硅外延层中，并且源极区和体区可以被部署在形成于第一硅外延层之上的第二硅外延层中。
个别地或组合地，栅极可以是形成在第二硅外延层中的沟槽栅极或者是形成在第二硅外延层的背对第一硅外延层的表面上的平坦栅极。
个别地或组合地，半导体器件可以进一步包括与第二硅外延层中的源极区和体区电接触的接触部。
个别地或组合地，接触部可以竖向地延伸通过第二硅外延层，进入到第一硅外延层中，并且电接触多个第二导电类型的区中的区，并且接触部的侧壁可以通过绝缘材料与第二硅外延层和第一硅外延层在横向上分离开。
个别地或组合地，第二硅外延层可以接触第二导电类型的区的顶面。
根据制造半导体器件的方法的实施例，方法包括：形成第一导电类型的源极区和漏极区；形成第二导电类型的体区，其中，体区被部署在源极区和漏极区之间；形成栅极，该栅极被配置为控制通过体区的沟道的电流；形成第一导电类型的漂移区带，其中漂移区带被部署在体区与漏极区之间；形成被通过漂移区带的各间隔区在横向上彼此分隔开的多个第二导电类型的区，以形成超结结构；以及沿着超结结构的第二导电类型的区的侧壁形成扩散阻挡结构，扩散阻挡结构包括交替的硅层和掺杂有氧的硅层以及在交替的硅层和掺杂有氧的硅层上的硅遮盖层。
形成多个第二导电类型的区并且沿着第二导电类型的区的侧壁形成扩散阻挡结构可以包括：在第一导电类型的第一硅外延层中蚀刻多个沟槽，其中第一硅外延层包括漂移区带；在沟槽的侧壁和底部上外延生长交替的硅层和掺杂有氧的硅层；在交替的硅层和掺杂有氧的硅层上外延生长硅遮盖层；以及在形成扩散阻挡结构之后，利用第二导电类型的外延硅填充沟槽。
个别地或组合地，形成源极区和体区可以包括：在利用第二导电类型的外延硅填充沟槽之后，在第一硅外延层之上形成第二硅外延层；将第一导电类型的掺杂剂物质注入到第二硅外延层的对应于源极区的第一部分中；将第二导电类型的掺杂剂物质注入到第二硅外延层的对应于体区的第二部分中；以及对第二硅外延层退火，以激活所注入的第一导电类型的掺杂剂物质以形成源极区并且激活所注入的第二导电类型的掺杂剂物质以形成体区。
个别地或组合地，漏极区可以被部署在其上形成有第一硅外延层的硅衬底中。
个别地或组合地，可以在高于1000℃的温度范围内在30分钟或更短的时间内对第二硅外延层退火。
个别地或组合地，方法可以进一步包括在形成第二硅外延层之前平坦化第二导电类型的外延硅。
个别地或组合地，方法可以进一步包括：将接触沟槽蚀刻到第二硅外延层中，该接触沟槽暴露出源极区的侧壁和体区的顶表面；以及利用导电材料填充接触沟槽，该导电材料接触源极区的侧壁和体区的顶表面。
个别地或组合地，蚀刻接触沟槽可以进一步包括：将接触沟槽蚀刻到第一硅外延层中以暴露第一硅外延层的侧壁；在体区的侧壁和第一硅外延层的侧壁上沉积绝缘材料；以及将接触沟槽蚀刻到多个第二导电类型的区中的区中，其中导电材料可以与接触沟槽被蚀刻进入到其中的第二导电类型的区接触，其中可以通过绝缘材料在横向上将导电材料的侧壁与第二硅外延层和第一硅外延层分离开。
个别地或组合地，方法可以进一步包括在利用第二导电类型的外延硅填充多个沟槽之前从多个沟槽的底部去除交替的硅层和掺杂有氧的硅层以及硅遮盖层，从而当利用第二导电类型的外延硅填充多个沟槽时多个沟槽的底部未被覆盖。
个别地或组合地，利用第二导电类型的外延硅填充多个沟槽可以包括：在多个沟槽中选择性地原位生长第二导电类型的掺杂外延硅；以及在形成第二硅外延层之前将第二导电类型的原位掺杂的外延硅平坦化。
个别地或组合地，利用第二导电类型的外延硅填充多个沟槽可以包括：在多个沟槽中选择性地生长外延硅；平坦化外延硅；将第二导电类型的掺杂剂物质注入到平坦化的外延硅中；以及对第一硅外延层退火，以激活所注入的第二导电类型的掺杂剂物质。
本领域技术人员在阅读以下详细描述并且在查看随附附图时将认识到附加的特征和优点。
附图说明
附图中的元素未必相对于彼此成比例。同样的参考标号指明对应的相似部分。各种所图示的实施例的特征可以被组合，除非它们彼此排斥。在附图中描绘了实施例，并且在随后的描述中详述实施例。
图1图示具有超结结构和扩散阻挡结构的半导体器件的一个单元的实施例的部分横截面视图。
图2图示具有超结结构和扩散阻挡结构的半导体器件的一个单元的另一实施例的部分横截面视图。
图3A至图3E图示在制造处理的实施例的不同阶段期间具有超结结构和扩散阻挡结构的半导体器件的相应的横截面视图。
图4A至图4O图示在制造处理的另一实施例的不同阶段期间具有超结结构和扩散阻挡结构的半导体器件的相应的横截面视图。
具体实施方式
在此描述的实施例提供在半导体器件的超结结构的p型柱和n型柱之间的扩散阻挡结构。扩散阻挡结构控制在器件的超结区中从两个横向（侧）方向的掺杂剂相互扩散，由此例如通过减小单元间距来改善超结器件性能。单元间距可以是相邻单元的中心到中心距离或边缘edge到边缘距离。在每种情况下，在此描述的扩散阻挡结构提供在半导体器件的超结区中的更严密的掺杂剂分布控制。作为结果，通过将小间距器件的超结区中的n型和p型掺杂剂相互扩散的量减掉一半，从而可以把由Rdson*A给出的导通损耗FOM降低约20％或更多，允许在低电压范围（例如如10V那么低）中使用基于超结的晶体管。在此描述的扩散阻挡结构教导也非常适合于高电压应用，例如达到1000V或者甚至更高。接下来更详细地描述具有这样的扩散阻挡结构的半导体器件的实施例以及对应的制造方法。
图1图示具有超结结构的半导体器件100的一个单元的实施例的部分横截面视图。半导体器件100可以包括多个这样的单元，每个单元具有相同或相似的构造。半导体器件100可以是功率半导体器件，诸如功率MOSFET、IGBT（绝缘栅双极晶体管）等。半导体器件包括：第一导电类型的源极区102和漏极区104；在源极区102和漏极区104之间的与第一导电类型相反的第二导电类型的体区106；平坦栅极108，其包括栅极电极110，该栅极电极110通过栅极电介质112与下面的半导体材料分离开，并且被配置为控制通过体区106的沟道114的电流；以及在体区106和漏极区104之间的第一导电类型的漂移区带116。沟道区114沿着平坦栅极108的底部横向地延伸。器件电流具有在沿平坦栅极横向延伸的沟道区114中的横向分量，以及沿着漂移区带竖向延伸的竖向分量。
取决于器件的类型，可以在漂移区带116中和/或在漂移区带116与漏极区104之间形成附加的结构。例如，在IGBT类型器件的情况下，可以在漂移区带116和漏极区104之间形成场停止层（未示出）。一般而言，具有超结结构的任何类型的半导体器件可以利用在此描述的扩散阻挡教导。
在n沟道器件的情况下，源极区102、漏极区104和漂移区带116被掺杂为n型，并且体区106和沟道区114被掺杂为p型。相反，在p沟道器件的情况下，源极区102、漏极区104和漂移区带116被掺杂为p型，并且体区106和沟道区114被掺杂为n型。在任一情况下，超结结构由被通过漂移区带116的间隔区120在横向上彼此分隔开的多个第二导电类型的区118形成。第二导电类型的区118可以具有柱状（竖向上细长的）形状、条形（横向上细长的）形状或者取决于单元构造的类型的另外的类型的形状。在图1中的半导体器件100的部分横截面视图中示出了第二导电类型的两个这样的区118和漂移区带116的一个间隔区120。
在一个实施例中，半导体器件100的漏极区104是诸如硅衬底的半导体衬底的高掺杂区，并且漂移区带116和第二导电类型的区118是形成在半导体衬底之上的第一外延层的部分。进一步地根据该实施例，半导体器件100的源极区102和体区106被部署在形成于第一外延层之上的第二外延层中。
半导体器件100还可以包括延伸通过源极区102并且进入到体区106中的接触沟槽122。该接触沟槽122被填充有诸如掺杂的多晶硅、金属等的导电材料124，其在接触沟槽122的侧壁处接触源极区102，并且在接触沟槽122的底部处接触高掺杂的体接触区126。高掺杂的体接触区126具有与体区106相同的掺杂类型，但是处在更高的浓度以提供与填充接触沟槽122的导电材料124的良好的欧姆接触。平坦栅极108被通过层间电介质128与上面的导电材料124分离开。
半导体器件100进一步包括沿着超结结构的第二导电类型的区118的至少侧壁132部署的扩散阻挡结构130。根据图1中图示的实施例，扩散阻挡结构130还被沿着第二导电类型的区118的底面133部署。扩散阻挡结构130包括交替的硅层134和掺杂有氧的硅层136以及在交替的硅层134和掺杂有氧的硅层136上的硅遮盖层138。掺杂有氧的硅层136在相应的各单层136中具有非常高的氧掺杂剂浓度，每个单层136与硅层134邻接，该硅层134与邻接的掺杂有氧的硅层136相比可以是不同的厚度。
交替的硅层134和掺杂有氧的硅层136形成通过外延而生长的掺杂有氧的硅区。在实施例中，针对每个掺杂有氧的硅层136的氧浓度低于5x1014cm-3。每个掺杂有氧的硅层136可以具有在原子范围内（例如一个或几个原子厚）内或者在纳米（nm）范围内的厚度，以确保用于在掺杂有氧的硅层136上生长硅134的足够的晶体信息。可以通过如下来实现交替的硅层134和掺杂有氧的硅层136：与氧层136交替地外延生长硅层134，各氧层136被例如以用于掺杂有氧的硅层136的特定地限制的厚度而分别吸收在硅层134的表面上，以确保足够的硅生长。
图1提供扩散阻挡结构130的分解视图，该扩散阻挡结构130还可以包括在交替的硅层134和掺杂有氧的硅层136下方的硅缓冲层140。该硅缓冲层140可以相对薄，例如在2—5nm厚的范围内。可以在注入或蚀刻步骤之后生长硅缓冲层140。遮盖层138提供在器件100的该区中的高载流子迁移率。沟道区114的部分可以被形成在硅遮盖层138的沿着平坦栅极108横向地延伸的部分中。可以省略缓冲层140。
扩散阻挡结构130的掺杂有氧的硅层136限制掺杂剂原子从超结结构的第二导电类型的区118横向地向外扩散到漂移区带116的间隔区120中，并且由于氧充当间隙阻止物而在限制间隙驱动的扩散方面尤其有效。因此，可以很好地控制第二导电类型的区118的横向尺寸，允许更小的单元间距。在与扩散阻挡结构130的掺杂有氧的硅层136平行的平面中，掺杂剂照常扩散。在垂直于扩散阻挡结构130的掺杂有氧的硅层136的平面中，扩散阻挡结构130减慢掺杂剂相互扩散。扩散阻挡结构130的掺杂有氧的硅层136还可以改善器件100的沟道区114内的载流子迁移率。
可以通过将氧部分单层引入硅晶格来形成扩散阻挡结构130的掺杂有氧的硅层136。氧原子被间隙地放置以最小化对硅晶格的破坏。硅原子的层134将相邻的氧部分单层136分离。交替的硅层134和掺杂有氧的硅层136可以是通过在不同的步骤处在进行氧吸收的情况下进行硅外延而形成的。例如，可以在外延处理期间控制温度和气体条件以形成部分氧单层136。可以通过例如控制氧前体到外延室中的引入来在外延的硅层134之间引入/并入氧。所得到的扩散阻挡结构130包括主要包括硅但是具有一定掺杂水平或浓度水平的氧的单层136，其与没有氧的标准的外延硅层134交替。扩散阻挡结构130还包括在交替的硅层134和掺杂有氧的硅层136上外延生长的硅遮盖层138，或者可以省略该硅遮盖层138。
图2图示具有超结结构的半导体器件200的一个单元的另一实施例的部分横截面视图。图2中图示的实施例类似于图1中图示的实施例。然而不同的是，半导体器件200具有沟槽栅极202而不是平坦栅极。沟槽栅极202包括延伸到半导体材料中的栅极沟槽204和被部署在栅极沟槽204中的栅极电极206。栅极电极206通过栅极电介质208与周围的半导体材料绝缘。场电极（未示出）可以在栅极沟槽204中被部署在栅极电极206下方，并且通过场电介质（未示出）与周围的半导体材料和栅极电极206绝缘。场电极可以被替代地部署在与栅极电极206不同的沟槽中或者被完全省略。在每种情况下，半导体器件200还包括被沿着超结结构的第二导电类型的区118的至少侧壁132部署的扩散阻挡结构130。
图3A至图3E图示在制造处理的实施例的不同阶段期间具有超结结构和扩散阻挡结构130的半导体器件的相应的横截面视图。
图3A示出在提供了诸如硅衬底的半导体生长衬底300并且在衬底300上外延生长了第一导电类型的第一外延层302之后的半导体器件。生长衬底300可以被重掺杂，例如以形成器件的漏极区。第一外延层302可以被原位掺杂或离位掺杂，并且形成器件的漂移区带。
图3B示出在第一外延层302中形成沟槽304之后的半导体器件。可以使用任何典型的沟槽形成处理来将沟槽304蚀刻进入到第一外延层302中，诸如在第一外延层302的前主表面303上施加掩模/绝缘材料（未示出），并且通过掩模中的相应开口将沟槽304蚀刻进入到第一外延层302中。
图3C示出在沟槽304的侧壁和底部上外延生长了扩散阻挡结构130的交替的硅层134和掺杂有氧的硅层136之后的半导体器件。根据该实施例，在将沟槽304蚀刻进入到第一外延层302中之后但是在形成器件的源极区和体区之前，在沟槽304的侧壁和底部上外延生长交替的硅层134和掺杂有氧的硅层136。硅遮盖层138可以具有与交替的硅层134和掺杂有氧的硅层136相同的标准的原位掺杂浓度，并且可以稍后被利用不同的掺杂剂物质和浓度来掺杂。替换地，与交替的硅层134和掺杂有氧的硅层136相比，硅遮盖层138可以具有不同的原位掺杂浓度。
图3D示出在利用第二导电类型的外延硅306填充了沟槽304之后的半导体器件。第二导电类型的外延硅306可以被原位掺杂或离位掺杂并且可以是例如通过化学机械抛光（CMP）来平坦化的。
图3E示出在将第一导电类型的掺杂剂物质注入到第二导电类型的外延硅306的第一部分中或者注入到生长在外延硅306之上的第二硅外延层中之后以及在将第二导电类型的掺杂剂物质注入到外延硅306或第二外延层的第二（更深）部分中之后的半导体器件。对半导体器件退火以激活所注入的第一导电类型的掺杂剂物质以形成器件的源极区308，并且激活所注入的第二导电类型的掺杂剂物质以形成器件的体区310。在一个实施例中，退火是在高于1000℃的温度范围中在30分钟或更短时间内完成的。在第二导电类型的外延硅306之上生长第二外延层的情况下，可以在形成第二硅外延层之前例如通过CMP来平坦化第二导电类型的外延硅306。
栅极沟槽312也形成在半导体材料中，并且在每个栅极沟槽312中部署有栅极电极314。栅极电极314通过栅极电介质316与周围的半导体材料绝缘。接触沟槽318延伸通过源极区308并且进入到体区310中。接触沟槽318被填充有导电材料320，诸如掺杂的多晶硅、金属等，其在接触沟槽318的侧壁处接触源极区308并且在接触沟槽318的底部处接触高掺杂的体接触区322。高掺杂的体接触区322具有与体区310相同的掺杂类型，但是处于更高的浓度以提供与填充接触沟槽318的导电材料320的良好的欧姆接触。在半导体材料的顶表面和导电材料320之间提供层间电介质324。
图4A至图4O图示在制造处理的另一实施例的不同阶段期间具有超结结构和扩散阻挡结构130的半导体器件的相应的横截面视图。图4A至图4O图示一个单元中的半导体器件的处理。该半导体器件可以包括多个这样的单元，每个单元具有相同或相似的构造。
图4A示出在提供了基底半导体材料400并且在基底半导体材料400上形成诸如基于硅的硬掩模之类的硬掩模402之后的半导体器件。该硬掩模402具有开口404，其限定要被蚀刻进入到基底半导体材料400中的沟槽的位置。基底半导体材料400可以是诸如硅衬底的生长衬底或者在诸如衬底上生长的硅外延层。
图4B示出在将沟槽406蚀刻进入到基底半导体材料400中之后以及在沿着沟槽406的侧壁408和底部410形成扩散阻挡结构130之后的半导体器件。该扩散阻挡结构130可以如在此先前描述的那样形成。
图4C示出在间隔部蚀刻处理之后的半导体器件，间隔部蚀刻处理将扩散阻挡结构130从沟槽406的底部去除。在这种情况下，基底半导体材料400可以形成器件的漂移区带，并且漂移区带可以邻接沟槽406的底部410。替换地，可以跳过间隔部蚀刻处理，从而扩散阻挡结构130沿着沟槽406的底部保留。
图4D示出在沟槽406中以及在基底半导体材料400的顶表面上选择性地外延生长第二导电类型的半导体材料412之后的半导体器件。填充沟槽406的第二导电类型的半导体材料412可以被原位掺杂或离位掺杂。在离位掺杂的情况下，例如，如果想要进行更精确的掺杂剂量控制，则在沟槽406中执行硅的选择性外延生长，随后进行平坦化、硬掩模去除、被掩蔽的掺杂剂注入和掺杂剂激活，以限定沟槽406中的第二导电类型的区412。在原位掺杂的情况下，在沟槽406中执行掺杂（第二导电类型）的硅的选择性外延生长，随后进行平坦化和硬掩模去除。
在原位掺杂或离位掺杂的情况下，例如通过在硬掩模402上停止的CMP来平坦化填充沟槽406的半导体材料412，并且去除硬掩模402，产生第二导电类型的区412，其被由通过基底半导体材料400实现的漂移区带的间隔区414在横向上彼此分隔开。第二导电类型的区412和漂移区带的间隔区414如先前在此描述那样共同形成超结结构。在图4D的部分横截面视图中示出一个这样的第二导电类型的区412和两个这样的漂移区带的间隔区414。在如在图4C中示出那样扩散阻挡结构130被从沟槽406的底部去除的情况下，由基底半导体材料400实现的漂移区带与第二导电类型的区412的底面416接触。
图4E示出在第一导电类型的基底半导体材料400之上生长同一导电类型的硅外延层418之后的半导体器件。第一导电类型的硅外延层418可以被原位掺杂或离位掺杂。
图4F示出在将栅极沟槽420蚀刻到第一导电类型的硅外延层418中、在栅极沟槽420的侧壁和底部上形成牺牲氧化物422、以及执行进入栅极沟槽420的底部中的可选的第一导电类型的注入以形成恰好在栅极沟槽420下方的第一导电类型的掺杂区424之后的半导体器件。
图4G示出在从栅极沟槽420的侧壁和底部去除牺牲氧化物422、随后在栅极沟槽420的侧壁和底部上形成栅极氧化物426以及在栅极沟槽420中形成栅极电极428之后的半导体器件。栅极氧化物426将栅极电极428与周围的半导体材料分离。
图4H示出在硅外延层418上形成屏蔽氧化物430之后，并且在将第二导电类型的掺杂剂物质注入并且驱动到硅外延层418的下部部分432中以及将第一导电类型的掺杂剂物质注入到硅外延层418的上部部分434中之后的半导体器件。最终对硅外延层418退火以激活所注入的第一导电类型的掺杂剂物质以形成每个单元的源极区434'，并且激活所注入的第二导电类型的掺杂剂物质以形成每个单元的体区432'。在一个实施例中，在高于1000℃的温度范围内在30分钟或更短的时间内对硅外延层418退火。
图4I示出在硅外延层418上形成层间电介质436之后，并且在层间电介质上形成诸如光致抗蚀剂的图案化的接触掩模438之后的半导体器件。图案化的接触掩模438具有与形成在基底半导体材料400中的沟槽406对准的开口440。
图4J示出在将接触沟槽422蚀刻进入到硅外延层418中并且蚀刻至填充沟槽406的第二导电类型的半导体材料412之后的半导体器件。接触沟槽蚀刻处理蚀刻暴露出硅外延层418和基底半导体材料400的侧壁423，并且可以包括层间电介质436的暴露部分的各向异性蚀刻、硅外延层418的暴露部分的各向异性蚀刻、以及层间电介质436的横向蚀刻，以相对于蚀刻进入到硅外延层418中的沟槽442扩宽形成在层间电介质436中的开口。在形成接触沟槽442之后，去除图案化的接触掩模438。
图4K示出在接触沟槽442中沉积间隔部氧化物444之后的半导体器件。间隔部氧化物444沉积在硅外延层418和基底半导体材料400的暴露的侧壁423上，并且沉积在半导体材料412的顶表面446上。
图4L示出在从填充沟槽406的第二导电类型的半导体材料412的顶表面446去除间隔部氧化物444之后的半导体器件。
图4M示出在对填充沟槽406的第二导电类型的半导体材料412的暴露的顶表面446进行凹槽蚀刻之后、并且在对源极区434'进行横向回蚀以在源极区434'和体区432'之间创建台阶448之后的半导体器件。在横向回蚀之后，每个接触沟槽422暴露出邻接的源极区434'的侧壁450和体区432'的顶表面452。
图4N示出在体区432'的暴露的顶表面452中以及在填充沟槽406的第二导电类型的半导体材料412的凹入部分中形成在n沟道器件的情况下的p+区之类的高掺杂体接触区454之后的半导体器件。高掺杂的体接触区454提供到相邻的半导体材料的低欧姆接触。可以在此时对器件退火以激活所有先前注入的掺杂剂，包括源极区掺杂剂和体区掺杂剂。
图4O示出在接触沟槽442被填充有接触源极区434'的侧壁450和体区432'的顶表面452的导电材料456之后的半导体器件。在一个实施例中，通过在接触沟槽442中沉积诸如Ti或TiN衬垫的导电衬垫458、随后利用诸如W的金属460填充接触沟槽并且例如通过回蚀处理平坦化金属460来形成导电材料456。然后，使用典型的金属光刻处理在层间电介质436上沉积金属层462。金属层与填充接触沟槽442的导电材料456接触。
为了易于描述而使用了诸如“在..之下”、“下方”、“下部”、“之上”和“上部”等的空间相对术语以解释一个元件相对于第二元件的定位。这些术语意图涵盖器件的除了与在各图中描绘的那些不同的定向之外的不同定向。进一步地，诸如“第一”、“第二”等的术语也被用于描述各种元件、区、部段等，并且也不意图进行限制。贯穿于描述，同样的术语指代同样的元素。
如在此使用的那样，术语“具有”、“包含”、“包括”、和“含有”等是开放式术语，其指示所声明的元素或特征的存在但是不排除附加的元素或特征。除非上下文另外清楚地指示，否则量词“一”、“一个”和指代词“该”意图包括复数以及单数。
考虑到以上变化和应用的范围，应当理解，本发明不限于前述描述，也不限于附图。相反，本发明仅由所附权利要求及其合法等同物限制。

Claims (20)

1.一种半导体器件，包括：
第一导电类型的源极区和漏极区；
在源极区和漏极区之间的第二导电类型的体区；
栅极，被配置为控制通过体区的沟道的电流；
在体区和漏极区之间的第一导电类型的漂移区带；
由多个第二导电类型的区形成的超结结构，所述多个第二导电类型的区被由漂移区带的各间隔区在横向上彼此分隔开；以及
沿着第二导电类型的区的侧壁部署的扩散阻挡结构，扩散阻挡结构包括交替的硅层和掺杂有氧的硅层以及在交替的硅层和掺杂有氧的硅层上的硅遮盖层。
2.根据权利要求1所述的半导体器件，其中扩散阻挡结构还被沿着第二导电类型的区的底面部署。
3.根据权利要求1所述的半导体器件，其中漂移区带与第二导电类型的区的底面接触。
4.根据权利要求1所述的半导体器件，其中漏极区被形成在硅衬底中，其中漂移区带被部署在形成于硅衬底之上的第一硅外延层中，并且其中源极区和体区被部署在形成于第一硅外延层之上的第二硅外延层中。
5.根据权利要求4所述的半导体器件，其中栅极是形成在第二硅外延层中的沟槽栅极。
6.根据权利要求4所述的半导体器件，其中栅极是形成在第二硅外延层的背对第一硅外延层的表面上的平坦栅极。
7.根据权利要求4所述的半导体器件，进一步包括与第二硅外延层中的源极区和体区电接触的接触部。
8.根据权利要求7所述的半导体器件，其中接触部竖向地延伸通过第二硅外延层，进入到第一硅外延层中，并且电接触所述多个第二导电类型的区中的区，并且其中接触部的侧壁通过绝缘材料与第二硅外延层和第一硅外延层在横向上分离开。
9.根据权利要求4所述的半导体器件，其中第二硅外延层接触第二导电类型的区的顶面。
10.一种制造半导体器件的方法，所述方法包括：
形成第一导电类型的源极区和漏极区；
形成第二导电类型的体区，其中体区被部署在源极区和漏极区之间；
形成栅极，栅极被配置为控制通过体区的沟道的电流；
形成第一导电类型的漂移区带，其中漂移区带被部署在体区与漏极区之间；
形成被通过漂移区带的各间隔区在横向上彼此分隔开的多个第二导电类型的区，以形成超结结构；以及
沿着超结结构的第二导电类型的区的侧壁形成扩散阻挡结构，扩散阻挡结构包括交替的硅层和掺杂有氧的硅层以及在交替的硅层和掺杂有氧的硅层上的硅遮盖层。
11.根据权利要求10所述的方法，其中形成所述多个第二导电类型的区并且沿着第二导电类型的区的侧壁形成扩散阻挡结构包括：
在第一导电类型的第一硅外延层中蚀刻多个沟槽，其中第一硅外延层包括漂移区带；
在沟槽的侧壁和底部上外延生长交替的硅层和掺杂有氧的硅层；
在交替的硅层和掺杂有氧的硅层上外延生长硅遮盖层；以及
在形成扩散阻挡结构之后，利用第二导电类型的外延硅填充沟槽。
12.根据权利要求11所述的方法，其中形成源极区和体区包括：
在利用第二导电类型的外延硅填充沟槽之后，在第一硅外延层之上形成第二硅外延层；
将第一导电类型的掺杂剂物质注入到第二硅外延层的对应于源极区的第一部分中；
将第二导电类型的掺杂剂物质注入到第二硅外延层的对应于体区的第二部分中；以及
对第二硅外延层退火，以激活所注入的第一导电类型的掺杂剂物质以形成源极区并且激活所注入的第二导电类型的掺杂剂物质以形成体区。
13.根据权利要求12所述的方法，其中漏极区被部署在其上形成有第一硅外延层的硅衬底中。
14.根据权利要求12所述的方法，其中在高于1000℃的温度范围内在30分钟或更短的时间内对第二硅外延层退火。
15.根据权利要求12所述的方法，进一步包括：
在形成第二硅外延层之前平坦化第二导电类型的外延硅。
16.根据权利要求12所述的方法，进一步包括：
将接触沟槽蚀刻到第二硅外延层中，接触沟槽暴露出源极区的侧壁和体区的顶表面；以及
利用导电材料填充接触沟槽，导电材料接触源极区的侧壁和体区的顶表面。
17.根据权利要求16所述的方法，其中蚀刻接触沟槽进一步包括：
将接触沟槽蚀刻到第一硅外延层中以暴露第一硅外延层的侧壁；
在体区的侧壁和第一硅外延层的侧壁上沉积绝缘材料；以及
将接触沟槽蚀刻到所述多个第二导电类型的区中的区中，
其中导电材料与接触沟槽被蚀刻进入到其中的第二导电类型的区接触，
其中通过绝缘材料在横向上将导电材料的侧壁与第二硅外延层和第一硅外延层分离开。
18.根据权利要求11所述的方法，进一步包括：
在利用第二导电类型的外延硅填充所述多个沟槽之前从所述多个沟槽的底部去除交替的硅层和掺杂有氧的硅层以及硅遮盖层，从而当利用第二导电类型的外延硅填充所述多个沟槽时所述多个沟槽的底部未被覆盖。
19.根据权利要求11所述的方法，其中利用第二导电类型的外延硅填充所述多个沟槽包括：
在所述多个沟槽中选择性地原位生长第二导电类型的掺杂外延硅；以及
在形成第二硅外延层之前将第二导电类型的原位掺杂的外延硅平坦化。
20.根据权利要求11所述的方法，其中利用第二导电类型的外延硅填充所述多个沟槽包括：
在所述多个沟槽中选择性地生长外延硅；
平坦化外延硅；
将第二导电类型的掺杂剂物质注入到平坦化的外延硅中；以及
对第一硅外延层退火，以激活所注入的第二导电类型的掺杂剂物质。
CN201911087459.9A 2018-11-09 2019-11-08 具有超结和嵌氧硅层的半导体器件 Pending CN111180522A (zh)

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