JP5246403B2 - 半導体装置及びその製造方法、並びに電子部品及びその製造方法 - Google Patents
半導体装置及びその製造方法、並びに電子部品及びその製造方法 Download PDFInfo
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- JP5246403B2 JP5246403B2 JP2008247427A JP2008247427A JP5246403B2 JP 5246403 B2 JP5246403 B2 JP 5246403B2 JP 2008247427 A JP2008247427 A JP 2008247427A JP 2008247427 A JP2008247427 A JP 2008247427A JP 5246403 B2 JP5246403 B2 JP 5246403B2
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 136
- 238000004519 manufacturing process Methods 0.000 title claims description 39
- 238000000034 method Methods 0.000 title description 47
- 239000011347 resin Substances 0.000 claims abstract description 81
- 229920005989 resin Polymers 0.000 claims abstract description 81
- 238000005452 bending Methods 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 4
- 230000035882 stress Effects 0.000 abstract description 100
- 229910000679 solder Inorganic materials 0.000 abstract description 65
- 230000008646 thermal stress Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 283
- 239000010949 copper Substances 0.000 description 60
- 239000011651 chromium Substances 0.000 description 35
- 238000005516 engineering process Methods 0.000 description 34
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 33
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 31
- 229910052802 copper Inorganic materials 0.000 description 31
- 238000010586 diagram Methods 0.000 description 27
- 229920001721 polyimide Polymers 0.000 description 26
- 229910052782 aluminium Inorganic materials 0.000 description 17
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 17
- 239000009719 polyimide resin Substances 0.000 description 17
- 239000011241 protective layer Substances 0.000 description 17
- 239000011521 glass Substances 0.000 description 15
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 15
- 239000010408 film Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 12
- 239000000758 substrate Substances 0.000 description 12
- 239000002585 base Substances 0.000 description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 10
- 229910052737 gold Inorganic materials 0.000 description 10
- 239000010931 gold Substances 0.000 description 10
- 239000004642 Polyimide Substances 0.000 description 9
- 238000011161 development Methods 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000006071 cream Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 239000004033 plastic Substances 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 230000008642 heat stress Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- -1 aluminum silicon copper Chemical compound 0.000 description 1
- 239000003963 antioxidant agent Substances 0.000 description 1
- 230000003078 antioxidant effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001151 other effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L23/00—Details of semiconductor or other solid state devices
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
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- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
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- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Description
前記電極の少なくとも一部を避けて前記ウエーハに第1の応力緩和層を設ける工程と、
前記電極から前記第1の応力緩和層の上にかけて第1の導通部を形成する工程と、
前記第1の応力緩和層の上方で前記第1の導通部に接続される外部電極を形成する工程と、
前記ウエーハを個々の個片に切断する工程と、
を有し、
前記第1の応力緩和層を設ける工程及び前記第1の導通部を形成する工程の少なくともいずれか一方の工程にて、応力緩和を増長させる構造を形成する。
前記第2の導通部が形成された前記第2の応力緩和層の上に、第3の応力緩和層及び第3の導通部を設け、
前記第2の導通部を線状に形成し、前記第1及び第3の導通部を、前記第2の導通部よりも大きな平面的拡がりを有するように面状に形成してもよい。
前記半導体チップの上にて前記電極の少なくとも一部を避けるように設けられる第1の応力緩和層と、
前記電極から前記第1の応力緩和層の上にかけて形成される第1の導通部と、
前記第1の応力緩和層の上方に位置する前記第1の導通部に形成される外部電極と、
を有し、
前記第1の応力緩和層は表面に窪み部を有するように形成され、前記第1の導通部は前記窪み部の上を通って形成される。
前記第2の導通部が形成された前記第2の応力緩和層の上に設けられる第3の応力緩和層及び第3の導通部と、
を有し、
前記第2の導通部は線状に形成され、前記第1及び第3の導通部は、前記第2の導通部よりも大きな平面的拡がりを有するように面状に形成されてもよい。
図5は、本発明の前提となる半導体装置を示す平面図である。この半導体装置は、いわゆるCSPに分類されるもので、半導体チップ1の電極12から、能動面1aの中央方向に配線3が形成され、各配線3には外部電極5が設けられている。全ての外部電極5は、応力緩和層7の上に設けられているので、回路基板(図示せず)に実装されたときの応力の緩和を図ることができる。また、外部電極5の上には、保護膜としてソルダレジスト層8が形成されている。
配線3<電極12
となっているが、
電極12≦配線3
とすることが好ましい。特に、
電極12<配線3
となる場合には、配線3の抵抗値が小さくなるばかりか、強度が増すので断線が防止される。
図6A〜図7Cは、第2の前提技術に係る半導体装置の製造方法を説明する図である。本技術は、第1の前提技術と比べて、図3A以降の工程において異なり、図2Eまでの工程は第1の前提技術と同様である。したがって、図6Aに示すウエーハ110、電極112、樹脂層114、クローム(Cr)層116、銅(Cu)層120、レジスト層122及び台座124は、図2Eに示すウエーハ10、電極12、樹脂層14、クローム(Cr)層16、銅(Cu)層20、レジスト層22及び台座124と同様であり、製造方法も図1A〜図2Eに示すものと同様のため、説明を省略する。
図8A〜図9Dは、第3の前提技術に係る半導体装置の製造方法を説明する図である。
図10は、第4の前提技術に係る半導体装置の製造方法を説明する図である。
図11A〜図12Cは、第5の前提技術に係る半導体装置の製造方法を説明する図である。
図13A〜図13Dは、第6の前提技術に係る半導体装置の製造方法を説明する図である。本技術では応力緩和層にポリイミド板を選択した。ポリイミドはヤング率が低く応力緩和層として好適な部材であるからである。なおそのほかにも例えばプラスチック板やガラスエポキシ系等の複合板を用いてもよい。この場合、実装基板と同材料を用いると熱膨張係数に差がなくなり好ましい。特に今日では実装基板としてプラスチック基板が多いため、プラスチック板を応力緩和層に用いることは有効である。
本発明は、上記技術をさらに改良すべくなされたもので、以下、本発明の好適な実施の形態について図面を参照して説明する。
次に、図15に示す半導体装置190は、アルミパッド192と、応力緩和層194の上に設けられたハンダボール196と、を接続する配線200に特徴を有する。配線200は、第1の前提技術等にて選択した配線材料のうちいずれのものを用いても良い。この配線200は、じゃばら部200aを有する。じゃばら部200aは、図14Dに示すように、配線の中が空洞(スリット)になっている状態であり、通常の配線をはさんで複数のじゃばら部200aが連続形成される。このじゃばら部200aは、屈曲する配線184よりも応力吸収性に優れている。このじゃばら部200aを有することで、半導体チップ上で配線200にクラックが生じたり、アルミパッド192やその他の能動素子へのダメージがなくなり、半導体装置としての信頼性が向上する。また、じゃばら部200aは、一本の配線に設けられるため、応力吸収構造のためのスペースは微細なもので足りる。これによって、CSPのカテゴリーを逸脱しないように、半導体装置の小型化を維持しつつ、設計の自由度を向上することができる。なお、本実施形態において、じゃばら部200aは平面方向に対しての例であるが、これを厚み方向に設けても良い。
図16〜図20は、本発明に係る第3実施形態を示す図である。図16は、本実施形態に係る半導体装置の断面を示す図である。この半導体装置300は、半導体チップ302上に複数層(4層)構造を有し、表面がソルダレジスト350にて保護されるものである。なお、本実施形態においても、他の実施形態及び前提技術について説明した材料や製造方法などを適用することができる。
本発明は、上記実施形態に限定されるものではなく、種々の変形が可能である。例えば、上記実施形態は、半導体装置に本発明を適用したが、能動部品か受動部品かを問わず、種々の面実装用の電子部品に本発明を適用することができる。
Claims (4)
- 電極の形成されたウエーハを用意する工程と、
前記電極の少なくとも一部を避けて前記ウエーハにヤング率が1×1010Pa以下であり、傾斜部および窪み部を有する樹脂層を設ける工程と、
前記電極から前記樹脂層の上にかけ、前記傾斜部および前記窪み部の上に位置する部分を有する導通部を形成する工程と、
前記樹脂層の上方で前記導通部に接続される外部電極を形成する工程と、
前記ウエーハを個々の個片に切断する工程と、
を有し、
前記導通部を形成する工程では、
前記導通部を、前記樹脂層の上で平面方向に屈曲する第1の屈曲部を有するように形成し、
前記導通部の前記樹脂層の上に形成された部分が、前記樹脂層の前記平面方向と直交する方向における断面形状において屈曲する第2の屈曲部を少なくとも3つ有するように形成する、半導体装置の製造方法。 - 電極の形成されたウエーハを用意する工程と、
前記電極の少なくとも一部を避けて前記ウエーハにヤング率が1×1010Pa以下であり、傾斜部および窪み部を有する樹脂層を設ける工程と、
前記電極から前記樹脂層の上にかけ、前記傾斜部および前記窪み部の上に位置する部分を有する導通部を形成する工程と、
前記樹脂層の上方で前記導通部に接続される外部電極を形成する工程と、
前記ウエーハを個々の個片に切断する工程と、
を有し、
前記導通部を形成する工程では、
前記導通部を、前記樹脂層の上で平面方向に屈曲する第1の屈曲部を有するように形成し、
前記導通部の前記樹脂層の上に形成された部分が、前記樹脂層の前記平面方向と直交する方向における断面形状において屈曲する第2の屈曲部を少なくとも3つ有するように形
成する、電子部品の製造方法。 - 電極を有する半導体チップと、
前記半導体チップの上にて前記電極の少なくとも一部を避けるように設けられ、ヤング率が1×1010Pa以下であり、傾斜部および窪み部を有する樹脂層と、
前記電極から前記樹脂層の上にかけて形成され、前記傾斜部および前記窪み部の上に位置する部分を有する導通部と、
前記樹脂層の上方に位置する前記導通部に形成される外部電極と、
を有し、
前記導通部は、前記樹脂層上で平面方向に屈曲する第1の屈曲部を有し、
前記導通部の前記樹脂層の上に形成された部分が、前記樹脂層の前記平面方向と直交する方向における断面形状において屈曲する第2の屈曲部を少なくとも3つ有する、半導体装置。 - 電極を有するチップ部と、
前記電極の少なくとも一部を避けるように設けられ、ヤング率が1×1010Pa以下であり、傾斜部および窪み部を有する樹脂層と、
前記電極から前記樹脂層の上にかけて形成され、前記傾斜部および前記窪み部の上に位置する部分を有する導通部と、
前記樹脂層の上方に位置する前記導通部に形成される外部電極と、
を有し、
前記導通部は、前記樹脂層上で平面方向に屈曲する第1の屈曲部を有し、
前記導通部の前記樹脂層の上に形成された部分が、前記樹脂層の前記平面方向と直交する方向における断面形状において屈曲する第2の屈曲部を少なくとも3つ有する、電子部品。
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US5702980A (en) * | 1996-03-15 | 1997-12-30 | Taiwan Semiconductor Manufacturing Company Ltd | Method for forming intermetal dielectric with SOG etchback and CMP |
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TW459323B (en) * | 1996-12-04 | 2001-10-11 | Seiko Epson Corp | Manufacturing method for semiconductor device |
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1997
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- 1997-12-02 TW TW090100512A patent/TW571373B/zh not_active IP Right Cessation
- 1997-12-04 WO PCT/JP1997/004438 patent/WO1998025298A1/ja active IP Right Grant
- 1997-12-04 JP JP52348998A patent/JP3981710B2/ja not_active Expired - Fee Related
- 1997-12-04 US US09/117,526 patent/US6255737B1/en not_active Expired - Lifetime
- 1997-12-04 KR KR10-1998-0705997A patent/KR100501662B1/ko not_active IP Right Cessation
- 1997-12-04 AU AU51364/98A patent/AU5136498A/en not_active Abandoned
- 1997-12-04 CN CNB971920338A patent/CN100380612C/zh not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
TW571373B (en) | 2004-01-11 |
KR19990082268A (ko) | 1999-11-25 |
US20090174068A1 (en) | 2009-07-09 |
JP3981710B2 (ja) | 2007-09-26 |
US7183189B2 (en) | 2007-02-27 |
JP5278716B2 (ja) | 2013-09-04 |
JP2012169679A (ja) | 2012-09-06 |
JP5445732B2 (ja) | 2014-03-19 |
US6255737B1 (en) | 2001-07-03 |
KR100501662B1 (ko) | 2005-11-14 |
US6608389B1 (en) | 2003-08-19 |
TW459323B (en) | 2001-10-11 |
CN100380612C (zh) | 2008-04-09 |
US8384213B2 (en) | 2013-02-26 |
WO1998025298A1 (fr) | 1998-06-11 |
JP2009004815A (ja) | 2009-01-08 |
AU5136498A (en) | 1998-06-29 |
JP2008294481A (ja) | 2008-12-04 |
US20030213981A1 (en) | 2003-11-20 |
US7521796B2 (en) | 2009-04-21 |
CN1210622A (zh) | 1999-03-10 |
US20060249843A1 (en) | 2006-11-09 |
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