JPS641257A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS641257A JPS641257A JP15598787A JP15598787A JPS641257A JP S641257 A JPS641257 A JP S641257A JP 15598787 A JP15598787 A JP 15598787A JP 15598787 A JP15598787 A JP 15598787A JP S641257 A JPS641257 A JP S641257A
- Authority
- JP
- Japan
- Prior art keywords
- bumps
- electrodes
- layer
- passivation film
- prevent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Formation Of Insulating Films (AREA)
- Wire Bonding (AREA)
Abstract
PURPOSE: To prevent a passivation film from cracking by providing a coating film of energy beam shielding resin on a region except a region formed with electrodes, providing wiring conductors extended along the coating film from the electrodes, and forming bumps on separate region from the region formed with the electrodes.
CONSTITUTION: Bumps 21 are displaced with respect to electrodes 24, and a polyimide layer 27 is interposed between the bumps 21 and a passivation film 26. A force F is acted on the bumps 21 in case of mounting a device 20, and thermal stresses σ due to thermal hysteresis thereafter are operated reversely to each other. The force F is alleviated by the layer 27, and thermal stress σis absorbed by the deformation of the layer 27. Alpha-pays 30 irradiated from the bumps 21 are shielded from the layer 27 by the layers 27, 28. Thus, it can effectively prevent the passivation film from cracking and prevent a software error from occurring.
COPYRIGHT: (C)1989,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-155987A JPH011257A (en) | 1987-06-23 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-155987A JPH011257A (en) | 1987-06-23 | semiconductor equipment |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS641257A true JPS641257A (en) | 1989-01-05 |
JPH011257A JPH011257A (en) | 1989-01-05 |
Family
ID=
Cited By (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05235000A (en) * | 1991-12-17 | 1993-09-10 | Internatl Business Mach Corp <Ibm> | Apparatus and method for reducing alpha particles |
WO1998025297A1 (en) * | 1996-12-04 | 1998-06-11 | Seiko Epson Corporation | Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment |
WO1998025298A1 (en) * | 1996-12-04 | 1998-06-11 | Seiko Epson Corporation | Semiconductor device, method for manufacture thereof, circuit board, and electronic equipment |
EP1005082A4 (en) * | 1998-03-27 | 2001-08-16 | Seiko Epson Corp | Semiconductor device, method for manufacturing the same, circuit board and electronic apparatus |
EP0991119A4 (en) * | 1997-06-06 | 2002-01-23 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for manufacturing the same |
US6518665B1 (en) * | 1997-07-11 | 2003-02-11 | Delaware Capital Formation, Inc. | Enhanced underfill adhesion |
JP2005217445A (en) * | 1996-12-04 | 2005-08-11 | Seiko Epson Corp | Production process of semiconductor device |
CN100440472C (en) * | 1996-12-04 | 2008-12-03 | 精工爱普生株式会社 | Semiconductor device and method of making the same, circuit board, and electronic instrument |
US8917532B2 (en) | 2011-10-03 | 2014-12-23 | Invensas Corporation | Stub minimization with terminal grids offset from center of package |
US8981547B2 (en) | 2011-10-03 | 2015-03-17 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US9070423B2 (en) | 2013-06-11 | 2015-06-30 | Invensas Corporation | Single package dual channel memory with co-support |
US9224431B2 (en) | 2011-10-03 | 2015-12-29 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals |
US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
US9281271B2 (en) | 2011-10-03 | 2016-03-08 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals having modulo-x symmetry in assemblies without wirebonds to package substrate |
US9287216B2 (en) | 2011-07-12 | 2016-03-15 | Invensas Corporation | Memory module in a package |
US9287195B2 (en) | 2011-10-03 | 2016-03-15 | Invensas Corporation | Stub minimization using duplicate sets of terminals having modulo-x symmetry for wirebond assemblies without windows |
US9368477B2 (en) | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
US9373565B2 (en) | 2011-10-03 | 2016-06-21 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
US9377824B2 (en) | 2011-10-03 | 2016-06-28 | Invensas Corporation | Microelectronic assembly including memory packages connected to circuit panel, the memory packages having stub minimization for wirebond assemblies without windows |
US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57154858A (en) * | 1981-03-20 | 1982-09-24 | Hitachi Ltd | Method for formation of electrode |
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57154858A (en) * | 1981-03-20 | 1982-09-24 | Hitachi Ltd | Method for formation of electrode |
Cited By (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05235000A (en) * | 1991-12-17 | 1993-09-10 | Internatl Business Mach Corp <Ibm> | Apparatus and method for reducing alpha particles |
US7511362B2 (en) | 1996-12-04 | 2009-03-31 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
JP4513973B2 (en) * | 1996-12-04 | 2010-07-28 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
CN100380612C (en) * | 1996-12-04 | 2008-04-09 | 精工爱普生株式会社 | Semiconductor device, method for manufacturing thereof, circuit board, and electronic equipment |
CN100440472C (en) * | 1996-12-04 | 2008-12-03 | 精工爱普生株式会社 | Semiconductor device and method of making the same, circuit board, and electronic instrument |
US7183189B2 (en) | 1996-12-04 | 2007-02-27 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
US8384213B2 (en) | 1996-12-04 | 2013-02-26 | Seiko Epson Corporation | Semiconductor device, circuit board, and electronic instrument |
US6475896B1 (en) | 1996-12-04 | 2002-11-05 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
US8115284B2 (en) | 1996-12-04 | 2012-02-14 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board and electronic instrument |
US6608389B1 (en) | 1996-12-04 | 2003-08-19 | Seiko Epson Corporation | Semiconductor device with stress relieving layer comprising circuit board and electronic instrument |
US6730589B2 (en) | 1996-12-04 | 2004-05-04 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
US7888260B2 (en) | 1996-12-04 | 2011-02-15 | Seiko Epson Corporation | Method of making electronic device |
JP2005217445A (en) * | 1996-12-04 | 2005-08-11 | Seiko Epson Corp | Production process of semiconductor device |
WO1998025297A1 (en) * | 1996-12-04 | 1998-06-11 | Seiko Epson Corporation | Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment |
US6255737B1 (en) | 1996-12-04 | 2001-07-03 | Seiko Epson Corporation | Semiconductor device and method of making the same, circuit board, and electronic instrument |
US7842598B2 (en) | 1996-12-04 | 2010-11-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
US7470979B2 (en) | 1996-12-04 | 2008-12-30 | Seiko Epson Corporation | Electronic component and semiconductor device, method of making the same and method of mounting the same, circuit board, and electronic instrument |
JP2009021620A (en) * | 1996-12-04 | 2009-01-29 | Seiko Epson Corp | Method of mounting electronic component |
WO1998025298A1 (en) * | 1996-12-04 | 1998-06-11 | Seiko Epson Corporation | Semiconductor device, method for manufacture thereof, circuit board, and electronic equipment |
US7521796B2 (en) | 1996-12-04 | 2009-04-21 | Seiko Epson Corporation | Method of making the semiconductor device, circuit board, and electronic instrument |
US6812573B2 (en) | 1997-06-06 | 2004-11-02 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for manufacturing the same |
EP0991119A4 (en) * | 1997-06-06 | 2002-01-23 | Matsushita Electric Ind Co Ltd | Semiconductor device and method for manufacturing the same |
US6518665B1 (en) * | 1997-07-11 | 2003-02-11 | Delaware Capital Formation, Inc. | Enhanced underfill adhesion |
EP1005082A4 (en) * | 1998-03-27 | 2001-08-16 | Seiko Epson Corp | Semiconductor device, method for manufacturing the same, circuit board and electronic apparatus |
US6414390B2 (en) | 1998-03-27 | 2002-07-02 | Seiko Epson Corporation | Semiconductor device and method of manufacturing the same, circuit board and electronic instrument |
US9287216B2 (en) | 2011-07-12 | 2016-03-15 | Invensas Corporation | Memory module in a package |
US9508629B2 (en) | 2011-07-12 | 2016-11-29 | Invensas Corporation | Memory module in a package |
US8981547B2 (en) | 2011-10-03 | 2015-03-17 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US9377824B2 (en) | 2011-10-03 | 2016-06-28 | Invensas Corporation | Microelectronic assembly including memory packages connected to circuit panel, the memory packages having stub minimization for wirebond assemblies without windows |
US9224431B2 (en) | 2011-10-03 | 2015-12-29 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals |
US10692842B2 (en) | 2011-10-03 | 2020-06-23 | Invensas Corporation | Microelectronic package including microelectronic elements having stub minimization for wirebond assemblies without windows |
US9281271B2 (en) | 2011-10-03 | 2016-03-08 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals having modulo-x symmetry in assemblies without wirebonds to package substrate |
US10643977B2 (en) | 2011-10-03 | 2020-05-05 | Invensas Corporation | Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows |
US9287195B2 (en) | 2011-10-03 | 2016-03-15 | Invensas Corporation | Stub minimization using duplicate sets of terminals having modulo-x symmetry for wirebond assemblies without windows |
US9214455B2 (en) | 2011-10-03 | 2015-12-15 | Invensas Corporation | Stub minimization with terminal grids offset from center of package |
US9373565B2 (en) | 2011-10-03 | 2016-06-21 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
US9679838B2 (en) | 2011-10-03 | 2017-06-13 | Invensas Corporation | Stub minimization for assemblies without wirebonds to package substrate |
US9423824B2 (en) | 2011-10-03 | 2016-08-23 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US10090280B2 (en) | 2011-10-03 | 2018-10-02 | Invensas Corporation | Microelectronic package including microelectronic elements having stub minimization for wirebond assemblies without windows |
US10032752B2 (en) | 2011-10-03 | 2018-07-24 | Invensas Corporation | Microelectronic package having stub minimization using symmetrically-positioned duplicate sets of terminals for wirebond assemblies without windows |
US9496243B2 (en) | 2011-10-03 | 2016-11-15 | Invensas Corporation | Microelectronic assembly with opposing microelectronic packages each having terminals with signal assignments that mirror each other with respect to a central axis |
US8917532B2 (en) | 2011-10-03 | 2014-12-23 | Invensas Corporation | Stub minimization with terminal grids offset from center of package |
US9515053B2 (en) | 2011-10-03 | 2016-12-06 | Invensas Corporation | Microelectronic packaging without wirebonds to package substrate having terminals with signal assignments that mirror each other with respect to a central axis |
US9530458B2 (en) | 2011-10-03 | 2016-12-27 | Invensas Corporation | Stub minimization using duplicate sets of signal terminals |
US9679876B2 (en) | 2011-10-03 | 2017-06-13 | Invensas Corporation | Microelectronic package having at least two microelectronic elements that are horizontally spaced apart from each other |
US9368477B2 (en) | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
US9460758B2 (en) | 2013-06-11 | 2016-10-04 | Invensas Corporation | Single package dual channel memory with co-support |
US9070423B2 (en) | 2013-06-11 | 2015-06-30 | Invensas Corporation | Single package dual channel memory with co-support |
US9281296B2 (en) | 2014-07-31 | 2016-03-08 | Invensas Corporation | Die stacking techniques in BGA memory package for small footprint CPU and memory motherboard design |
US9691437B2 (en) | 2014-09-25 | 2017-06-27 | Invensas Corporation | Compact microelectronic assembly having reduced spacing between controller and memory packages |
US10026467B2 (en) | 2015-11-09 | 2018-07-17 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
US9679613B1 (en) | 2016-05-06 | 2017-06-13 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
US9928883B2 (en) | 2016-05-06 | 2018-03-27 | Invensas Corporation | TFD I/O partition for high-speed, high-density applications |
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