JPS61239656A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61239656A JPS61239656A JP60080773A JP8077385A JPS61239656A JP S61239656 A JPS61239656 A JP S61239656A JP 60080773 A JP60080773 A JP 60080773A JP 8077385 A JP8077385 A JP 8077385A JP S61239656 A JPS61239656 A JP S61239656A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating material
- semiconductor device
- input
- output electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、多層構造をもつ半導体装置に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device having a multilayer structure.
従来半導体装置では、第２図の如く入出力電極、１：
端子群２は、素子領域乙の外側に位置していた。In a conventional semiconductor device, input/output electrodes 1:
Terminal group 2 was located outside element area B.
それは、本来の目的である探針検査と外部との接続に゛
よる衝撃より素子領域を保護するためである。This is to protect the element area from impact caused by the probe inspection, which is the original purpose, and connection with the outside.
また多層構造をもつ半導体装置では、第４図の］
如く１層目の金属等配線４の上に有機系樹脂絶縁材料ま
たは無機系絶縁材料５０１層で層間絶縁しフォトリソグ
ラフィ工程により所定の位置に開口部６を設け、更に開
口部６により１層目金属等配線４との接続をとった２層
目の金属等配線７を形 ”成し交差配線等を実現し
でいる。In addition, in a semiconductor device with a multilayer structure,
As described above, the first layer of metal wiring 4 is interlayer insulated with 501 layers of organic resin insulating material or inorganic insulating material, and openings 6 are formed at predetermined positions by a photolithography process. A second layer of metal wiring 7 that is connected to the metal wiring 4 is formed to realize cross wiring and the like.
一方、素子領域を除く入出力電極端子群の配置されてい
る領域は、通常半導体装置面積の２０〜３０％を占めて
おり何らかの方法で素子領域上に。On the other hand, the area where the input/output electrode terminal group is arranged, excluding the element area, usually occupies 20 to 30% of the area of the semiconductor device, and is formed on the element area by some method.
配置することができれば半導体装置面積を縮小させるこ
とができ収率を増大させることができる。If it can be arranged, the area of the semiconductor device can be reduced and the yield can be increased.
しかし従来の技術では、入出力電極端子群を素子領域上
へ配置することは形態上可能であるが、入出力電極端子
群の本来の目的である探針検査や外部との接続による衝
撃により層間絶縁層の破壊に ・到り信頼性面での低
下を生ずる。However, with conventional technology, although it is physically possible to arrange the input/output electrode terminal group on the element area, the original purpose of the input/output electrode terminal group is probe inspection or impact caused by connection with the outside can cause interlayer separation. This leads to breakdown of the insulating layer, resulting in a decrease in reliability.
従来の層間絶縁層を用いて多層構造を形成し、入出力端
子電極群を素子領域上に配置させることは、形態上は可
能であった。しかしながら探針検査や外部との接続時に
キズ、クランク、歪み等を生じ信頼性を低下させる等の
問題があった。Formally, it was possible to form a multilayer structure using conventional interlayer insulating layers and arrange the input/output terminal electrode group on the element region. However, there have been problems such as scratches, cranks, distortions, etc. occurring during probe inspection and connection with the outside, reducing reliability.
本発明の第１の目的は、かかる点に着目し、探針検査や
外部との接続等による衝撃に耐えうろ層間絶縁層を提供
するものでル〕る。A first object of the present invention is to focus on this point and provide an interlayer insulating layer that can withstand shocks caused by probe inspection, external connections, and the like.
第２の目的は、この層間絶縁層を用いて多層構造を形成
し、入出力電極端子群を素子領域上へ配置することによ
って面積を縮小１−ることができる半導体装置を提供す
るものである。The second object is to provide a semiconductor device whose area can be reduced by forming a multilayer structure using this interlayer insulating layer and arranging a group of input/output electrode terminals on the element region. .
本発明は、この問題を解決するために従来の層間絶縁層
のかわりに有機系樹脂絶縁材料と無機系絶縁材料の２層
からなる層間絶縁膜を用いることにより実現した。In order to solve this problem, the present invention was realized by using an interlayer insulating film made of two layers of an organic resin insulating material and an inorganic insulating material in place of the conventional interlayer insulating layer.
この２層からなる層間絶縁層は、以下のような作用をす
る。下層の有機系樹脂絶縁材料を回転塗布及び硬化させ
る。これにより半導体素子表面のｊ 段差や突起等
の凸凹を吸収することができ、また衝撃を緩和すること
ができる。この有機系樹脂絶縁層だけでは、硬度的に不
足である。上層の無機系絶縁層により、下層の足らない
硬度を補うことができろ。This interlayer insulating layer consisting of two layers functions as follows. The lower layer organic resin insulating material is spin-coated and cured. This makes it possible to absorb irregularities such as j steps and protrusions on the surface of the semiconductor element, and also to reduce impact. This organic resin insulating layer alone is insufficient in hardness. The upper inorganic insulating layer can compensate for the lack of hardness in the lower layer.
この上下２層の絶縁層を層間絶縁層とじ、用いることに
より、探針検査や外部との接続等による衝撃に剛え５る
構造をもたせることができる。By using these two upper and lower insulating layers as an interlayer insulating layer, it is possible to provide a structure that can withstand impacts caused by probe inspection, external connection, etc.
以下本発明の実施例を図面に基づいて詳述する。 Embodiments of the present invention will be described in detail below based on the drawings.
第１図は、本発明の１実施例を示す断面図である。FIG. 1 is a sectional view showing one embodiment of the present invention.
第１図に示す如く半導体基板１上に形成された素子の上
にポリイミド系樹脂層８を０５μｍ以上回転塗布し、熱
により硬化させ、更にその一１＝ヘスバッタリングやプ
ラズマＣＶ Ｉ）等の手段でＳｉｎ、、層９を１μｍ以
」二形成し、１層目金属等配線４」二にフォトリングラ
フィにより開けられた開口部６を通して１層目金属等配
線４と接続をとった２層目金属等配線７により、素子領
域上に入出力電極端子群２を終端せしめている。As shown in FIG. 1, a polyimide resin layer 8 is spin-coated to a thickness of 05 μm or more on an element formed on a semiconductor substrate 1, cured by heat, and further coated with Hess battering, plasma CV I), etc. A layer 9 of 1 .mu.m or more is formed by means of a method, and a connection is made to the first layer metal wiring 4 through an opening 6 made by photolithography in the first layer metal wiring 4. The input/output electrode terminal group 2 is terminated on the element area by the metal wiring 7.
以上詳述した如く、本発明によれば従来の方法では非常
に難しいとされていた半導体装置の素子領域上への入出
力電極端子群の配置を可能とし、また探針検査、外部と
の接続による衝撃にも耐えうる構造となり、これにより
半導体装置面積の２０〜３０％の縮小が実現でき収率の
増大が行える。As described in detail above, according to the present invention, it is possible to arrange input/output electrode terminal groups on the element area of a semiconductor device, which was considered extremely difficult with conventional methods, and also to facilitate probe inspection and external connection. As a result, the area of the semiconductor device can be reduced by 20 to 30%, and the yield can be increased.
第１図は、本発明の半導体装置の断面図、第２゛ 図は
、従来の半導体装置の平面図、第３図はその断面図であ
る。
第４図は、従来の多層構造をもつ半導体装置の断面図で
ある。
１・・・・・・半導体基板、
２・・・・・入出力電極端子、
３・・・・・・素子領域、
４・・・・・・１層目金属等配線、
５・・・・・層間絶縁層、
６・・・・・・開口部、
７・・・・・・２層目金属等配線、
８・・・・有機系樹脂絶縁層、
９・・・・・無機系絶縁層。
特許出願人 シチズン時計株式会社
第１図
第２図
９ＡＯ−FIG. 1 is a sectional view of a semiconductor device of the present invention, FIG. 2 is a plan view of a conventional semiconductor device, and FIG. 3 is a sectional view thereof. FIG. 4 is a sectional view of a conventional semiconductor device having a multilayer structure. 1... Semiconductor substrate, 2... Input/output electrode terminal, 3... Element area, 4... First layer metal wiring, etc., 5...・Interlayer insulating layer, 6...Opening, 7...Second layer metal wiring, 8...Organic resin insulating layer, 9...Inorganic insulating layer . Patent applicant Citizen Watch Co., Ltd. Figure 1 Figure 2 9AO-
Claims (1)
層に有機系樹脂絶縁材料、上層に無機絶縁材料の２層を
用いて層間絶縁層を形成し、入出力電極端子群を素子領
域上へ配置したことを特徴とする半導体装置。In a semiconductor device having a multilayer structure, an interlayer insulating film is formed using two layers: an organic resin insulating material in the lower layer and an inorganic insulating material in the upper layer, and the input/output electrode terminal group is placed above the element area. A semiconductor device characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60080773A JPS61239656A (en) | 1985-04-16 | 1985-04-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60080773A JPS61239656A (en) | 1985-04-16 | 1985-04-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61239656A true JPS61239656A (en) | 1986-10-24 |
Family
ID=13727740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60080773A Pending JPS61239656A (en) | 1985-04-16 | 1985-04-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61239656A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01280337A (en) * | 1988-05-06 | 1989-11-10 | Nec Corp | Semiconductor integrated circuit device |
| US4984061A (en) * | 1987-05-15 | 1991-01-08 | Kabushiki Kaisha Toshiba | Semiconductor device in which wiring layer is formed below bonding pad |
| US5317185A (en) * | 1990-11-06 | 1994-05-31 | Motorola, Inc. | Semiconductor device having structures to reduce stress notching effects in conductive lines and method for making the same |
| JP2007019215A (en) * | 2005-07-07 | 2007-01-25 | Sanken Electric Co Ltd | Semiconductor device and its manufacturing method |
| JP2008252115A (en) * | 2008-05-19 | 2008-10-16 | Sanken Electric Co Ltd | Semiconductor device and manufacturing method thereof |
-
1985
- 1985-04-16 JP JP60080773A patent/JPS61239656A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4984061A (en) * | 1987-05-15 | 1991-01-08 | Kabushiki Kaisha Toshiba | Semiconductor device in which wiring layer is formed below bonding pad |
| JPH01280337A (en) * | 1988-05-06 | 1989-11-10 | Nec Corp | Semiconductor integrated circuit device |
| US5317185A (en) * | 1990-11-06 | 1994-05-31 | Motorola, Inc. | Semiconductor device having structures to reduce stress notching effects in conductive lines and method for making the same |
| JP2007019215A (en) * | 2005-07-07 | 2007-01-25 | Sanken Electric Co Ltd | Semiconductor device and its manufacturing method |
| US7847316B2 (en) | 2005-07-07 | 2010-12-07 | Sanken Electric Co., Ltd. | Semiconductor device and its manufacture |
| JP2008252115A (en) * | 2008-05-19 | 2008-10-16 | Sanken Electric Co Ltd | Semiconductor device and manufacturing method thereof |
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