JP2004063729A - Electrode structure and its forming method - Google Patents

Electrode structure and its forming method Download PDF

Info

Publication number
JP2004063729A
JP2004063729A JP2002219303A JP2002219303A JP2004063729A JP 2004063729 A JP2004063729 A JP 2004063729A JP 2002219303 A JP2002219303 A JP 2002219303A JP 2002219303 A JP2002219303 A JP 2002219303A JP 2004063729 A JP2004063729 A JP 2004063729A
Authority
JP
Japan
Prior art keywords
insulating film
bump
contact hole
electrode structure
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002219303A
Other languages
Japanese (ja)
Inventor
Shinya Iijima
飯島　真也
Yoshikatsu Ishizuki
石月　義克
Masataka Mizukoshi
水越　正孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2002219303A priority Critical patent/JP2004063729A/en
Publication of JP2004063729A publication Critical patent/JP2004063729A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent cracks and delamination from occurring in an insulating film when forming a bump electrode structure and packaging an electronic component having the bump electrode structure by adopting an extremely simple means. <P>SOLUTION: In the insulating film 5, a contact hole where one portion of a pad electrode 3 is exposed is formed, and a bump 8 coming into contact with the pad electrode 3 in the contact hole is formed. The insulating film 5 has a step 5D near the edge of the bump 8, and a thinned portion 5C that goes toward the outside from the step 5D. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体デバイスなど電子部品に用いて好適な突起状電極であるバンプをもつ電極構造及びその形成方法の改良に関する。
【０００２】
【従来の技術】
図４は従来の技術を説明する為の電極構造を表す要部切断側面図であり、図に於いて、１は絶縁膜、２は最上層配線、３はパッド電極、４はＰＳＧ（ｐｈｏｓｐｈｏｓｉｌｉｃａｔｅ　ｇｌａｓｓ）からなる絶縁膜、５はポリイミドからなる絶縁膜、６はＣｕ／Ｃｒからなる密着層、７はＮｉからなるバリア層、８ははんだバンプをそれぞれ示している。
【０００３】
図４に示した電極構造を作製するには、絶縁膜１で覆われ、最上層配線２と接続されているパッド電極３をもつ基板（図示せず）に絶縁膜４を形成し、パッド電極３上の絶縁膜４にコンタクト・ホールを形成し、該コンタクト・ホール内も含め絶縁膜５を形成し、パッド電極３上の絶縁膜５にコンタクト・ホールを形成し、該開口内を含めバンプ８を載せる為の密着層６及びパッド電極３とバンプ８との反応を防ぐ為のバリア層７を形成し、その後、はんだボール或いははんだペーストをリフローしてはんだバンプ８を形成する。
【０００４】
図４に見られる電極構造の場合、バンプ８の形成時、或いは、電子部品を実装した場合、バンプ８の収縮応力に依ってポリイミドからなる絶縁膜５がバリア層７に引っ張られ、バリア層７及び密着層６のエッジ近傍に於ける絶縁膜５にクラック５Ａが発生する。
【０００５】
図５は絶縁膜にクラックが発生することを抑止した電極構造を表す要部切断側面図であり、図４に於いて用いた記号と同記号は同部分を表すか或いは同じ意味を持つものとする。
【０００６】
図５の電極構造が図４の電極構造と比較して相違するところは、密着層６をバリア層７よりも若干突出するように大き目に形成した構造とし、この構造に依って密着層６の直下に於ける応力を低減させ、クラック５Ａの発生を抑止しようとするものである。
【０００７】
然しながら、図５に見られる電極構造の場合、クラック５Ａの発生は抑止できるが、新たに絶縁層５のコンタクト・ホール側壁と密着層６との界面に応力が集中して層間剥離５Ｂを生ずることになる。
【０００８】
【発明が解決しようとする課題】
本発明では、極めて簡単な手段を採ることで、バンプ電極構造を形成する場合やバンプ電極構造をもつ電子部品を実装する場合、絶縁膜にクラックや層間剥離が発生しないようにする。
【０００９】
【課題を解決するための手段】
本発明に依る電極構造及びその形成方法に於いては、下部電極（例えばパッド電極３：図１）の一部が表出されるコンタクト・ホール（例えばコンタクト・ホール５Ｍ：図２（Ｂ））が形成され且つ該コンタクト・ホール内で下部電極とコンタクトするバンプ（例えばバンプ８：図１）が形成された絶縁膜（例えば絶縁膜５：図１）に於いて、該絶縁膜は該バンプのエッジ近傍に段差（例えば段差５Ｄ：図１）をもち且つ該段差から外方に向かう薄膜化部分（例えば薄膜化部分５Ｃ：図１）をもつことが基本になっている。
【００１０】
前記手段を採ることに依り、バンプ電極構造を形成する場合やバンプ電極構造をもつ電子部品を実装する場合、絶縁膜にクラックや層間剥離が発生することを防止することができ、そして、この場合に必要な技法は、半導体技術分野に於いて多用されている技法であるから、その実施に何らの困難性もない。
【００１１】
【発明の実施の形態】
図１は本発明の実施の形態１を説明する為の電極構造を表す要部切断側面図であり、図４に於いて用いた記号と同記号は同部分を表すか或いは同じ意味を持つものとする。
【００１２】
本発明の電極構造が、図４及び図５について説明した従来の電極構造と相違するところは、バンプ８の外周近傍に於けるポリイミドからなる絶縁膜５に薄膜化部分５Ｃが形成され、従って、段差５Ｄが生成されていることである。
【００１３】
段差５Ｄは、応力に対するバッファとなって、絶縁膜５にクラック５Ａや剥離５Ｂが発生することを抑止する役割を果たすことができる。即ち、段差５Ｄの存在で、バンプ８の近傍に於ける絶縁膜５に対するパッド電極３に依る拘束が小さくなって変形の自由度が大きくなり、応力に対して変形し易くなる為、応力を吸収することができるものである。
【００１４】
この段差５Ｄを形成するのは、極めて簡単であって、従来から多用されている半導体技術に於ける技法を用いて容易に実現することが可能であり、それには、大別して二つの方法があって、その一つは、露光量を変えて二重露光を行って現像時間を一定にする方法であり、もう一つは、二重露光は行うが露光量は同じにして現像時間を変える方法である。
【００１５】
図２及び図３は本発明の実施の形態２を説明する為の工程要所に於ける電極構造を表す要部切断側面図であり、以下、これ等の図を参照しつつ製造工程を説明する。尚、この実施の形態２は露光量を変えて二重露光する方法に関するものであり、図１に於いて用いた記号と同記号は同部分を表すか或いは同じ意味を持つものとする。
【００１６】
図２（Ａ）参照
（１）
通常の技法を適用し、基板に絶縁膜１、配線２、パッド電極３、電極３上に開口をもつＰＳＧからなる絶縁膜４を形成する。
【００１７】
（２）
ポジ型感光性ポリイミドを塗布して絶縁膜５を形成する。
【００１８】
（３）
電極３上にコンタクト・ホールを形成する為の露光マスク１１を用いて絶縁
膜５の第１回目の露光を行う。
【００１９】
図２（Ｂ）参照
（４）
絶縁膜５の現像を行ってコンタクト・ホール５Ｍを形成し、その中にパッド
電極３の一部を表出させる。
【００２０】
図３（Ａ）参照
（５）
段差を生成させる箇所から内側（パッド電極３側）を覆う露光マスク１２を用いて絶縁膜５の第２回目の露光を行う。この場合の露光量は、第１回目の露光の場合と比較して少なくする。
【００２１】
図３（Ｂ）参照
（６）
絶縁膜５の現像を行ってバンプ形成予定部分の外側を薄膜化して薄膜化部分５Ｃ並びに段差５Ｄを形成する。尚、薄膜化部分５Ｃの厚さは当初の絶縁膜５
の厚さの略１／２である。
【００２２】
（７）
この後、密着層６、バリア層７、バンプ８を形成して完成させる。
【００２３】
次に、実施の形態３、即ち、露光量は同じにして現像時間を変える方法について説明するが、実施の形態２と比較すると、ポジ型感光性ポリイミドからなる絶縁膜５に対する露光量と露光時間とが相違するのみで、二重露光を行う点では同じであり、従って、工程を表す図として図２及び図３を用いる。
【００２４】
実施の形態３では、実施の形態２に於いて、図２（Ａ）について説明した工程（３）に於ける第１回目の露光、図２（Ｂ）について説明した工程（４）に於ける現像のそれぞれについて設定した各条件は全く同じであるが、図３（Ａ）について説明した工程（５）に於ける第２回目の露光は、第１回目と同じ露光量の露光を行い、そして、図３（Ｂ）について説明した工程（６）に於ける現像の時間よりも少ない時間で現像を行って、絶縁膜５に於ける膜厚の略１／２を除去し、実施の形態２と同様の薄膜化部分５Ｃと段差５Ｄを実現することができる。
【００２５】
実施の形態２及び実施の形態３に依れば、バンプ８を形成した後、絶縁膜５にクラック５Ａや剥離５Ｃが発生することはない。
【００２６】
次に、実施の形態２及び実施の形態３に対応する具体的実施例について説明する。
実施例１
ポジ型感光性ポリイミドを用い、露光量を変えた二重露光に依って段差を形成する例（実施の形態２に対応）。
【００２７】
ＰＳＧからなる絶縁膜４まで形成したシリコン・デバイスに於けるＣｕからなるパッド電極３を含めた全面にポジ型感光性ポリイミドであるＲＮ−９０２（日産化学の商品名）を１５００〔ｒｐｍ〕×２０〔ｓｅｃ〕でスピン・コート（膜厚条件は１０〔μｍ〕）し、ホット・プレートで８０〔℃〕、２０〔分〕の仮乾燥を行い、露光マスクを用いて５００〔ｍＪ／ｃｍ２　〕の露光量で紫外線露光を行い、現像液であるＮＭＤ−３（東京応化の商品名）で約５〔分〕間のディップ現像を行ってコンタクト・ホールを形成した。
【００２８】
別の露光マスクを用いて段差形成予定部分の外側、即ち、薄膜化する部分に対して１００〔ｍＪ／ｃｍ２　〕の露光量で紫外線露光を行い、現像液ＮＭＤ−３を用いて約５〔分〕間のディップ現像を行って約５〔μｍ〕のポリイミドを溶解して薄膜化部分５Ｃ及び段差５Ｄを生成した。
【００２９】
ポリイミドＲＮ−９０２からなる絶縁膜５を３５０〔℃〕でキュアーしてから開口５Ｍ内を含めた絶縁膜５の厚い部分にＣｒ／Ｃｕ／Ｎｉからなるバンプ搭載層（Ｃｒ／Ｃｕ：密着層６、Ｎｉ：バリア層７）を形成し、Ｓｎ−Ａｇはんだを２２０〔℃〕の温度でリフローしてバンプ８を形成した。
【００３０】
この際、絶縁膜５にクラック５Ａや層間剥離５Ｂは発生せず、また、このシリコン・デバイスを基板に実装したところ、同じく、バンプ８の近傍に於いて、絶縁膜５にクラック５Ａや層間剥離５Ｂは発生せず、良好な接合を行うことができた。
【００３１】
実施例２
ポジ型感光性ポリイミドを用い、現像時間を変えた二重露光に依って段差を形成する例（実施の形態３に対応）。
【００３２】
ＰＳＧからなる絶縁膜４まで形成したシリコン・デバイスに於けるＣｕからなるパッド電極３を含めた全面にポジ型感光性ポリイミドであるＲＮ−９０２（日産化学の商品名）を１５００〔ｒｐｍ〕×２０〔ｓｅｃ〕でスピン・コート（膜厚条件は１０〔μｍ〕）し、ホット・プレートで８０〔℃〕、２０〔分〕の仮乾燥を行い、露光マスクを用いて５００〔ｍＪ／ｃｍ２　〕の露光量で紫外線露光を行い、現像液であるＮＭＤ−３（東京応化の商品名）で約５〔分〕間のディップ現像を行ってコンタクト・ホールを形成した。
【００３３】
別の露光マスクを用いて段差形成予定部分の外側、即ち、薄膜化する部分に対して５００〔ｍＪ／ｃｍ２　〕の露光量で紫外線露光を行い、現像液ＮＭＤ−３を用いて約２〔分〕間のディップ現像を行って約５〔μｍ〕のポリイミドを溶解して薄膜化部分５Ｃ及び段差５Ｄを生成した。
【００３４】
ポリイミドＲＮ−９０２からなる絶縁膜５を３５０〔℃〕でキュアーしてから開口５Ｍ内を含めた絶縁膜５の厚い部分にＣｒ／Ｃｕ／Ｎｉからなるバンプ搭載層（Ｃｒ／Ｃｕ：密着層６、Ｎｉ：バリア層７）を形成し、Ｓｎ−Ａｇはんだを２２０〔℃〕の温度でリフローしてバンプ８を形成した。
【００３５】
この際、絶縁膜５にクラック５Ａや層間剥離５Ｂは発生せず、また、このシリコン・デバイスを基板に実装したところ、同じく、バンプ８の近傍に於いて、絶縁膜５にクラック５Ａや層間剥離５Ｂは発生せず、良好な接合を行うことができた。
【００３６】
【発明の効果】
本発明に依る電極構造及びその形成方法に於いては、下部電極の一部が表出されるコンタクト・ホールが形成され且つ該コンタクト・ホール内で下部電極とコンタクトするバンプが形成された絶縁膜に於いて、該絶縁膜は該バンプのエッジ近傍に段差をもち且つ該段差から外方に向かう薄膜化部分をもつように形成されることが基本になっている。
【００３７】
前記構成を採ることに依り、バンプ電極構造を形成する場合やバンプ電極構造をもつ電子部品を実装する場合、絶縁膜にクラックや剥離が発生することを防止することができ、そして、この場合に必要な技法は、半導体技術分野に於いて多用されている技法であるから、その実施に何らの困難性もない。
【図面の簡単な説明】
【図１】本発明の実施の形態１を説明する為の電極構造を表す要部切断側面図である。
【図２】本発明の実施の形態２を説明する為の工程要所に於ける電極構造を表す要部切断側面図である。
【図３】本発明の実施の形態２を説明する為の工程要所に於ける電極構造を表す要部切断側面図である。
【図４】従来の技術を説明する為の電極構造を表す要部切断側面図である。
【図５】絶縁膜にクラックが発生することを抑止した電極構造を表す要部切断側面図である。
【符号の説明】
１　絶縁膜
２　最上層配線
３　パッド電極
４　ＰＳＧからなる絶縁膜
５　ポリイミドからなる絶縁膜
５Ａ　クラック
５Ｂ　層間剥離
５Ｃ　薄膜化部分
５Ｄ　段差
５Ｍ　コンタクト・ホール
６　Ｃｕ／Ｃｒからなる密着層
７　Ｎｉからなるバリア層
８　はんだバンプ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electrode structure having a bump, which is a protruding electrode suitable for use in an electronic component such as a semiconductor device, and an improvement in a method for forming the same.
[0002]
[Prior art]
FIG. 4 is a cutaway side view of a main part showing an electrode structure for explaining a conventional technique. In the figure, reference numeral 1 denotes an insulating film, 2 denotes an uppermost layer wiring, 3 denotes a pad electrode, and 4 denotes a PSG (phosphosilicate glass). ), 5 is an insulating film made of polyimide, 6 is an adhesion layer made of Cu / Cr, 7 is a barrier layer made of Ni, and 8 is a solder bump.
[0003]
In order to manufacture the electrode structure shown in FIG. 4, an insulating film 4 is formed on a substrate (not shown) having a pad electrode 3 covered with an insulating film 1 and connected to an uppermost layer wiring 2, and a pad electrode is formed. A contact hole is formed in the insulating film 4 on the pad 3, an insulating film 5 is formed in the contact hole, a contact hole is formed in the insulating film 5 on the pad electrode 3, and a bump is formed in the opening. Then, an adhesion layer 6 for mounting the pad 8 and a barrier layer 7 for preventing a reaction between the pad electrode 3 and the bump 8 are formed. Thereafter, a solder ball or a solder paste is reflowed to form a solder bump 8.
[0004]
In the case of the electrode structure shown in FIG. 4, when the bump 8 is formed, or when an electronic component is mounted, the insulating film 5 made of polyimide is pulled by the barrier layer 7 due to the shrinkage stress of the bump 8, and the barrier layer 7 In addition, a crack 5A occurs in the insulating film 5 near the edge of the adhesion layer 6.
[0005]
FIG. 5 is a cutaway side view of a main part showing an electrode structure in which cracks are suppressed from occurring in the insulating film. The same symbols and symbols used in FIG. 4 represent the same parts or have the same meanings. I do.
[0006]
The difference between the electrode structure of FIG. 5 and the electrode structure of FIG. 4 is that the adhesion layer 6 is formed to be slightly larger than the barrier layer 7, and the structure of the adhesion layer 6 depends on this structure. The purpose is to reduce the stress immediately below and suppress the occurrence of cracks 5A.
[0007]
However, in the case of the electrode structure shown in FIG. 5, cracks 5A can be suppressed, but stress is concentrated on the interface between the contact hole side wall of the insulating layer 5 and the adhesion layer 6 to cause delamination 5B. become.
[0008]
[Problems to be solved by the invention]
According to the present invention, cracks and delamination are prevented from occurring in the insulating film when a bump electrode structure is formed or when an electronic component having the bump electrode structure is mounted by employing extremely simple means.
[0009]
[Means for Solving the Problems]
In the electrode structure and the method of forming the same according to the present invention, a contact hole (for example, a contact hole 5M: FIG. 2B) in which a part of a lower electrode (for example, a pad electrode 3: FIG. 1) is exposed is formed. In an insulating film (for example, insulating film 5: FIG. 1) formed and having a bump (for example, bump 8: FIG. 1) in contact with the lower electrode in the contact hole, the insulating film is an edge of the bump. Basically, there is a step (for example, step 5D: FIG. 1) in the vicinity and a thinned portion (for example, thinned portion 5C: FIG. 1) outward from the step.
[0010]
By employing the above means, when forming a bump electrode structure or mounting an electronic component having a bump electrode structure, it is possible to prevent cracks and delamination from occurring in the insulating film, and in this case, The techniques required for this are techniques widely used in the field of semiconductor technology, and there is no difficulty in implementing them.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a cutaway side view of an essential part showing an electrode structure for explaining Embodiment 1 of the present invention, wherein the same symbols as those used in FIG. 4 represent the same parts or have the same meanings. And
[0012]
The difference between the electrode structure of the present invention and the conventional electrode structure described with reference to FIGS. 4 and 5 is that the thinned portion 5C is formed on the insulating film 5 made of polyimide near the outer periphery of the bump 8, and therefore, That is, the step 5D is generated.
[0013]
The step 5D serves as a buffer against stress, and can play a role of suppressing the occurrence of cracks 5A and peeling 5B in the insulating film 5. In other words, the presence of the step 5D reduces the constraint of the insulating film 5 in the vicinity of the bump 8 by the pad electrode 3 and increases the degree of freedom of deformation. Is what you can do.
[0014]
The formation of the step 5D is extremely simple, and can be easily realized by using a technique in semiconductor technology which has been widely used in the past. There are roughly two methods. One method is to change the exposure amount and perform double exposure to make the development time constant, and the other is to perform double exposure but change the development time while keeping the exposure amount the same. It is.
[0015]
FIGS. 2 and 3 are cutaway side views showing a main part of an electrode structure in a process step for explaining a second embodiment of the present invention. Hereinafter, a manufacturing process will be described with reference to these drawings. I do. The second embodiment relates to a method of performing double exposure by changing the exposure amount, and the same symbols as those used in FIG. 1 represent the same parts or have the same meanings.
[0016]
See FIG. 2A (1)
By applying a normal technique, an insulating film 1, a wiring 2, a pad electrode 3, and an insulating film 4 made of PSG having an opening on the electrode 3 are formed on a substrate.
[0017]
(2)
The insulating film 5 is formed by applying a positive photosensitive polyimide.
[0018]
(3)
First exposure of the insulating film 5 is performed using an exposure mask 11 for forming a contact hole on the electrode 3.
[0019]
See FIG. 2B (4)
The contact hole 5M is formed by developing the insulating film 5, and a part of the pad electrode 3 is exposed therein.
[0020]
See FIG. 3 (A) (5)
The second exposure of the insulating film 5 is performed using the exposure mask 12 that covers the inside (the pad electrode 3 side) from the position where the step is to be generated. The exposure amount in this case is smaller than that in the case of the first exposure.
[0021]
See FIG. 3 (B) (6)
The outside of the portion where the bump is to be formed is thinned by developing the insulating film 5 to form the thinned portion 5C and the step 5D. The thickness of the thinned portion 5C is the same as that of the initial insulating film 5C.
Is approximately の of the thickness.
[0022]
(7)
Thereafter, an adhesion layer 6, a barrier layer 7, and a bump 8 are formed and completed.
[0023]
Next, a description will be given of a third embodiment, that is, a method of changing the development time while maintaining the same exposure amount. However, in comparison with the second embodiment, the exposure amount and the exposure time for the insulating film 5 made of positive photosensitive polyimide are compared. 2 and 3 are the same in that double exposure is performed. Therefore, FIGS. 2 and 3 are used as diagrams showing steps.
[0024]
In the third embodiment, in the second embodiment, the first exposure in the step (3) described with reference to FIG. 2A and the step (4) described in FIG. Although the conditions set for each of the developments are exactly the same, the second exposure in the step (5) described with reference to FIG. 3A is performed with the same exposure amount as the first exposure, and The development is performed in a time shorter than the development time in the step (6) described with reference to FIG. 3B to remove approximately half of the film thickness of the insulating film 5, and the second embodiment is performed. 5C and a step 5D can be realized.
[0025]
According to the second and third embodiments, no crack 5A or peeling 5C occurs in insulating film 5 after bump 8 is formed.
[0026]
Next, specific examples corresponding to the second and third embodiments will be described.
Example 1
An example in which a step is formed by double exposure using a positive photosensitive polyimide and changing the exposure amount (corresponding to Embodiment 2).
[0027]
In the silicon device formed up to the insulating film 4 made of PSG, RN-902 (trade name of Nissan Chemical) which is a positive photosensitive polyimide is coated on the entire surface including the pad electrode 3 made of Cu at 1500 [rpm] × 20. In [sec], spin coating (film thickness condition: 10 [μm]), preliminary drying on a hot plate at 80 [° C] for 20 [minutes], and 500 [mJ / cm 2 ] using an exposure mask. UV exposure was performed at the exposure amount of, and a contact hole was formed by performing dip development for about 5 minutes with NMD-3 (trade name of Tokyo Ohka) as a developer.
[0028]
Using another exposure mask, the outside of the portion where the step is to be formed, that is, the portion to be thinned, is exposed to ultraviolet light at an exposure amount of 100 [mJ / cm 2 ], and about 5 [ Min), about 5 [μm] of polyimide was dissolved to form a thinned portion 5C and a step 5D.
[0029]
After curing the insulating film 5 made of polyimide RN-902 at 350 ° C., a bump mounting layer made of Cr / Cu / Ni (Cr / Cu: adhesion layer 6) is formed on the thick portion of the insulating film 5 including the inside of the opening 5M. , Ni: barrier layer 7) was formed, and Sn-Ag solder was reflowed at a temperature of 220 ° C. to form bumps 8.
[0030]
At this time, no crack 5A or delamination 5B occurred in the insulating film 5, and when this silicon device was mounted on a substrate, the crack 5A and delamination were similarly formed in the insulating film 5 near the bump 8. 5B did not occur, and good bonding could be performed.
[0031]
Example 2
An example in which a positive photosensitive polyimide is used and a step is formed by double exposure in which the developing time is changed (corresponding to Embodiment 3).
[0032]
In the silicon device formed up to the insulating film 4 made of PSG, RN-902 (trade name of Nissan Chemical) which is a positive photosensitive polyimide is coated on the entire surface including the pad electrode 3 made of Cu at 1500 [rpm] × 20. In [sec], spin coating (film thickness condition: 10 [μm]), preliminary drying on a hot plate at 80 [° C] for 20 [minutes], and 500 [mJ / cm 2 ] using an exposure mask. UV exposure was performed at the exposure amount of, and a contact hole was formed by performing dip development for about 5 minutes with NMD-3 (trade name of Tokyo Ohka) as a developer.
[0033]
Using another exposure mask, the outside of the portion where the step is to be formed, that is, the portion to be thinned is exposed to ultraviolet light at an exposure amount of 500 [mJ / cm 2 ], and about 2 [ Min), about 5 [μm] of polyimide was dissolved to form a thinned portion 5C and a step 5D.
[0034]
After curing the insulating film 5 made of polyimide RN-902 at 350 ° C., a bump mounting layer made of Cr / Cu / Ni (Cr / Cu: adhesion layer 6) is formed on the thick portion of the insulating film 5 including the inside of the opening 5M. , Ni: barrier layer 7) was formed, and Sn-Ag solder was reflowed at a temperature of 220 ° C. to form bumps 8.
[0035]
At this time, no crack 5A or delamination 5B occurred in the insulating film 5, and when this silicon device was mounted on a substrate, the crack 5A and delamination were similarly formed in the insulating film 5 near the bump 8. 5B did not occur, and good bonding could be performed.
[0036]
【The invention's effect】
In the electrode structure and the method for forming the same according to the present invention, a contact hole in which a part of the lower electrode is exposed is formed, and an insulating film in which a bump that contacts the lower electrode is formed in the contact hole. In this case, the insulating film is basically formed so as to have a step near the edge of the bump and to have a thinned portion directed outward from the step.
[0037]
By adopting the above configuration, when forming a bump electrode structure or mounting an electronic component having a bump electrode structure, it is possible to prevent cracks and peeling from occurring in the insulating film, and in this case, The required technique is a technique that is widely used in the field of semiconductor technology, so that there is no difficulty in implementing it.
[Brief description of the drawings]
FIG. 1 is a cutaway side view of a main part showing an electrode structure for describing Embodiment 1 of the present invention.
FIG. 2 is a fragmentary sectional side view showing an electrode structure in a process key point for explaining a second embodiment of the present invention.
FIG. 3 is a cutaway side view of a main part showing an electrode structure in a process key point for explaining a second embodiment of the present invention.
FIG. 4 is a cutaway side view of a main part showing an electrode structure for explaining a conventional technique.
FIG. 5 is a fragmentary side view showing an electrode structure in which cracks are suppressed from being generated in an insulating film.
[Explanation of symbols]
Reference Signs List 1 insulating film 2 top layer wiring 3 pad electrode 4 insulating film made of PSG 5 insulating film made of polyimide 5A crack 5B delamination 5C thinned portion 5D step 5M contact hole 6 adhesion layer made of Cu / Cr 7 barrier made of Ni Layer 8 Solder bump

Claims (3)

下部電極の一部が表出されるコンタクト・ホールが形成され且つ該コンタクト・ホール内で下部電極とコンタクトするバンプが形成された絶縁膜に於いて、
該絶縁膜は該バンプのエッジ近傍に段差をもち且つ該段差から外方に向かう薄膜化部分をもつこと
を特徴とする電極構造。In an insulating film in which a contact hole in which a part of the lower electrode is exposed is formed and a bump that contacts the lower electrode in the contact hole is formed,
The electrode structure, wherein the insulating film has a step near the edge of the bump and has a thinned portion extending outward from the step. パッド電極が形成された基板上にポジ型感光性材料からなる絶縁膜を形成する工程と、
次いで、該絶縁膜の露光及び現像を行ってコンタクト・ホールを形成する工程と、
次いで、該絶縁膜に於けるバンプのエッジ近傍に段差を生成する為に薄膜化すべき部分に対して該コンタクト・ホール形成時の露光量に比較して少ない露光量で再び露光及び現像を行って膜厚を低減させる工程と
が含まれてなることを特徴とする電極構造の形成方法。Forming an insulating film made of a positive photosensitive material on the substrate on which the pad electrode is formed,
Next, a step of forming a contact hole by exposing and developing the insulating film;
Next, the portion to be thinned in order to generate a step near the edge of the bump in the insulating film is again exposed and developed with a smaller exposure amount than the exposure amount at the time of forming the contact hole. A step of reducing the film thickness. パッド電極が形成された基板上にポジ型感光性材料からなる絶縁膜を形成する工程と、
次いで、該絶縁膜の露光及び現像を行ってコンタクト・ホールを形成する工程と、
次いで、該絶縁膜に於けるバンプのエッジ近傍に段差を生成する為に薄膜化すべき部分に対して該コンタクト・ホール形成時の露光量と同じ露光量で再び露光を行ってから該コンタクト・ホール形成時の現像時間に比較して少ない時間で現像を行って膜厚を低減させる工程と
が含まれてなることを特徴とする電極構造の形成方法。Forming an insulating film made of a positive photosensitive material on the substrate on which the pad electrode is formed,
Next, a step of forming a contact hole by exposing and developing the insulating film;
Next, the portion to be thinned in order to generate a step near the edge of the bump in the insulating film is exposed again at the same exposure amount as the exposure amount at the time of forming the contact hole. A step of reducing the film thickness by performing development in a shorter time than the development time in forming the electrode structure.
JP2002219303A 2002-07-29 2002-07-29 Electrode structure and its forming method Pending JP2004063729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002219303A JP2004063729A (en) 2002-07-29 2002-07-29 Electrode structure and its forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002219303A JP2004063729A (en) 2002-07-29 2002-07-29 Electrode structure and its forming method

Publications (1)

Publication Number Publication Date
JP2004063729A true JP2004063729A (en) 2004-02-26

Family

ID=31940241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002219303A Pending JP2004063729A (en) 2002-07-29 2002-07-29 Electrode structure and its forming method

Country Status (1)

Country Link
JP (1) JP2004063729A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173415A (en) * 2005-12-20 2007-07-05 Fujitsu Ltd Semiconductor device and its manufacturing method
JP2011003586A (en) * 2009-06-16 2011-01-06 Fujitsu Semiconductor Ltd Semiconductor element and method of fabricating the same
JP2015097244A (en) * 2013-11-15 2015-05-21 日立オートモティブシステムズ株式会社 Semiconductor integrated circuit
US9136218B2 (en) 2008-07-04 2015-09-15 Rohm Co., Ltd. Semiconductor device including a protective film

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007173415A (en) * 2005-12-20 2007-07-05 Fujitsu Ltd Semiconductor device and its manufacturing method
US8420522B2 (en) 2005-12-20 2013-04-16 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method of the same
US9136218B2 (en) 2008-07-04 2015-09-15 Rohm Co., Ltd. Semiconductor device including a protective film
US9391037B2 (en) 2008-07-04 2016-07-12 Rohm Co., Ltd. Semiconductor device including a protective film
US9698112B2 (en) 2008-07-04 2017-07-04 Rohm Co., Ltd. Semiconductor device including a protective film
JP2011003586A (en) * 2009-06-16 2011-01-06 Fujitsu Semiconductor Ltd Semiconductor element and method of fabricating the same
JP2015097244A (en) * 2013-11-15 2015-05-21 日立オートモティブシステムズ株式会社 Semiconductor integrated circuit

Similar Documents

Publication Publication Date Title
JP4755486B2 (en) Semiconductor device and manufacturing method thereof
JP5102726B2 (en) Manufacturing method of semiconductor device
JP2001068495A (en) Semiconductor device and manufacture thereof
JP2007012678A (en) Method of manufacturing semiconductor device
JP2007173415A (en) Semiconductor device and its manufacturing method
JPH06252151A (en) Manufacture of semiconductor chip bump
JP2008210827A (en) Semiconductor device and wiring board, and their manufacturing process
TW202008539A (en) Assembly structure, method of bonding using the same, and circuit board therefor
JP2005101463A (en) Semiconductor device and its manufacturing method
JP2000188357A (en) Semiconductor device and manufacture thereof
US20060157850A1 (en) Semiconductor device and manufacturing method thereof
KR100691151B1 (en) An Anchor System for Solder Bump
JP2000188305A (en) Semiconductor device and its manufacture
JP2004063729A (en) Electrode structure and its forming method
JP2002313832A (en) Bump electrode and its manufacturing method
JP3116573B2 (en) Bump electrode for semiconductor device and method of forming the same
JP2001035876A (en) Flip-chip connection structure, semiconductor device and fabrication thereof
JP2008244218A (en) Semiconductor device
JP2004172163A (en) Semiconductor device and method of manufacturing the same
JP7566508B2 (en) Semiconductor device and method for manufacturing the same
JPH0661233A (en) Manufacture of semiconductor device
JP2002237500A (en) Manufacturing method of semiconductor device
US20200090953A1 (en) Method of manufacturing semiconductor device
JP4461628B2 (en) Manufacturing method of semiconductor package
JP2008258439A (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050615

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070131

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070306

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070426

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20070619