JP2014158050A - トランジスタ及びその製造方法 - Google Patents
トランジスタ及びその製造方法 Download PDFInfo
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- JP2014158050A JP2014158050A JP2014093489A JP2014093489A JP2014158050A JP 2014158050 A JP2014158050 A JP 2014158050A JP 2014093489 A JP2014093489 A JP 2014093489A JP 2014093489 A JP2014093489 A JP 2014093489A JP 2014158050 A JP2014158050 A JP 2014158050A
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- metal
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28158—Making the insulator
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28255—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
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Abstract
【解決手段】 トランジスタは、基板と、基板上の一対のスペーサと、基板上且つスペーサ対間のゲート誘電体層と、ゲート誘電体層上且つスペーサ対間のゲート電極層と、ゲート電極層上且つスペーサ対間の絶縁キャップ層と、スペーサ対に隣接する一対の拡散領域とを有する。絶縁キャップ層は、ゲートにセルフアラインされるエッチング停止構造を形成し、コンタクトエッチングがゲート電極を露出させることを防止し、それにより、ゲートとコンタクトとの間の短絡を防止する。絶縁キャップ層は、セルフアラインコンタクトを実現し、パターニング限界に対して一層ロバストな、より幅広なコンタクトを最初にパターニングすることを可能にする。
【選択図】 図3C
Description
Claims (22)
- 基板と、
前記基板上の一対のスペーサと、
前記基板上且つ前記一対のスペーサ間のゲート誘電体層と、
前記ゲート誘電体層上且つ前記一対のスペーサ間のゲート電極層であり、前記ゲート誘電体層が、前記基板の表面上、及び該ゲート電極層と前記一対のスペーサとの間にある、ゲート電極層と、
前記ゲート電極層上且つ前記一対のスペーサ間にあり、且つ前記ゲート電極層と前記一対のスペーサとの間の前記ゲート誘電体層の直上にある絶縁キャップ層と、
前記一対のスペーサに隣接する一対の拡散領域と、
前記一対のスペーサに隣接し且つ前記一対の拡散領域の上にある第1の絶縁層であり、前記絶縁キャップ層と同一平面にある頂面を有する第1の絶縁層と、
前記第1の絶縁層の前記頂面の上及び前記絶縁キャップ層の第1部分の上にある第2の絶縁層と、
前記一対の拡散領域のうちの一方に接触した導電コンタクトであり、該導電コンタクトは前記一対のスペーサのうちの一方に隣接し且つ前記第2の絶縁層に隣接し、該導電コンタクトの一部が前記絶縁キャップ層の第2部分の上にある、導電コンタクトと、
を有するトランジスタ。 - 前記ゲート誘電体層、前記ゲート電極層及び前記絶縁キャップ層の結合体の高さは、前記一対のスペーサの高さを超えない、請求項1に記載のトランジスタ。
- 前記絶縁キャップ層は、窒化シリコン、酸化シリコン、炭化シリコン、炭素ドープされた窒化シリコン、酸窒化シリコン、又は酸化アルミニウムを有する、請求項1に記載のトランジスタ。
- 前記絶縁キャップ層は、窒化物材料、炭化物材料、酸化物材料、金属酸化物材料、又はlow−k誘電体材料を有する、請求項1に記載のトランジスタ。
- 前記絶縁キャップ層は、窒化ホウ素又は炭化ホウ素を有する、請求項1に記載のトランジスタ。
- 前記絶縁キャップ層は、炭素、窒素及び水素のうちの1つ以上でドープされたlow−k誘電体材料を有する、請求項1に記載のトランジスタ。
- 基板上にゲート誘電体層を形成する工程と、
前記ゲート誘電体層上にゲート電極層を形成する工程と、
前記ゲート誘電体層及び前記ゲート電極層の両側面に一対のスペーサを形成する工程と、
前記一対のスペーサに隣接する一対の拡散領域を形成する工程と、
前記一対のスペーサに隣接して前記一対の拡散領域の上に第1の絶縁層を形成する工程と、
前記一対のスペーサ及び前記第1の絶縁層を形成した後に、前記ゲート電極層をリセス化して、リセス化されたゲート電極層を形成する工程と、
前記一対のスペーサの内側で、前記リセス化されたゲート電極層上に絶縁キャップ層を形成する工程であり、該絶縁キャップ層は、前記第1の絶縁層の頂面と同一平面にある頂面を有する、工程と、
前記第1の絶縁層の前記頂面の上及び前記絶縁キャップ層の上に第2の絶縁層を形成する工程と、
前記第1及び第2の絶縁層内にコンタクト開口を形成する工程であり、該コンタクト開口は、前記一対の拡散領域のうちの一方と前記絶縁キャップ層の一部とを露出させる、工程と、
前記コンタクト開口内に前記一対の拡散領域のうちの前記一方に接触させて導電コンタクトを形成する工程であり、該導電コンタクトは前記一対のスペーサのうちの一方に隣接し且つ前記第2の絶縁層に隣接し、該導電コンタクトの一部が前記絶縁キャップ層の前記一部の上に形成される、工程と、
を有するトランジスタを製造する方法。 - 前記絶縁キャップ層を形成する工程は、
前記リセス化されたゲート電極層の上にブランケット絶縁材料層を堆積する工程と、
前記絶縁材料層を平坦化することで前記絶縁キャップ層を形成する工程と
を有する、請求項7に記載の方法。 - 前記拡散領域が形成された後に、前記ゲート電極層及び前記ゲート誘電体層を除去し、それにより前記一対のスペーサ間にトレンチを形成する工程と、
前記スペーサ間の前記トレンチの側壁及び底面に沿ってコンフォーマルhigh−kゲート誘電体層を堆積する工程と、
前記high−kゲート誘電体層上に金属ゲート電極層を堆積し、その後、該金属ゲート電極層をリセス化する工程と、
を更に有する請求項7に記載の方法。 - 前記絶縁キャップ層は、窒化シリコン、酸化シリコン、炭化シリコン、炭素ドープされた窒化シリコン、酸窒化シリコン、又は酸化アルミニウムを有する、請求項7に記載の方法。
- 前記絶縁キャップ層は、窒化物材料、炭化物材料、酸化物材料、金属酸化物材料、又はlow−k誘電体材料を有する、請求項7に記載の方法。
- 前記絶縁キャップ層は、窒化ホウ素又は炭化ホウ素を有する、請求項7に記載の方法。
- 前記絶縁キャップ層は、炭素、窒素及び水素のうちの1つ以上でドープされたlow−k誘電体材料を有する、請求項7に記載の方法。
- 前記ゲート誘電体層が、前記ゲート電極層と前記一対のスペーサとの間にもある、請求項7に記載の方法。
- 前記ゲート誘電体層が、前記絶縁キャップ層と前記一対のスペーサとの間にある、請求項7に記載の方法。
- 当該方法は更に、前記ゲート誘電体層をリセス化して、前記一対のスペーサと前記リセス化されたゲート電極との間のリセス化されたゲート誘電体層を形成する工程を有し、前記絶縁キャップ層は更に、前記リセス化されたゲート誘電体層の上に形成される、請求項7に記載の方法。
- 基板と、
前記基板上の一対のスペーサと、
前記基板上且つ前記一対のスペーサ間のゲート誘電体層と、
前記ゲート誘電体層上且つ前記一対のスペーサ間のゲート電極層と、
前記ゲート電極層上且つ前記一対のスペーサ間の絶縁キャップ層と、
前記一対のスペーサに隣接する一対の拡散領域と
を有し、
前記ゲート誘電体層が、前記一対のスペーサと前記ゲート電極層との間にあり、前記ゲート誘電体層がまた、前記一対のスペーサと前記絶縁キャップ層との間にあり、前記一対のスペーサと前記絶縁キャップ層との間前記ゲート誘電体層は、前記絶縁キャップ層の頂面と実質的に平坦な頂面を有する、
トランジスタ。 - 前記ゲート誘電体層、前記ゲート電極層及び前記絶縁キャップ層の結合体の高さは、前記一対のスペーサの高さを超えない、請求項17に記載のトランジスタ。
- 前記絶縁キャップ層は、窒化シリコン、酸化シリコン、炭化シリコン、炭素ドープされた窒化シリコン、酸窒化シリコン、又は酸化アルミニウムを有する、請求項17に記載のトランジスタ。
- 前記絶縁キャップ層は、窒化物材料、炭化物材料、酸化物材料、金属酸化物材料、又はlow−k誘電体材料を有する、請求項17に記載のトランジスタ。
- 前記絶縁キャップ層は、窒化ホウ素又は炭化ホウ素を有する、請求項17に記載のトランジスタ。
- 前記絶縁キャップ層は、炭素、窒素及び水素のうちの1つ以上でドープされたlow−k誘電体材料を有する、請求項17に記載のトランジスタ。
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