CN109411405A - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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Publication number
CN109411405A
CN109411405A CN201710704697.4A CN201710704697A CN109411405A CN 109411405 A CN109411405 A CN 109411405A CN 201710704697 A CN201710704697 A CN 201710704697A CN 109411405 A CN109411405 A CN 109411405A
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layer
interlayer dielectric
dielectric layer
contact
semiconductor structure
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永井享浩
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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Priority to CN201710704697.4A priority Critical patent/CN109411405A/zh
Priority to US15/705,267 priority patent/US20190057935A1/en
Publication of CN109411405A publication Critical patent/CN109411405A/zh
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Abstract

本发明公开一种半导体结构及其制作方法，该半导体结构包含一半导体基底；一第一层间介电层，设于该半导体基底上；一金属垫，设于该第一层间介电层中；一接触自对准结构，设于该第一层间介电层上，该接触自对准结构包含一开口，位于该金属垫正上方；一第二层间介电层，设于该第一层间介电层上；及一接触插塞，贯穿该第二层间介电层，并经由该接触自对准结构的该开口，电连接至该金属垫。

Description

半导体结构及其制作方法
技术领域
本发明涉及半导体制作工艺技术领域，特别是涉及一种半导体结构及其制作方法。
背景技术
在DRAM半导体元件中，通常包括存储单元区域、周边电路区域及核心区域。存储单元区域用于存储数据。周边电路区域可用于将外部电压信号转换为内部电压信号或用于半导体芯片内、外部的信号传输。当要将数据写入存储单元或要读取存储在存储单元中的数据时，则需利用核心电路区域选择性地控制连接到相应存储单元的字符线及位线。
通常，在DRAM的存储单元区域中形成有最小宽度的图案，并且周边电路区域设置有比存储单元区域宽的宽度的图案及较大的空出区域。核心电路区域设置有称为读出放大器的信号放大装置，其包括非常精细且复杂的电路。也就是说，核心电路区域需要与存储单元区域相当的细线路设计规则。
现有技术的缺点在于，核心电路区域内的接触插塞是在存储单元区域的电容结构完成后才开始制作，因此接触洞的制作必须以干蚀刻制作工艺蚀穿较厚的介电层(厚度通常超过电容的高度)，而核心电路区域的接触垫区域的宽度受限于前述细线路设计规则，因此线宽非常的小，不易对准，加上蚀刻开孔时不容易判定蚀刻终点，导致接触洞蚀刻时易发生良率问题。
发明内容
本发明的主要目的在于提供一种改良的半导体元件及其制作方法，可以解决现有技术的不足。
根据本发明一实施例，提供一种半导体结构，包含一半导体基底；一第一层间介电层，设于该半导体基底上；一金属垫，设于该第一层间介电层中；一接触自对准结构，设于该第一层间介电层上，该接触自对准结构包含一开口，位于该金属垫正上方；一第二层间介电层，设于该第一层间介电层上；及一接触插塞，贯穿该第二层间介电层，并通过该接触自对准结构的该开口，电连接至该金属垫。
根据本发明另一实施例，提供一种制作半导体结构的方法。首先提供一半导体基底。在该半导体基底上形成一第一层间介电层。再于该第一层间介电层中形成一金属垫。再于该第一层间介电层上形成一接触自对准结构，其中该接触自对准结构包含一开口，为于该金属垫正上方。再于该第一层间介电层上形成一第二层间介电层。再形成一接触插塞，贯穿该第二层间介电层，并通过该接触自对准结构的该开口，电连接至该金属垫。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图5为本发明一实施例所绘示的一种制作半导体结构的方法的剖面示意图；
图6为本发明一实施例所绘示的接触自对准结构的上视示意图；
图7为本发明另一实施例所绘示的接触自对准结构的上视示意图。
主要元件符号说明
10 半导体基底
101 存储器阵列区域
111 存储胞
121 下电极结构结构
131 高介电常数层
140 电容上电极层
141 氮化钛层
142 多晶硅层
143 钨金属层
144 硬掩模层
201 核心电路区域
210 导电区域
211 电路元件
240 接触自对准结构
240a 开口
241 第一部位
242 第二部位
302 第一层间介电层
304 蚀刻停止层
306 第二层间介电层
311、321 金属垫
320 接触元件
322 细线路
402 接触洞
404 接触插塞
M0 金属层
w 宽度
wx 长轴宽度
wy 短轴宽度
具体实施方式
在下文中，将参照附图说明细节，该些附图中的内容也构成说明书细节描述的一部分，并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以具以实施。
当然，也可采行其他的实施例，或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此，下文的细节描述不应被视为是限制，反之，其中所包含的实施例将由随附的权利要求来加以界定。
本文实施例中的描述，有关于各种薄膜(包括导电膜、金属、介电层等)的沉积、图案化或蚀刻等步骤均可利用已知的工艺来完成，例如，化学气相沉积法、物理气相沉积法、溅镀法、原子层沉积法、光学光刻制作工艺、等离子体干蚀刻、湿蚀刻、反应性离子蚀刻法等，其细节将不另赘述。
请参阅图1至图5，其为依据本发明一实施例所绘示的一种制作半导体结构的方法的剖面示意图。如图1所示，首先提供一半导体基底10，包含一存储器阵列区域101以及一核心电路区域201。在存储器阵列区域101内形成有多个存储胞111，在核心电路区域201内形成有多个电路元件211，例如，MOS晶体管等。
需注意，图中的存储胞、电路元件仅为例示说明，且其比例并未按照原尺寸比例绘示。在半导体基底10中可以另形成有掺杂区或离子阱等，此外，在存储器阵列区域101内可以形成有埋入字符线等结构，由于这些结构特征均为周知技术，因此不另赘述其细节，在图中也予以省略，以求简洁。
根据本发明一实施例，核心电路区域201通可以包含有读出放大器(SenseAmplifier，SA)及/或次字符线驱动(Sub-Word Driver，SWD)电路等等，其包括非常精细且复杂的线路。通常，核心电路区域201需要与存储单元区域相当的细线路设计规则。
根据本发明一实施例，在半导体基底10上另形成有一第一层间介电层302，覆盖存储器阵列区域101以及核心电路区域201。根据本发明一实施例，第一层间介电层302包含二氧化硅，但不限于此。根据本发明一实施例，在第一层间介电层302中形成有一金属垫311及321。根据本发明一实施例，金属垫311及321形成在M0金属层中。
根据本发明一实施例，金属垫311形成在存储器阵列区域101内，作为存储节点接触垫(storage node contact pad)，金属垫321则是形成在核心电路区域201内，作为接触垫，通过一接触元件320与下方的导电区域210电连接。在金属垫321周围可以形成有细线路322，其中，金属垫321与细线路322的线路间距与存储器阵列区域101内的线路间距(例如字符线与位线的线路间距)相当。
根据本发明一实施例，在金属垫321及第一层间介电层302上可以另形成一蚀刻停止层304，例如，蚀刻停止层304可以包含氮化硅，但不限于此。
根据本发明一实施例，此时，在存储器阵列区域101内的金属垫311上分别以形成有多个下电极结构121。下电极结构121由导电材料所构成，例如氮化钛等，下电极结构连接电容与金属垫311。下电极结构121的制作方法为周知技术，因此其细节不另赘述。
如图2所示，在完成存储器阵列区域101内的下电极结构121的制作后，接着于半导体基底10上形成一高介电常数层131，并覆盖在下电极结构121上。根据本发明一实施例，在存储器阵列区域101内，高介电常数层131共形的覆盖在下电极结构121表面上作为电容介电层，在核心电路区域201内，高介电常数层131覆盖在蚀刻停止层304上，并与蚀刻停止层304直接接触。
根据本发明一实施例，高介电常数层131的介电常数大于或等于8。举例来说，高介电常数层131可以包含Al2O3、HfO2、ZrO2或La2O3，但不限于此。
接着，在高介电常数层131上形成一电容上电极层140。根据本发明一实施例，举例来说，电容上电极层140可以包含一氮化钛层141、一多晶硅层142、一钨金属层143及一硬掩模层144，其中硬掩模层144可以包含氮化硅，但不限于此。根据本发明一实施例，电容上电极层140同时覆盖存储器阵列区域101及核心电路区域201。
如图3所示，接着进行一光刻及蚀刻制作工艺，在核心电路区域201内，将电容上电极层140图案化成一接触自对准结构240，其中接触自对准结构240包含一开口240a，为于金属垫321的正上方，并且大致对准金属垫321。接触自对准结构240直接接触高介电常数层131。
由于接触自对准结构240是从电容上电极层140图案化而形成的，故接触自对准结构240与电容上电极层140的各层结构均相同，换言之，接触自对准结构同样从下到上包含氮化钛层141、多晶硅层142、钨金属层143及硬掩模层144。
请同时参阅图6，其为接触自对准结构240的上视示意图。图6中同时显示出接触自对准结构240下方的金属垫321及细线路322。根据本发明一实施例，接触自对准结构240可以是一连续的、封闭的环状图案，围绕着开口240a。
根据本发明一实施例，接触自对准结构240可以具有一矩形轮廓，而开口为一椭圆形，具有一长轴宽度wx及一短轴宽度wy，其中短轴宽度wy小于或等于金属垫的一宽度w，例如，宽度w可以小于或等于70nm，但不限于此。
根据本发明一实施例，接触自对准结构240不一定是一连续的、封闭的环状图案接触。例如，图7中自对准结构240具有一第一部位241及一第二部位242，其中第一部位241及第二部位242彼此分离，而开口240a介于第一部位241及第二部位242中间。
根据本发明一实施例，第一部位241及第二部位242可以是彼此平行设置的长条形或长方形图案，其长轴平行于图中的参考x轴坐标。根据本发明一实施例，第一部位241及第二部位242间的空间(参考y轴坐标方向上)小于或等于金属垫321的一宽度w。
如图4所示，接着，在存储器阵列区域101及核心电路区域201上形成一第二层间介电层306，例如，第二层间介电层306包含氧化硅、二氧化硅、BSG、BPSG等。
第二层间介电层306是在存储器阵列区域101内的电容结构完成后才沉积，又可称之为存储器后介电(post-memory dielectric，PMD)层。根据本发明一实施例，第二层间介电层306的厚度超过存储器阵列区域101内的电容结构的高度。根据本发明一实施例，例如，第二层间介电层306约为2至3微米。
接着，进行一光刻及蚀刻制作工艺，在第二层间介电层306蚀刻出一接触洞402。根据本发明一实施例，接触洞402贯穿第二层间介电层306、高介电常数层131及蚀刻停止层304，显露出部分金属垫321的上表面。
根据本发明一实施例，在第二层间介电层306中蚀刻接触洞402的过程中，可能因为对不准或者蚀刻角度倾斜的因素，使得最终接触洞402底部与金属垫321相对位置偏移，本发明通过设置在第一层间介电层302上的自对准结构240使得接触洞402底部可以自对准自对准结构240的开口240a，自对准结构240中的钨金属层143可以抵挡蚀刻，由此改善接触洞蚀刻时的良率。
如图5所示，在完成接触洞402后，接着于接触洞402内形成一接触插塞404，其中接触插塞404贯穿第二层间介电层306、高介电常数层131及蚀刻停止层304，电连接至金属垫321。根据本发明一实施例，接触插塞404可以包含氮化钛及/或钨金属，但不限于此。后续，可以继续进行后段的金属化制作工艺，形成金属内连线结构(图未示)。
以上所述仅为本发明之优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种半导体结构，包含：
半导体基底；
第一层间介电层，设于该半导体基底上；
金属垫，设于该第一层间介电层中；
接触自对准结构，设于该第一层间介电层上，该接触自对准结构包含一开口，位于该金属垫正上方；
第二层间介电层，设于该第一层间介电层上；及
接触插塞，贯穿该第二层间介电层，并通过该接触自对准结构的该开口。
2.如权利要求1所述的半导体结构，其中该接触自对准结构具有一环状图案，围绕着该开口。
3.如权利要求2所述的半导体结构，其中该接触自对准结构具有一矩形轮廓。
4.如权利要求1所述的半导体结构，其中该开口为一椭圆形，具有一长轴宽度及一短轴宽度。
5.如权利要求4所述的半导体结构，其中该短轴宽度小于或等于该金属垫的一宽度。
6.如权利要求1所述的半导体结构，其中该接触自对准结构具有一第一部位及一第二部位，该第一部位及该第二部位彼此分离，而该开口介于该第一部位及该第二部位中间。
7.如权利要求6所述的半导体结构，其中该第一部位及该第二部位间的空间小于或等于该金属垫的一宽度。
8.如权利要求1所述的半导体结构，其中该接触自对准结构包含一钨金属层。
9.如权利要求8所述的半导体结构，其中该接触自对准结构另包含一多晶硅层，设于该钨金属层下方。
10.如权利要求9所述的半导体结构，其中该接触自对准结构另包含一氮化钛层，设于该多晶硅层下方。
11.如权利要求1所述的半导体结构，其中该接触插塞经由该接触自对准结构的该开口，电连接至该金属垫。
12.一种制作半导体结构的方法，包含：
提供一半导体基底；
在该半导体基底上形成一第一层间介电层；
在该第一层间介电层中形成一金属垫；
在该第一层间介电层上形成一接触自对准结构，其中该接触自对准结构包含一开口，为于该金属垫正上方；
在该第一层间介电层上形成一第二层间介电层；及
形成一接触插塞，贯穿该第二层间介电层，并通过该接触自对准结构的该开口。
13.如权利要求10所述的制作半导体结构的方法，其中另包含：
在该第一层间介电层上形成该接触自对准结构前，先于该金属垫及该第一层间介电层上形成一蚀刻停止层；及
在该蚀刻停止层上形成一高介电常数层，其中该接触插塞贯穿该第二层间介电层、该高介电常数层及该蚀刻停止层。
14.如权利要求13所述的制作半导体结构的方法，其中该高介电常数层包含Al2O3、HfO2、ZrO2或La2O3。
15.如权利要求13所述的制作半导体结构的方法，其中该接触自对准结构直接接触该高介电常数层。
16.如权利要求15所述的制作半导体结构的方法，其中该接触自对准结构包含一钨金属层。
17.如权利要求16所述的制作半导体结构的方法，其中该接触自对准结构另包含一多晶硅层，设于该钨金属层下方。
18.如权利要求17所述的制作半导体结构的方法，其中该接触自对准结构另包含一氮化钛层，设于该多晶硅层下方。
19.如权利要求18所述的制作半导体结构的方法，其中该接触自对准结构另包含硬掩模层，设于该钨金属层上方。
20.如权利要求12所述的制作半导体结构的方法，其中该接触插塞经由该接触自对准结构的该开口，电连接至该金属垫。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6350642B1 (en) * 2000-11-21 2002-02-26 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor memory device including various contact studs
CN1577823A (zh) * 2003-06-25 2005-02-09 三星电子株式会社 半导体器件及其制造方法
CN101009267A (zh) * 2006-01-23 2007-08-01 三星电子株式会社 具有自对准接触的半导体器件及其制造方法
CN102640291A (zh) * 2009-12-30 2012-08-15 英特尔公司 自对准接触部
US20150108605A1 (en) * 2013-10-15 2015-04-23 Jae-hwa Park Integrated Circuit Devices Having Through Silicon Via Structures and Methods of Manufacturing the Same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6534809B2 (en) * 1999-12-22 2003-03-18 Agilent Technologies, Inc. Hardmask designs for dry etching FeRAM capacitor stacks
KR20020065795A (ko) * 2001-02-07 2002-08-14 삼성전자 주식회사 디램 장치 및 그 형성 방법
US6472266B1 (en) * 2001-06-18 2002-10-29 Taiwan Semiconductor Manufacturing Company Method to reduce bit line capacitance in cub drams
US6709919B2 (en) * 2002-05-15 2004-03-23 Taiwan Semiconductor Manufacturing Company Method for making auto-self-aligned top electrodes for DRAM capacitors with improved capacitor-to-bit-line-contact overlay margin
KR100919712B1 (ko) * 2007-06-27 2009-10-06 삼성전자주식회사 반도체 집적 회로 장치 및 그 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6350642B1 (en) * 2000-11-21 2002-02-26 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor memory device including various contact studs
CN1577823A (zh) * 2003-06-25 2005-02-09 三星电子株式会社 半导体器件及其制造方法
CN101009267A (zh) * 2006-01-23 2007-08-01 三星电子株式会社 具有自对准接触的半导体器件及其制造方法
CN102640291A (zh) * 2009-12-30 2012-08-15 英特尔公司 自对准接触部
US20150108605A1 (en) * 2013-10-15 2015-04-23 Jae-hwa Park Integrated Circuit Devices Having Through Silicon Via Structures and Methods of Manufacturing the Same

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