JP2019050415A - トランジスタ及びその製造方法 - Google Patents

トランジスタ及びその製造方法 Download PDF

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JP2019050415A
JP2019050415A JP2018220316A JP2018220316A JP2019050415A JP 2019050415 A JP2019050415 A JP 2019050415A JP 2018220316 A JP2018220316 A JP 2018220316A JP 2018220316 A JP2018220316 A JP 2018220316A JP 2019050415 A JP2019050415 A JP 2019050415A
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Japan
Prior art keywords
metal
structure
layer
gate electrode
contact
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JP2018220316A
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English (en)
Inventor
ティー. ボーア,マーク
T Bohr Mark
ティー. ボーア,マーク
ガーニ,タヒル
Tahir Ghani
エム. ラッハル−オラビ,ナディア
M Rahhal-Orabi Nadia
エム. ラッハル−オラビ,ナディア
ジョシ,スブハシュ
Joshi Subhash
エム. スタイガーウォルド,ジョーゼフ
M Steigerwald Joseph
エム. スタイガーウォルド,ジョーゼフ
ダブリュー. クラウス,ジェイソン
W Klaus Jason
ダブリュー. クラウス,ジェイソン
ファン,ジャック
Jack Hwang
マッキーウィッツ,ライアン
Mackiewicz Ryan
Original Assignee
インテル コーポレイション
Intel Corp
インテル コーポレイション
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Priority to US12/655,408 priority Critical patent/US8436404B2/en
Priority to US12/655,408 priority
Application filed by インテル コーポレイション, Intel Corp, インテル コーポレイション filed Critical インテル コーポレイション
Publication of JP2019050415A publication Critical patent/JP2019050415A/ja
Pending legal-status Critical Current

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