TWI729128B - 半導體結構及其製作方法 - Google Patents

半導體結構及其製作方法 Download PDF

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TWI729128B
TWI729128B TW106115398A TW106115398A TWI729128B TW I729128 B TWI729128 B TW I729128B TW 106115398 A TW106115398 A TW 106115398A TW 106115398 A TW106115398 A TW 106115398A TW I729128 B TWI729128 B TW I729128B
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layer
top surface
conductive layer
gate
stress
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TW106115398A
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TW201901954A (zh
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劉恩銓
童宇誠
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聯華電子股份有限公司
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Priority to US15/627,427 priority patent/US10153369B2/en
Priority to US16/180,033 priority patent/US10340381B2/en
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Abstract

本發明提供一種半導體結構，包含一基底，包含有一介電層位於該基底上，一閘極導電層，位於該基底上，並位於該介電層中，兩側壁子，分別位於該閘極導電層的兩側，其中該兩側壁子的一頂面低於該閘極導電層的一頂面，以及一應力帽蓋層，覆蓋於該閘極導電層上以及該兩側壁子上，其中部分該應力帽蓋層位於該兩側壁子的正上方。

Description

半導體結構及其製作方法
本發明係關於一種半導體結構以及其製作方法，特別是關於一種修整側壁子以增強應力層之作用的方法和半導體結構。
隨著半導體製程之線寬的不斷縮小，金氧半電晶體(MOSFET)之尺寸亦不斷地朝向微型化發展，然而目前半導體製程之線寬已發展至瓶頸的情況下，如何提升載子遷移率以增加MOS電晶體之速度已成為目前半導體技術領域中之一大課題。
在目前已知的技術中，已有利用應力層的應用來提升NMOS電晶體與PMOS電晶體的整體效能，應力層的方式係藉由在MOS電晶體上形成高伸張或高壓縮的應力層，使得矽的帶結構(band structure)發生改變，而造成載子移動性增加。
本發明提供一種半導體結構，包含一基底，包含有一介電層位於該基底上，一閘極導電層，位於該基底上，並位於該介電層中，兩側壁子，分別 位於該閘極導電層的兩側，其中該兩側壁子的一頂面低於該閘極導電層的一頂面，以及一應力帽蓋層，覆蓋於該閘極導電層上以及該兩側壁子上，其中部分該應力帽蓋層位於該兩側壁子的正上方。
本發明另提供一種半導體結構的製作方法，包含：首先提供一基底，接著形成一介電層位於該基底上，並形成一閘極導電層以及兩側壁子位於該介電層中，其中該兩側壁子分別位於該閘極導電層的兩側，接下來部分移除該閘極導電層，之後部分移除該兩側壁子，其中該兩側壁子的一頂面低於該閘極導電層的一頂面，以及形成一應力帽蓋層覆蓋於該閘極導電層上以及該兩側壁子上，其中部分該應力帽蓋層位於該兩側壁子的正上方。
本實施例的特徵在於，將側壁子部分移除，因此後續形成的應力帽蓋層將會更接近電晶體的通道區域，且應力帽蓋層不單僅有覆蓋在閘極結構的頂面，也同時覆蓋在閘極結構部分側壁，如此覆蓋面積更大，更能有效將應力帽蓋層124的應力傳遞至通道區。
100:基底
102:淺溝隔離
104:閘極結構
104A:閘極結構
104B:閘極結構
104C:閘極結構
108:閘極介電層
109A:高介電常數層
109B:功函數金屬層
109C:頂面
110:閘極導電層
110a:頂面
112:側壁子
112’:側壁子
112a:頂面
116:接觸蝕刻停止層
120:遮罩層
122:凹槽
122’:凹槽
124:應力帽蓋層
124’:應力帽蓋層
124A:延伸部分
124B:延伸部分
208:閘極介電層
209A:高介電常數層
209B:功函數金屬層
210:閘極導電層
212:側壁子
308:閘極介電層
309A:高介電常數層
309B:功函數金屬層
310:閘極導電層
312:側壁子
332:應力帽蓋層
340:空洞
P1:蝕刻步驟
P2:蝕刻步驟
第1圖至第4圖，其繪示本發明第一實施例之製作一半導體結構的步驟示意圖。
第5圖至第6圖，其繪示本發明第二實施例之製作一半導體結構的步驟示意圖。
第7圖繪示本發明另一實施例之一半導體結構的示意圖。
第8圖繪示本發明另一實施例之一半導體結構的示意圖。
為使熟習本發明所屬技術領域之一般技藝者能更進一步了解本發明，下文特列舉本發明之較佳實施例，並配合所附圖式，詳細說明本發明的構成內容及所欲達成之功效。
為了方便說明，本發明之各圖式僅為示意以更容易了解本發明，其詳細的比例可依照設計的需求進行調整。在文中所描述對於圖形中相對元件之上下關係，在本領域之人皆應能理解其係指物件之相對位置而言，因此皆可以翻轉而呈現相同之構件，此皆應同屬本說明書所揭露之範圍，在此容先敘明。
請參考第1圖至第4圖，其繪示本發明第一實施例之製作一半導體結構的步驟示意圖。首先，提供一基底100，並於基底100上形成一介電層101，之後形成至少一閘極結構104位於介電層101中，在此分別定義為第一閘極結構104A與第二閘極結構104B。基底100可以是具有半導體材料的基底，例如是矽基底(silicon substrate)、磊晶矽(epitaxial silicon substrate)、矽鍺半導體基底(silicon germanium substrate)、碳化矽基底(silicon carbide substrate)或矽覆絕緣(silicon-on-insulator，SOI)基底等，也可以是具有非半導體材質之基底，例如是玻璃基底(glass substrate)，介電層101例如為氮化矽或氧化矽，但不以此為限。此外，可預先於基底100形成至少一個淺溝隔離(shallow trench isolation，STI)102，以藉由淺溝隔離102定義出各主動區域。另外，本發明中更可能包含複數鰭狀結構(圖未示)位於基底100上，也屬於本發明涵蓋範圍內。
舉例來說，典型的積體電路(例如半導體元件)包含有複數個主動區與 複數個非主動區，主動區內可能包含有鰭狀電晶體等元件(例如n型鰭狀電晶體或p型鰭狀電晶體)。各主動區可能包含有不同的圖案密度、不同的鰭狀電晶體元件，或是各自包含的鰭狀電晶體具有不同的導電型態等。
各閘極結構104A、104B各自包含有一閘極介電層108、208、一高介電常數層109A、209A、一功函數金屬層109B、209B以及一閘極導電層110、210，其中閘極介電層108、208的材料可以包括氧化矽(SiO)、氮化矽(SiN)、氮氧化矽(SiON)等，高介電常數層109A、209A包含介電常數大於4的介電材料，例如係選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide，HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化鋁(aluminum oxide，Al2O3)、氧化鑭(lanthanum oxide，La2O3)、氧化鉭(tantalum oxide，Ta2O5)、氧化釔(yttrium oxide，Y2O3)、氧化鋯(zirconium oxide，ZrO2)、鈦酸鍶(strontium titanate oxide，SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide，ZrSiO4)、鋯酸鉿(hafnium zirconium oxide，HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。
功函數金屬層109B、209B可包含一p型功函數金屬層或是一n型功函數金屬層(取決於預定形成p型電晶體或是n型電晶體)，p型功函數金屬層例如氮化鈦(titanium nitride，TiN)、碳化鈦(titanium carbide，TiC)、氮化鉭(tantalum nitride，TaN)、碳化鉭(tantalum carbide，TaC)、碳化鎢(tungsten carbide，WC)、或氮化鋁鈦(aluminum titanium nitride，TiAlN)，但不限於此。或者n型功函數金屬層例如鋁化鈦(titanium aluminide，TiAl)層、鋁化鋯(zirconium aluminide，ZrAl)層、鋁化鎢(tungsten aluminide，WAl)層、鋁化鉭(tantalum aluminide，TaAl)層或鋁化鉿(hafnium aluminide，HfAl)層，但不限於此。
閘極導電層110、210的材料可以包括未摻雜的多晶矽、重摻雜的多晶矽、或是單層或多層金屬層，金屬層例如功函數金屬層，阻擋層和低電阻金屬層等，但本發明不限於此，上述閘極結構所包含的材料可依照實際需求而調整。
此外，本發明更包含複數個側壁子112、212，分別位於各閘極結構104A與104B的兩側。側壁子112、212的材質例如為氮化矽或氧化矽等。之後，於基底100上形成一接觸蝕刻停止層(contact etch stop layer，CESL)116，並覆蓋各閘極結構104A、104B以及各側壁子112、212，接觸蝕刻停止層116可為單一層或複合層，以對閘極結構104施加所需的壓縮應力或是伸張應力，但並不以此為限。在其他實施例中，也可省略形成接觸蝕刻停止層116的步驟。此外，在側壁子112、212兩側的基底100中，形成有源/汲極區域106，在另一實施例中，可依據實際元件需求，選擇在形成側壁子112、212之前，於基底先形成一輕摻雜汲極(light doped drain；LDD，未繪示)。
在上述元件完成之後，為了進一步形成應力層於特定閘極結構104上，以提供閘極結構所需的應力(壓縮應力或是伸張應力)，將繼續進行後續步驟，以下以閘極結構104A為例說明：如第2圖所示，藉由一蝕刻步驟P1，移除閘極結構104A的部分頂部區域，值得注意的是，可以藉由單次或是多次蝕刻步驟，可移除部分的高介電常數層109A、功函數金屬層109B以及閘極導電層110。蝕刻步驟P1完成後，閘極導 電層110的頂面110a較佳為一平坦頂面，且較佳高於剩餘的高介電常數層109A與功函數金屬層109B的頂面(定義為頂面109C)。至於閘極結構104B由於在此步驟中沒有預定形成應力層於其上，因此形成一遮罩層120保護閘極結構104B。
如第3圖所示，再次進行另外一蝕刻步驟P2，以移除部分的側壁子112，此時在閘極結構104A的上半部形成一“倒U型”的凹槽122。剩餘的側壁子定義為112’，值得注意的是，側壁子112’的頂面112a將會低於高介電常數層109A與功函數金屬層109B的頂面109C，也會低於閘極導電層110的頂面110a。值得注意的是，本實施例中側壁子112與接觸蝕刻停止層116包含有不同蝕刻選擇比，因此在蝕刻步驟P2進行後，主要移除側壁子112，而接觸蝕刻停止層116沒有被移除或是僅有少部分被移除，因此此時接觸蝕刻停止層116的頂面將會高於側壁子112’的頂面112a，在一些實施例中，也同時高於閘極導電層110的頂面110a。
接著，形成一應力層於凹槽122內，並且再進行一平坦化步驟或一回蝕刻步驟(圖未示)移除多餘的應力層。以形成一應力帽蓋層124於閘極結構104A上方，以及位於側壁子112’的正上方。因為應力帽蓋層124填入凹槽122內，因此應力帽蓋層124也具有一倒U型的剖面。更進一步而言，應力帽蓋層124包含有兩延伸部分124A、124B，延伸部分124A或延伸部分124B位於側壁子112’的正上方，並且位於接觸蝕刻停止層116與閘極導電層110之間。應力帽蓋層124的材質取決於閘極結構104A預計製作為n型電晶體或是p型電晶體而有所不同，舉例來說，若閘極結構104A若預計製作為n型電晶體，則應力帽蓋層124較佳選自具有拉伸應力的材質。此外更可以針對應力帽蓋層124本身進行額外處理步驟，例如退火處理、紫外線光照處理等，以進一步增強其應力，也屬於本發明的涵蓋範圍內。此外值得注意的是，本實施例中接觸蝕刻停止層116直接接觸部分應力帽 蓋層124的側壁，而應力帽蓋層124不位於接觸蝕刻停止層116的正上方。
上述步驟中，並未在閘極結構104B上方形成應力帽蓋層。後續步驟中，可能需要對閘極結構104B形成不同的應力帽蓋層，舉例來說，若閘極結構104A將形成n型電晶體，而閘極結構104B將形成p型電晶體，則需要重複上述第2圖至第4圖的步驟，並且在閘極結構104B頂端應力層形成時，選擇具有壓縮應力的材料。由於步驟大致相同，在此不重複贅述。至此本發明的半導體閘極結構已經完成，後續閘極結構可用於製作電晶體或是記憶元件等，該些技術屬於本領域的常見技術而不多加贅述。
下文將針對本發明之半導體結構及其製作方法的不同實施樣態進行說明，且為簡化說明，以下說明主要針對各實施例不同之處進行詳述，而不再對相同之處作重覆贅述。此外，本發明之各實施例中相同之元件係以相同之標號進行標示，以利於各實施例間互相對照。
在上述實施例中，側壁子112被部分移除並形成凹槽122時，接觸蝕刻停止層116並未被一併移除(或是僅有一少部分被移除)，因此接觸蝕刻停止層116會高於側壁子112’的頂面112a。然而在本發明的另外一實施例中，請參考第5圖，若側壁子112與接觸蝕刻停止層116所選的材料相近，或是調整蝕刻步驟P2對於不同材料的蝕刻速率，可以在蝕刻步驟P2過程中一併移除部分接觸蝕刻停止層116，或著是在蝕刻步驟P2進行之後額外進行其他的蝕刻步驟以移除接觸蝕刻停止層116，以在閘極結構104A頂部形成凹槽122’。此時接觸蝕刻停止層116的一頂面116a可能仍會高於側壁子112’的頂面112a，但是卻低於閘極導電層110的頂面110a(如第5圖所示)，或著是低於側壁子112’的頂面(圖未示)。較佳而言， 接觸蝕刻停止層116的頂面116a仍高於基底100的頂面，然而本發明不限於此，也可能移除接觸蝕刻停止層116，直至露出部分基底100的表面。後續步驟請參考第6圖，同樣形成應力帽蓋層124’於凹槽122’內，應力帽蓋層124’覆蓋閘極結構104A的頂部與側壁，且具有一倒U型的剖面結構。
在另外一實施例中，如第7圖所示，除了閘極結構104A以外，另外形成一閘極結構104C位於介電層101中，閘極結構104C與閘極結構104A的導電型態可能相同或是不同，閘極結構104C除了包含有閘極介電層308、高介電常數層309A、功函數金屬層309B、閘極導電層310、側壁子312之外，頂端包含有應力帽蓋層332，而應力帽蓋層332與閘極結構104A中的應力帽蓋層124尺寸不同(例如寬度或延伸部分的深度等)。此實施例也屬於本發明的涵蓋範圍內。
在另外一實施例中，如第8圖所示，可能在形成應力帽蓋層332的過程中，一併形成部分的空洞340於應力帽蓋層332的延伸部分內。而空洞340的位置較佳低於閘極導電層310的頂面，但不限於此。此外空洞340的位置也不限於在閘極結構104C內，也有可能位於104A的應力帽蓋層124內。該特徵也屬於本發明涵蓋範圍內。
本實施例的特徵在於，將側壁子部分移除，因此後續形成的應力帽蓋層124將會更接近電晶體的通道區域，且應力帽蓋層124不單僅有覆蓋在閘極結構(例如閘極結構104A)的頂面，也同時覆蓋在閘極結構部分側壁，如此覆蓋面積更大，更能有效將應力帽蓋層124的應力傳遞至通道區。以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化 與修飾，皆應屬本發明之涵蓋範圍。
100:基底
101:介電層
102:淺溝隔離
104A:閘極結構
108:閘極介電層
109A:高介電常數層
109B:功函數金屬層
110:閘極導電層
112’:側壁子
116:接觸蝕刻停止層
120:遮罩層
124:應力帽蓋層
124A:延伸部分
124B:延伸部分
208:閘極介電層
209A:高介電常數層
209B:功函數金屬層
210:閘極導電層
212:側壁子

Claims (17)

  1. 一種半導體結構，包含：一基底，包含有一介電層位於該基底上；以及一第一閘極結構位於該介電層中，其中該第一閘極結構包含有：一閘極導電層，位於該基底上，並位於該介電層中；兩側壁子，分別位於該閘極導電層的兩側，其中該兩側壁子的一頂面低於該閘極導電層的一頂面；以及一帽蓋層，覆蓋於該閘極導電層上以及該兩側壁子上，其中部分該帽蓋層位於該兩側壁子的正上方，其中該帽蓋層提供一第一應力至該第一閘極結構的一通道區。
  2. 如申請專利範圍第1項所述的半導體結構，其中更包含有至少一空洞，位於該帽蓋層內，且該空洞較該閘極導電層的該頂面低。
  3. 如申請專利範圍第1項所述的半導體結構，其中更包含有一第二閘極結構，該第二閘極結構包含有一第二帽蓋層，且該第二帽蓋層提供一第二應力至該第二閘極結構的一通道區，其中該第一應力與該第二應力不同。
  4. 如申請專利範圍第1項所述的半導體結構，其中更包含有一高介電常數層以及一功函數層位於該基底與該閘極導電層之間，其中該高介電常數層以及該功函數金屬層的一頂面，高於該兩側壁子的該頂面。
  5. 如申請專利範圍第1項所述的半導體結構，其中更包含有兩接觸蝕刻停止層，分別位於該兩側壁子的一外側壁。
  6. 如申請專利範圍第5項所述的半導體結構，其中該兩接觸蝕刻停止層的一頂面高於該兩側壁子的該頂面。
  7. 如申請專利範圍第5項所述的半導體結構，其中該帽蓋層不會位於各該接觸蝕刻停止層的正上方。
  8. 如申請專利範圍第5項所述的半導體結構，其中該兩接觸蝕刻停止層的一頂面高於該閘極導電層的該頂面。
  9. 如申請專利範圍第5項所述的半導體結構，其中該兩接觸蝕刻停止層的一頂面低於該閘極導電層的該頂面。
  10. 如申請專利範圍第1項所述的半導體結構，其中該閘極導電層的該頂面為一平坦頂面。
  11. 一種半導體結構的製作方法，包含：提供一基底；形成一介電層位於該基底上；形成一閘極導電層以及兩側壁子位於該介電層中，其中該兩側壁子分別位於該閘極導電層的兩側；部分移除該閘極導電層；部分移除該兩側壁子，其中該兩側壁子的一頂面低於該閘極導電層的一頂面；以及 形成一應力帽蓋層覆蓋於該閘極導電層上以及該兩側壁子上，其中部分該應力帽蓋層位於該兩側壁子的正上方，其中該應力帽蓋層提供一第一應力至該閘極導電層所屬的一閘極結構的一通道區。
  12. 如申請專利範圍第11項所述的方法，.其中更包含形成有兩接觸蝕刻停止層，分別位於該兩側壁子的一外側壁。
  13. 如申請專利範圍第12項所述的方法，其中該兩接觸蝕刻停止層的一頂面高於該兩側壁子的該頂面。
  14. 如申請專利範圍第12項所述的方法，.其中各該接觸蝕刻停止層直接接觸該應力帽蓋層的部分側壁。
  15. 如申請專利範圍第12項所述的方法，其中該應力帽蓋層不會位於各該接觸蝕刻停止層的正上方。
  16. 如申請專利範圍第12項所述的方法，其中該兩接觸蝕刻停止層的一頂面高於該閘極導電層的該頂面。
  17. 如申請專利範圍第11項所述的方法，其中更包含形成至少一空洞於該應力帽蓋層中。
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