TW201907568A - 自我對準接點(五) - Google Patents

自我對準接點(五) Download PDF

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Publication number
TW201907568A
TW201907568A TW107127791A TW107127791A TW201907568A TW 201907568 A TW201907568 A TW 201907568A TW 107127791 A TW107127791 A TW 107127791A TW 107127791 A TW107127791 A TW 107127791A TW 201907568 A TW201907568 A TW 201907568A
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Taiwan
Prior art keywords
gate
metal
dielectric
layer
dielectric layer
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TW107127791A
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English (en)
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TWI666772B (zh
Inventor
T. 鮑爾馬克
迦尼泰希爾
M. 雷海爾-歐拉比納迪亞
M. 喬斯沙布哈許
M. 史泰格華德喬瑟夫
W. 克勞斯傑森
黃傑克
麥凱維席萊恩
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美商英特爾公司
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Publication of TW201907568A publication Critical patent/TW201907568A/zh
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Abstract

一電晶體包含一基體、位於該基體上的一對間隔物、位於該基體上且介於該對間隔物之間的一閘極介電層、位於該閘極介電層上且介於該對間隔物之間的一閘極電極層、位於該閘極電極層上且介於該對間隔物之間的一絕緣帽層、及鄰近該對間隔物的一對擴散區。該絕緣帽層形成一蝕刻中止結構，該蝕刻中止結構自我對準於閘極且防止接點蝕刻造成閘極電極暴露，從而防止閘極與接點之短路。絕緣體帽層可實現自我對準接點，使對圖案化限制更為堅固的較寬接點能夠初始圖案化。

Description

自我對準接點(五) 發明領域
本發明係有關於自我對準接點。
發明背景
金屬氧化物半導體(MOS)電晶體，諸如MOS場效電晶體(MOSFET)，用於製造積體電路。MOS電晶體包括若干組件，諸如閘極、閘極介電層、間隔物及諸如源極區及汲極區的擴散區。一層間介電層(ILD)典型地形成於MOS電晶體上且覆蓋擴散區。
MOS電晶體藉由典型地以一諸如鎢的金屬形成的接點插塞達成電氣連接。該等接點插塞是藉由首先圖案化ILD層來形成下達擴散區的通孔而被製成。圖案化製程通常為一光蝕刻製程。接下來，金屬沈積於通孔中以形成接點插塞。一下達閘極的單獨接點插塞使用同一製程或一類似製程而形成。
在一接點插塞製造期間可能出現的一問題為形成一接點與閘極短路。一接點與閘極短路為在接點插塞未對準而與閘極電氣接觸時發生的短路。防止接點與閘極短 路的一種習知的方法係藉由控制對齊及臨界尺寸(CD)。遺憾的是，對具有等於或低於100奈米(nm)之閘極間距(閘極長度+間隔)的電晶體而言，對閘極及接點尺寸的CD控制必須小於10nm且閘極層與接點層之間的對齊控制也必須小於10nm以產生一可製造的製程範圍。因此，一接點與一閘極短路之可能性非常高。隨著電晶體閘極間距尺寸由於臨界尺寸變得更小而進一步按比例縮小尺寸，此問題變得更加普遍。
發明概要
依據本發明之一實施例，係特地提出一種積體電路結構，其包含：一基板，其包含矽；一閘極結構，其在該基板上方，該閘極結構包含一閘極介電質以及一閘極電極；一第一介電閘極間隔物，其鄰接該閘極結構之一第一側；一第二介電閘極間隔物，其鄰接該閘極結構之一第二側；一第一源極或汲極區，其在該閘極結構之該第一側；一第二源極或汲極區，其在該閘極結構之該第二側；一導電接觸結構，其在該第一源極或汲極區上；一第一介電層，其在該閘極結構之一部分上，該第一介電層具有在該導電接觸結構之一部分上之一開口；一第一介電接觸間隔物，其沿該第一介電層之該開口之一第一側壁延伸；一第二介電接觸間隔物，其沿該第一介電層之該開口之一第二側壁延伸；一金屬結構，其在該第一介電接觸間隔物與該第二介電接觸間隔物之間，該金屬結構與該導電接觸結構之該 部分接觸；以及一第二介電層，其在該第一介電層上。
100‧‧‧基體
101‧‧‧MOS電晶體
102‧‧‧閘極/金屬閘極/閘極層/下方金屬閘極/金屬閘極層
102a、102b‧‧‧金屬層
102a‧‧‧保形金屬閘極層/初始金屬閘極層/金屬閘極/金屬層
102b‧‧‧第二金屬層第二金屬閘極/層/第二金屬閘極層/金屬閘極/金屬層
104‧‧‧閘極介電層/高k閘極介電層/「U」形閘極介電層/保形介電層
106‧‧‧擴散區
108‧‧‧側壁間隔物/閘極間隔物/凹入之間隔物
110a、110b、110、902、1006‧‧‧ILD層
110a‧‧‧ILD層/第一ILD層/ILD
110b‧‧‧ILD層/附加ILD層
200‧‧‧未對準的溝槽接點
300‧‧‧絕緣體帽層/絕緣體帽/絕緣帽層
500‧‧‧虛擬閘極
502‧‧‧虛擬閘極介電層/虛擬閘極介電質
503a、503b、600、1002‧‧‧溝槽
504、602、700‧‧‧絕緣帽層/絕緣體帽層
800‧‧‧接觸溝槽開口
802‧‧‧矽化物層
804‧‧‧接點側壁間隔物
900‧‧‧金屬帽
904‧‧‧空隙
906‧‧‧自我對準絕緣帽層
1000‧‧‧間隔物
1004‧‧‧自我對準金屬銷
第1A圖繪示一基體及二習知的MOS電晶體以及一正確對準的溝槽接點。
第1B圖繪示一形成至MOS電晶體之一擴散區的未對準溝槽接點，其導致一接點與閘極短路。
第2A圖繪示依據本發明之一實施態樣的一基體及兩個具有各自在其金屬閘極頂上的絕緣體帽層的MOS電晶體。
第2B圖繪示一形成於具有絕緣體帽層的本發明之二MOS電晶體之間的正確對準的溝槽接點。
第2C圖繪示一形成於具有絕緣體帽層的本發明之二MOS電晶體之間的未對準的溝槽接點，其中該未對準並不導致一接點與閘極短路。
第3A至3C圖繪示一依據本發明之一實施態樣，在一替換金屬閘極製程之後形成的絕緣體帽層。
第4A至4C圖繪示一依據本發明之另一實施態樣，在一替換金屬閘極製程之後形成的絕緣體帽層。
第5A至5I圖繪示一關於依據本發明之一實施態樣，一在MOS電晶體之間隔物上延伸的絕緣體帽層之製造程序。
第6A至6F圖繪示一關於依據本發明之一實施態樣，具有一階狀輪廓的一金屬閘極之製造程序。
第7A至7C圖繪示依據本發明之一實施態樣，二 閘極具有階狀輪廓且在間隔物上具有延伸之絕緣體帽層的MOS電晶體。
第8A至8F圖繪示依據本發明之一實施態樣的接點側壁間隔物。
第9A至9D圖繪示一依據本發明之一實施態樣，用以在一金屬閘極頂上形成一絕緣帽的製程。
第10A至10G圖繪示一依據本發明之一實施態樣，用以在一溝槽接點頂上形成一金屬銷及絕緣間隔物的製程。
較佳實施例之詳細說明
本文描述在金屬氧化物半導體(MOS)電晶體製造期間減小接點與閘極短路之可能性之系統及方法。在以下說明中，說明性實施態樣之各種不同層面將使用熟於此技者所常用的用詞而被描述以將其作用本質傳達給其他熟於此技者。然而，熟於此技者將清楚理解的是本發明可僅利用某些描述層面而被實施。為了實現說明的目的，特定數字、材料及組態被提及以提供對該等說明性實施態樣之深入理解。然而，熟於此技者將清楚理解的是本發明在毋需特定細節之下也可被實施。在其他例子中，習知的特徵被忽略或簡化以免模糊該等說明性實施態樣。
各種不同的操作進而將以一最有助於理解本發明的方式被描述成多個分離操作，然而，說明順序不應被理解為暗示這些操作必然是與順序相關的。詳言之，這些 操作不一定以所描述順序執行。
第1A圖繪示一基體100及二MOS電晶體101。MOS電晶體101包括閘極102、閘極介電層104及間隔物108。擴散區106形成於基體100中。層間介電層(ILD)，諸如ILD層110a及110b，係被沈積於二MOS電晶體101之間及它們周圍的區域中。
第1A圖還繪示一穿過ILD層110a/b被形成下達至擴散區106的溝槽接點200。溝槽接點200典型地使用以一金屬沈積製程接隨一光蝕刻圖案化製程被成型。光蝕刻圖案化製程及金屬沈積製程是業界所習知的。光蝕刻圖案化製程穿過ILD層110a/b蝕刻一下達至擴散區106的溝槽開口。金屬沈積製程，諸如電鍍、無電鍍敷、化學氣相沈積、物理氣相沈積、濺鍍或原子層沈積，以一諸如鎢或銅的金屬來填充該溝槽開口。一金屬內襯通常先於金屬而被沈積，諸如鉭或氮化鉭內襯。一平坦化製程，諸如化學機械研磨(CMP)，用以移除所有過量金屬並完成溝槽接點200之製造。
應指出的是在本發明之替代實施態樣中，通孔接點可被使用來代替溝槽接點。因此，該接觸開口可以是一溝槽形或一通孔形，視所使用的圖案化製程或一特定的積體電路製程之需求而定。本文所描述的本發明之實施態樣將涉及接觸溝槽開口及溝槽接點，但是應指出的是通孔開口及通孔接點(也稱為接點插塞或通孔插塞)可在這些實施態樣之任一實施態樣中被使用來代替接觸溝槽開口及溝槽接點。
隨著積體電路技術的推進，電晶體閘極距離逐漸按比例縮小。此閘極距離之按比例縮減已經導致一些新的棘手問題，其中之一為一方面溝槽接點200與擴散區106且另一方面與閘極102之間相當緊密的間距所造成之增加寄生電容(由第1A圖中的「C」來表示)。間隔物108有助於在溝槽接點200/擴散區106與閘極102之間提供大間距。習知的間隔物材料，諸如氮化矽，對減小此寄生電容作用甚微。遺憾的是，寄生電容使電晶體性能降級且使晶片功率增加。
因閘極距離按比例縮減所造成之另一棘手問題為接點與閘極(CTG)短路之形成。溝槽接點200之製程被設計成防止溝槽接點200與金屬閘極102實體接觸。當此一接觸發生時，一CTG短路產生，實際上破壞MOS電晶體。隨著電晶體閘極距離按比例縮小至100奈米(nm)以下，CTG短路已經成為一主要的良率限制因素。
用以減少CTG短路的現行方法包括控制對齊及圖案化具有較小臨界尺寸的接點。然而，隨著閘極距離按比例縮小，對齊要求變得難以滿足現存技術。例如，具有等於或少於100nm閘極距離的電晶體需要小於10nm的CD控制及層對齊控制以提供一可製造的製程範圍。因此，一接點與一閘極短路之可能性非常高。
第1B圖繪示當溝槽接點200未對準時的情形。相同的光蝕刻製程被使用，但是如圖所示者，溝槽接點200在一不完全位於二間隔物108之間之區域內的位置被形成。未對準導致溝槽接點200與閘極102中一閘極102實體接觸，從 而產生一接點與閘極短路。
依據本發明之實施態樣，一絕緣體帽式閘極可用以使接點與閘極短路之可能性減少到最低限度。在一實施態樣中，絕緣體帽層形成於閘極102頂上及MOS電晶體101之間隔物108內。在本發明之某些實施態樣中，絕緣體帽可佔間隔物之間存在之體積的很大一部分。例如，絕緣體帽可佔間隔物之間存在之體積的10%至80%，但是通常將佔此體積的20%至50%。閘極及閘極介電層佔剩餘體積的大部分。可用以形成絕緣體帽的材料將在下文中描述。
第2A圖繪示一依據本發明之一實施態樣的絕緣體帽式金屬閘極。一基體100在第2A圖中繪示，MOS電晶體101形成於其上。基體100可以是一使用一大矽基體或一絕緣體上覆矽底部構造而形成的晶態半導體基體。在其他實施態樣中，半導體基體可使用替換之材料被形成，該等材料可以或可以不與矽組合，包括但不限於鍺、銻化銦、碲化鉛、砷化銦、磷化銦、砷化鎵、碲化鎵或其他III-V族材料。儘管可形成基體的材料之一些範例在此處被描述，任一種可用作製造一半導體裝置之基礎的材料落入本發明之精神及範圍內。
每一MOS電晶體101可以是一平面電晶體，如第2A圖中所示者，或可以是一非平面電晶體，諸如雙閘極或三閘極電晶體。儘管本文所描述之實施態樣例示平面電晶體，但本發明並不限於平面電晶體。本發明之實施態樣還可用在非平面電晶體上，包括但不限於鰭式場效電晶體 (FinFET)或三閘極電晶體。每一MOS電晶體101包括由三層：一閘極介電層104、一閘極層102及一絕緣體帽層300所形成的一閘極堆疊。閘極介電層104可由一諸如二氧化矽的材料或一高k材料形成。可用在閘極介電層104中的高k材料之範例包括但不限於氧化鉿、矽酸鉿、氧化鑭、鋁酸鑭、氧化鋯、矽酸鋯、氧化鉭、氧化鈦、鈦酸鍶鋇、鈦酸鋇、鈦酸鍶、氧化釔、氧化鋁、鉭酸鈧鉛及鈮鋅酸鉛。在某些實施例中，閘極介電層104可具有大約1埃(Å)至大約50埃(Å)的厚度。在其他實施例中，附加的加工製程可在閘極介電層104上執行，諸如當一高k材料被使用時一退火製程用來改進其品質。
閘極層102形成於閘極介電層104上且可由至少一P型功函數金屬或一N型功函數金屬組成，視電晶體為一PMOS還是一NMOS電晶體而定。在某些實施態樣中，閘極層102可由二或更多個金屬層組成，其中至少一金屬層為一功函數金屬層且至少一金屬層為一填充金屬層。
對一PMOS電晶體而言，可用於閘極的金屬包括但不限於釕、鈀、鉑、鈷、鎳及導電金屬氧化物，例如氧化釕。一P型金屬層將使一具有大約4.9eV與大約5.2eV之間的一功函數的PMOS閘極能夠形成。對一NMOS電晶體而言，可用於閘極的金屬包括但不限於鉿、鋯、鈦、鉭、鋁、此類金屬之合金，及此類金屬之碳化物，諸如碳化鉿、碳化鋯、碳化鈦、碳化鉭及碳化鋁。一N型金屬層將使一具有大約3.9eV與大約4.2eV之間的一功函數的NMOS閘極能夠 形成。
絕緣體帽層300形成於閘極層102上且可由以下材料形成，該等材料包括但不限於氮化矽、氧化矽、碳化矽、摻雜有碳的氮化矽、氮氧化矽、其他氮化物材料、其他碳化物材料、氧化鋁、其他氧化物材料、其他金屬氧化物、氮化硼、碳化硼及其他低k介電材料或摻雜有碳、氮及氫中一或多者的低k介電材料。絕緣體帽層300將在下文更加詳細地描述。
一對間隔物108將閘極堆疊托住。間隔物108可由一種諸如氮化矽、氧化矽、碳化矽、摻雜有碳的氮化矽及氮氧化矽的材料形成。用以形成間隔物的製程是業界所習知的且通常包括沈積及蝕刻製程步驟。
擴散區106形成於基體100內且鄰近MOS電晶體101之閘極堆疊。對每一MOS電晶體101而言，一相鄰擴散區106作用為一源極區且另一相鄰擴散區106作用為一汲極區。
擴散區106可使用業界所習知的方法或製程而形成。在一實施態樣中，諸如硼、鋁、銻、磷或砷的摻雜物可植入基體100以形成擴散區106。在另一實施態樣中，基體100可首先被蝕刻以在擴散區106之位置形成凹槽。一磊晶沈積製程可接著被實施以利用一諸如鍺化矽或碳化矽的矽合金來填充該等凹槽，從而形成擴散區106。在某些實施態樣中，以磊晶方式沈積的矽合金可與諸如硼、砷或磷的摻雜物原位摻雜。在其他實施態樣中，替代材料可沈積到該等 凹槽中以形成擴散區106。
一或更多個ILD層110a/b沈積於MOS電晶體101上。ILD層110a/b可使用已知適用於積體電路結構中的介電材料，諸如低k介電材料而形成。可使用的介電材料之範例包括但不限於二氧化矽(SiO2)、碳摻雜氧化物(CDO)、氮化矽、有機聚合物，諸如全氟環丁烷或聚四氟乙烯、氟矽玻璃(FSG)，以及有機矽酸鹽，諸如矽倍半氧烷、矽氧烷或有機矽酸鹽玻璃。ILD層110a/b可包括用以進一步減小它們的介電常數的孔或其他空隙。
一溝槽接點200之製造，也稱為接點圖案化，涉及至少一光蝕刻製程及一蝕刻製程。光蝕刻製程形成一界定溝槽接點200之位置的光阻硬遮罩。該製程藉由在ILD層110b上沈積一光阻材料而開始。所沈積的光阻層透過一圖案化的光罩被暴露於紫外線輻射下，其中圖案界定溝槽接點200。該光阻層接著顯影以產生一包括一形成溝槽接點200的開口的光阻硬遮罩層。應指出的是光蝕刻製程是業界所習知的且此說明僅為一典型的光蝕刻製程之一簡要概述。許多中間步驟，諸如加溫烘烤及對準步驟，已被省略。
一旦光阻硬遮罩在適當的位置界定溝槽接點200，一蝕刻製程即可被實施。蝕刻劑蝕刻由光阻硬遮罩上的開口被暴露的ILD層110a/b之一部分，諸如溝槽接點200之開口。該蝕刻劑因而蝕刻出一下達擴散區106的溝槽開口。所使用的蝕刻製程可以是一習知的化學濕式蝕刻製程或一電漿乾式蝕刻製程。該蝕刻製程在一由T ETCH夾表示、 足以將ILD層110一直蝕刻到擴散區106的時段上實施。蝕刻出的溝槽開口接著被填充上述之一或更多金屬以形成溝槽接點200。
依據本發明之實施態樣，絕緣體帽層300具有一厚度，若接觸溝槽開口與絕緣體帽層對準，該厚度在溝槽接點200製造期間足以防止金屬閘極102暴露。此外，絕緣體帽層300具有足以在溝槽接點200形成之後使金屬閘極102與溝槽接點200電氣隔離的一厚度。在本發明之一實施態樣中，此厚度可從5nm變化到50nm。在另一實施態樣中，絕緣體帽層之高度可占閘極堆疊之總高度的20%到80%。用以形成接觸溝槽開口的蝕刻製程對絕緣體帽層300是選擇性地進行。這意味著濕式或乾式蝕刻化學品將蝕刻ILD層110a/b之材料但是將選擇性地中止且自我對準至絕緣體帽層300及側壁間隔物108。
依據本發明之實施態樣，絕緣體帽層300也具有一足以在整個T ETCH上耐受蝕刻製程而不使下方金屬閘極102暴露的厚度。以不同方式表述，絕緣體帽層300具有一起始厚度，該起始厚度足以在一將ILD層110a/b一直蝕刻到擴散區106，而絕緣體帽層300之任一部分未被減少至一容許金屬閘極102與後續形成的溝槽接點200之間具有導電性的厚度所需的時段上耐受蝕刻製程。在蝕刻製程之後，絕緣體帽層300與間隔物108之組合使金屬閘極102與溝槽接點200電氣隔離，從而消除CTG短路。
有若干不同方式來形成本發明之絕緣體帽層 300。在本發明之一實施態樣中，在閘極102使用一前閘極製程而形成的情況下，一毯覆介電層最初沈積在一基體上。接下來，一毯覆電極層沈積於該介電層頂上。最終，一毯覆絕緣層形成於該電極層頂上。用以沈積該介電層、該電極層及該絕緣層的沈積製程是業界所習知的且可包括但不限於諸如電鍍、無電鍍敷、化學氣相沈積、原子層沈積、物理氣相沈積及濺鍍的製程。該等三層接著使用諸如光蝕刻製程的習知圖案化製程而被蝕刻，以形成一由一閘極介電層104、一閘極層102及一絕緣體帽層300組成的閘極堆疊。間隔物108及擴散區106接著被形成於該閘極堆疊之兩側上。一ILD層110a沈積於該閘極堆疊、間隔物108及擴散區110上。一溝槽接點200可接著如上所述而形成。
在一前閘極製程之一替代實施態樣中，一毯覆介電層及一毯覆電極層可被沈積及圖案化以形成一由閘極介電層104及閘極102組成的閘極堆疊。一對間隔物108及擴散區106可形成於該閘極堆疊之任一側上。接下來，一蝕刻製程可被實施以在間隔物108內使金屬閘極102凹入，從而減小金屬閘極102之厚度。金屬閘極102之凹入導致間隔物108之間形成一溝槽，其中該溝槽之底面相當於凹入的金屬閘極102之頂面。金屬蝕刻製程後隨以一絕緣材料沈積製程，該製程沈積一絕緣材料毯覆層且填充間隔物108之間的溝槽。一研磨製程，諸如化學機械平坦化製程，用以研磨該絕緣材料層且實質上移除間隔物108外部的所有絕緣材料。移除此過量絕緣材料產生一實質上被容納在間隔物108 內的絕緣體帽層300。
在本發明之另一實施態樣中，一後閘極製程，諸如替換金屬閘極製程，是被用以形成閘極。在此實施態樣中，一毯覆介電層及一毯覆虛擬電極層最初可被沈積及圖案化以形成一由閘極介電層104及一虛擬閘極(圖未示)組成的閘極堆疊。應指出的是「虛擬」一詞用以表示此層是犧牲性的。用在虛擬層中的材料可以是或不是與用在非虛擬層中者相同的材料。例如，虛擬電極層可由用在實際的閘極中的多晶矽組成。一對間隔物108及擴散區106可形成於閘極堆疊之任一側上。接下來，虛擬閘極可被蝕刻掉以在間隔物108之間及閘極介電層104頂上形成一溝槽。一電極金屬層可接著被沈積以填充該溝槽。該電極金屬層可被研磨以移除間隔物108外部的金屬且將電極金屬限制到介於間隔物108之間的溝槽，從而形成一金屬閘極102。
如上所述者，一蝕刻製程被實施以使金屬閘極102在間隔物108內凹入。金屬閘極102之凹入導致間隔物108之間形成一溝槽。一絕緣材料沈積製程填充該溝槽且一研磨製程用以研磨該絕緣材料層且實質上移除間隔物108外部的所有絕緣材料。這產生一實質上被容納在間隔物108內的絕緣體帽層300。
第2B圖繪示一在兩個具有絕緣體帽層300的MOS電晶體之間被正確對準的溝槽接點200。在此例中，絕緣體帽300未被使用。
第2C圖繪示一形成於兩個具有絕緣體帽層300 的MOS電晶體之間的未對準溝槽接點200。如圖所示者，一部分的未對準溝槽接點200位於閘極102正上方。然而，不同於第1B圖中所示之先前技術電晶體，由於使用了絕緣體帽層300，故一CTG短路被避免。絕緣體帽層300使金屬閘極102與未對準溝槽接點200電氣隔離，從而使溝槽接點200「自我對準」成為可能。
第3A至3C圖繪示第2A圖之電晶體之略微變化。在第3A圖中，一替換金屬閘極製程之一不同的實施態樣用以形成電晶體。在此實施態樣中，一毯覆虛擬介電層及一毯覆虛擬電極層沈積於一基體上。此處，該虛擬電極層可由多晶矽組成且該虛擬介電層可由二氧化矽組成，此二者皆用在實際的閘極及實際的閘極介電層中。此二虛擬層被蝕刻以形成一由一虛擬閘極介電層及一虛擬閘極層組成的閘極堆疊。間隔物108及擴散區106接著形成於閘極堆疊之兩側上。一ILD層110a沈積於該閘極堆疊、間隔物108及擴散區106上。ILD層110a被平坦化以使該虛擬電極層暴露。
接下來，該虛擬電極層及該虛擬閘極介電層使用一或更多個蝕刻製程而被移除。移除虛擬層使間隔物108之間產生一溝槽。基體100形成該溝槽之一底面。一新的高k閘極介電層104使用一化學氣相沈積製程或一原子層沈積製程而被沈積到該溝槽中。該高k閘極介電層104沿該溝槽之底部及側壁而沈積，從而形成一「U」形閘極介電層104，如第3A圖中所示者。接下來，一金屬閘極層102沈積於高k閘極介電層104上。用以形成金屬閘極102的製程是業界所 習知的。
依據本發明之實施態樣，最終金屬閘極102不完全填充溝槽。在一實施態樣中，金屬閘極102最初可完全填充該溝槽，但是一後續的蝕刻製程可使金屬閘極102凹入。在另一實施態樣中，金屬閘極沈積製程僅以金屬閘極102部分地填充溝槽。在此二實施態樣中，一溝槽仍在間隔物108之間存在於最終金屬閘極102上方。
最終，一絕緣材料沈積製程被用以沈積一絕緣材料毯覆層以填充間隔物108之間的溝槽。接著，一研磨製程，諸如化學機械平坦化製程，用以研磨該絕緣材料層且實質上移除間隔物108外部的任何絕緣材料。此一過量絕緣體之移除產生一實質上被限制在間隔物108內的絕緣體帽層300。如第3A圖中所示者，絕緣體帽300也被限制在閘極介電層104之側壁部分內。
第3B圖繪示一在兩個具有絕緣體帽層300的MOS電晶體之間正確地被對準的溝槽接點200。第3C圖繪示一形成於兩個具有絕緣體帽層300的MOS電晶體之間的未對準溝槽接點200。同樣，未對準溝槽接點200之一部分位於閘極102正上方。由於使用了使金屬閘極102與未對準溝槽接點200電氣隔離的絕緣體帽層300，故避免了CTG短路。
第4A至4C圖繪示第3A圖之電晶體之一略微變化。在第4A圖中，一替換閘極製程被再次用以形成具有一「U」形閘極介電層104的電晶體。閘極層102及閘極介電層104最初使用上文針對第3A圖而詳述的相同製程而形成。不 同於第3A圖，在此實施態樣中，「U」形閘極介電層104與金屬閘極102二者皆在絕緣體帽層300製成之前被凹入。一或更多蝕刻製程可用以使此二結構凹入。絕緣體帽300接著使用上文針對第3A圖而描述的相同製程而形成且既位於閘極102之頂上也位於一部分的閘極介電層104之頂上，如第4A圖中所示者。第4B圖繪示一正確地對準在兩個具有絕緣體帽層300的MOS電晶體之間的溝槽接點200。第4C圖繪示一形成於兩個具有絕緣體帽層300的MOS電晶體之間的未對準溝槽接點200。同樣，一部分之未對準溝槽接點200位於閘極102正上方。由於使用了使金屬閘極102與未對準溝槽接點200電氣隔離的絕緣體帽層300，故避免了CTG短路。
第5A至5F圖繪示一可與一MOS電晶體一起使用的替代絕緣體帽層之製造。最初，第5A圖繪示包括一虛擬閘極500及一虛擬閘極介電層502的二MOS電晶體。還繪示有通常由氮化矽形成的一對間隔物108。
依據本發明之實施態樣，一或多個蝕刻製程被實施以使虛擬閘極層500與間隔物108二者部分地凹入。此雙凹槽在第5B圖中繪示。用以使虛擬閘極500凹入的蝕刻化學品可能與用以使間隔物108凹入的蝕刻化學品不同。所使用的蝕刻製程可能是濕式蝕刻、乾式蝕刻或一組合。當虛擬閘極500及間隔物108已被凹入時，一溝槽503a形成於ILD層110a內，其中虛擬閘極500及間隔物108之頂面形成該溝槽之底部。
轉而參照第5C圖，一或更多蝕刻製程被實施以 完全地移除虛擬閘極500以及虛擬閘極介電質502。用以完全地移除虛擬閘極500及虛擬閘極介電質的蝕刻製程是業界所習知的。同樣，這些蝕刻可以是濕式蝕刻、乾式蝕刻或一組合。如第5C圖中所示者，溝槽503a現在更加深且具有一頂部相對較寬且底部相對較窄的截面。虛擬閘極500及虛擬閘極介電質502被整體移除，從而暴露基體100之頂部。
在第5D圖中，一閘極介電層104及一金屬閘極層102沈積於溝槽503a中。一保形沈積製程，諸如CVD或ALD製程，通常用以沈積閘極介電層104，產生一覆蓋在溝槽503a之側壁及底面上的保形介電層104。金屬閘極層102填充溝槽503a之剩餘部分。在本發明之某些實施態樣中，金屬閘極層102可由二或更多金屬層組成，例如一功函數金屬層及一填充金屬層。
在一替換金屬閘極流程中，利用金屬閘極材料，尤其是利用具有等於或少於22nm閘極寬度的電晶體來填充窄閘極溝槽非常困難。第5A至5D圖中所描述之流程藉由加寬溝槽開口頂部而不影響溝槽底部的狹窄寬度而改善了本質填充特性。因此，頂部開口相對較寬的溝槽503a之截面導致一具有更少空隙或其他缺陷的改良金屬閘極沈積。
接下來，金屬閘極層102及閘極介電層104如第5E圖中所示般凹入，形成一溝槽503b。同樣，一或更多蝕刻製程，即濕式或乾式蝕刻製程，可用以使閘極層102及閘極介電層104二者凹入。所使用的蝕刻製程必須對ILD層110a是選擇性地進行。金屬閘極102被凹入直到其頂面與間隔物 108齊平於或低於間隔物108之頂面為止。儘管在第5D圖中部分的金屬閘極102位於間隔物108之頂部上，重要的是在第5E圖中，金屬閘極102被凹入之後，金屬閘極102並無餘留在間隔物108頂部上的部分。這是因為任何餘留在間隔物108頂上的金屬閘極102部分最終可能與一未對準溝槽接點形成一CTG短路。
轉而參照第5F圖，一絕緣材料沈積製程填充溝槽503b且一研磨製程用以研磨該絕緣材料層並實質上移除溝槽503b外部的所有絕緣材料。這產生一實質上容納在溝槽503b內的絕緣體帽層504。由於絕緣體帽層504在間隔物108上橫向延伸而具有一蘑菇頂部外觀。絕緣體帽層504藉由在閘極間隔物108上延伸而改進接點與閘極邊緣。絕緣體帽層504可由包括但不限於下列的材料形成：氮化矽、氧化矽、碳化矽、摻雜有碳的氮化矽、氮氧化矽、其他氮化物材料、其他碳化物材料、氧化鋁、其他氧化物材料、其他金屬氧化物及低k介電材料。
第5G圖繪示覆蓋絕緣體帽層504且位於第一ILD層110a頂上的一附加ILD層110b之沈積。第5H圖繪示一已製作成穿過ILD層110a及110b下達至擴散區106的溝槽接點200。第5H圖之溝槽接點200已正確地被對準在相鄰電晶體之間隔物108之間。
第5I圖繪示一未對準的溝槽接點200。如圖所示者，即使溝槽接點200位於金屬閘極102之頂部上，絕緣帽層504也藉由使金屬閘極102與未對準溝槽接點200電氣隔 離而保護金屬閘極102且防止形成CTG短路。
由絕緣帽層504提供的另一優勢解決與第1A圖相關地在上文中討論的寄生電容問題。寄生電容問題由一側的溝槽接點200及擴散區106與另一側的閘極102之間的相對較緊密的間距所致。間隔物108有助於在溝槽接點200/擴散區106與閘極102之間提供大間距，但是習知的間隔物材料，諸如氮化矽，對減小此寄生電容作用甚微。然而，因為產生一溝槽接點200之接觸溝槽開口的蝕刻製程對氮化矽是選擇性地進行，故氮化矽仍被使用。
依據本發明之此一實施態樣，除了氮化矽以外的材料可使用在間隔物108中。此處，在用以製造溝槽接點200的蝕刻製程期間，橫向延伸的絕緣帽層504保護下方間隔物108。此類蝕刻製程通常為各向異性製程，因此，蝕刻化學品僅需要對絕緣帽層504選擇性地進行。絕緣帽層504可接著掩蓋下方間隔物108。故利用一各向異性製程，使用絕緣帽層504意味著蝕刻化學品不一定需要對間隔物108所使用的材料是選擇性的。這解除了間隔物材料選擇上的任何限制條件而能使用對電容而言最佳化的材料。舉例而言，諸如氮氧化矽(SiON)、碳摻雜的氮氧化矽(SiOCN)或低k介電材料的材料可用在間隔物108中以減少關於寄生電容的問題。
第6A至6F圖繪示一依據本發明之一實施態樣結合一絕緣帽層的階狀金屬閘極之形成。最初，第6A圖繪示包括一虛擬閘極500及一虛擬閘極介電層502的二MOS電晶 體。轉而參照第6B圖，一或更多蝕刻製程被實施以完全地移除虛擬閘極500以及虛擬閘極介電質502。用以完全地移除虛擬閘極500及虛擬閘極介電質的蝕刻製程是業界習知的。虛擬閘極500及虛擬閘極介電質502被整體移除，從而曝露基體100之頂部。
第6C圖繪示雙金屬閘極層：一保形金屬閘極層102a及一可以是或不是保形層的第二金屬層102b之沈積。初始金屬閘極層102a可使用一諸如化學氣相沈積或原子層沈積的保形沈積製程而沈積。諸如物理氣相沈積或濺鍍的其他製程也可被使用。由於層102b不必為一保形層，故第二金屬閘極102b使用一諸如化學氣相沈積、原子層沈積、物理氣相沈積、濺鍍的習知沈積製程、或甚至諸如電鍍或無電鍍敷的製程而沈積。
初始金屬閘極層102a典型地為一功函數金屬層且可使用上述任一種功函數金屬而形成。第二金屬閘極層102b可以是一第二功函數金屬層或其可以是一低電阻填充金屬層，諸如鋁、鎢或銅。依據本發明之實施態樣，用在金屬閘極102a中的金屬與用在金屬閘極102b中的金屬具有不同的蝕刻特性。
轉而參照第6D圖，雙金屬閘極層102a及102b被蝕刻且被製作凹槽以形成溝槽600，絕緣帽層可在其中被製作。依據本發明之一實施態樣，蝕刻製程移除金屬層102a的部分比移除金屬層102b的部分大。這對金屬閘極102產生一階狀或插塞形輪廓，如第6D圖中所示者。整個金屬閘極 102之一中間部分相對厚於整個金屬閘極102之外緣部分。以不同方式表述，金屬閘極102之一中間部分具有一比金屬閘極102之側部相對更大的高度。此一金屬閘極102之階狀輪廓提供如下文在第6F圖中所說明之優勢。
在一實施態樣中，一單一的蝕刻製程被使用，其以一比對金屬閘極層102b更快的速率蝕刻金屬閘極層102a。換言之，蝕刻化學品對金屬閘極102b更具有選擇性。在另一實施態樣中，二蝕刻製程可被使用，一個製程用於金屬層102a且另一製程用於金屬層102b。若二蝕刻製程被使用，金屬層102a必然相對於金屬層102b被移除一較大部分。因此，在一實施態樣中，該等二蝕刻製程中之第一製程可對金屬層102b具有選擇性且該等二蝕刻製程中之第二製程可對金屬層102a具有選擇性。所使用的蝕刻製程可以是濕式蝕刻、乾式蝕刻或其一組合。熟於此技者將瞭解的是對用在金屬層102a及102b中的幾乎所有任意的成對金屬而言，可以找到在二金屬之間區別作用的一濕式或乾式化學蝕刻。
如第6E圖中所示者，一絕緣材料沈積製程填充溝槽600且一研磨製程用以研磨該絕緣材料層且實質上移除溝槽600外部的所有絕緣材料。這產生一實質上容納在溝槽600內的絕緣體帽層602。由於金屬閘極102之階狀輪廓，絕緣體帽層602之外緣相對較厚且其中間部分相對較薄。絕緣體帽層602可由包括但不限於下列的材料形成：氮化矽、氧化矽、碳化矽、摻雜有碳的氮化矽、氮氧化矽、其他氮化 物材料、其他碳化物材料、氧化鋁、其他氧化物材料、其他金屬氧化物及低k介電材料。
第6F圖繪示一未對準的溝槽接點200。如圖所示者，即使溝槽接點200位於金屬閘極102之頂部上，絕緣體帽層602也藉由使金屬閘極102與未對準的溝槽接點200電氣隔離而保護金屬閘極102且防止CTG短路形成。金屬閘極102之階狀輪廓提供至少二優勢。首先，該階狀輪廓使絕緣體帽層602之厚部位於金屬閘極102與溝槽接點200之間，從而提供強大電氣隔離。其次，該階狀輪廓容許金屬閘極102之中間部分仍然保持是厚的，從而藉由增加金屬閘極102之金屬含量而減小其電阻。在本發明之各種不同的實施態樣中，階狀輪廓可藉由試圖使金屬閘極102之中間部分之體積或寬度最大化，同時維持與未對準的溝槽接點200電氣隔離而被最佳化。在某些實施態樣中，這可藉由增加金屬閘極102b之大小或厚度而實現。在其他實例中，這可藉由使用多於二金屬閘極層以更精細地製作階狀輪廓而實現。
依據本發明之另一實施態樣，第7A至7C圖繪示一將第5F圖之寬絕緣體帽層504與第6D至6F圖之階狀輪廓金屬閘極102組合的MOS電晶體之製造。從第5C圖中所示之結構開始，雙金屬閘極層如第7A圖中所示般沈積。一層為一保形金屬閘極層102a且另一層為一可以是或不是保形層的第二金屬層102b。初始金屬閘極層102a典型地為一功函數金屬層且第二金屬閘極層102b可以是一第二功函數金屬層或其可以是一填充金屬層。依據本發明之實施態樣，用在 金屬閘極102a中的金屬與用在金屬閘極102b中的金屬具有不同的蝕刻特性。
轉而參照第7B圖，雙金屬閘極層102a及102b以及閘極介電層104被蝕刻且被凹入。蝕刻製程對金屬閘極102b選擇性地進行。這使金屬閘極102產生一階狀輪廓，如第7B圖中所示者。整個金屬閘極102之一中間部分相對厚於整個金屬閘極102之外緣部分。
一絕緣材料接著被沈積且平坦化以在每一金屬閘極102頂上形成絕緣體帽層700。這在第7C圖中被繪示。同時有一未對準的溝槽接點200繪示於圖中。金屬閘極102之階狀輪廓容許絕緣體帽層700之厚部使金屬閘極102與溝槽接點200電氣隔離。該階狀輪廓還容許金屬閘極102之一中間部分仍然是厚的，從而減小電阻。在此實施態樣中，絕緣帽層700延伸在凹入的間隔物108上方，從而在溝槽接點200蝕刻製程期間保護間隔物並容許對於減小溝槽接點200與金屬閘極102之間的寄生電容最佳化的一材料被利用在間隔物108中。
第8A至8F圖繪示本發明之另一實施態樣，其中接點側壁間隔物用以減少CTG短路且改善寄生電容問題。第8A圖繪示一已蝕刻穿過ILD層110a及110b下達擴散區106的接觸溝槽開口800。如上文所說明者，光蝕刻圖案化及蝕刻製程用以形成接觸溝槽開口800。
第8A圖中還繪示有一已在接觸溝槽開口800之底部形成的矽化物層802。為了製作矽化物層802，一習知 的金屬沈積製程，諸如濺鍍沈積製程或ALD製程，可用以沿至少接觸溝槽開口800之底部形成一保形金屬層。通常金屬也將沈積在接觸溝槽開口800之側壁上。金屬可包括鎳、鈷、鉭、鈦、鎢、鉑、鈀、鋁、釔、鉺、鐿或作為矽化物之良好候選者的任一種其他金屬。一退火製程可接著被實施以使金屬與擴散區106發生反應且形成一矽化物層802。任何未發生反應的金屬可使用習知製程被選擇性地移除。矽化物層802減小後來形成的溝槽接點200與擴散區106之間的電阻。
第8B圖繪示依據本發明之一實施態樣沿接觸溝槽開口800之側壁而形成的一對接點側壁間隔物804。接點側壁間隔物804可使用類似於閘極間隔物108之製作的沈積及蝕刻製程而形成。例如，一絕緣材料之一保形層可沈積在接觸溝槽開口800內，導致該絕緣材料沿接觸溝槽開口800之側壁及底面而沈積。該絕緣材料可以是氧化矽、氮化矽、氮氧化矽(SiON)、碳摻雜的氮氧化矽(SiOCN)、任一種其他氧化物、任一種其他氮化物或任一種低k介電材料。接下來，一各向異性蝕刻製程用以從接觸溝槽開口800之底部上以及從諸如ILD層110b之表面的其他區域上移除該絕緣材料。這產生第8B圖中所示之接點側壁間隔物804。
熟於此技者將瞭解的是，一單獨的圖案化製程可用以形成下達金屬閘極102的通孔以形成閘極接點。此單獨的圖案化製程將典型地涉及利用一犧牲性光定義抗蝕層來塗佈晶圓，蝕刻閘極接點，且接著利用一濕式或乾式清洗 製程或其某一組合來移除該光阻劑。此單獨的圖案化製程通常在接觸溝槽開口800已形成之後實施，這意味著首先塗佈抗蝕劑且接著濕式或乾式清洗化學品進入接觸溝槽開口800且可使矽化物層802降級。因此，依據本發明之一實施態樣，用以形成間隔物804的絕緣材料保形層在閘極接點的圖案化製程之前沈積。該保形層維持在適當的位置以保護矽化物層802直到閘極接點已被圖案化為止。接著上文所述之各向異性蝕刻可被實施以蝕刻該保形層且形成間隔物804。
應指出的是矽化物層802在接點側壁間隔物804製成之前，即當接觸溝槽開口800處於其最大寬度時形成。藉由在接點側壁間隔物804形成之前形成矽化物層802，一相對較寬的矽化物層802可被形成以提供較佳的電阻特性，諸如較低的本質接觸電阻。若接點側壁間隔物804先形成，則較少的擴散區106將在矽化物製程中暴露，產生一相對較短的矽化物層。
一金屬沈積製程接著被實施以填充接觸溝槽開口800且形成溝槽接點200，如第8C圖中所示者。如上文所提到者，金屬沈積製程可以是任一種金屬沈積製程，諸如電鍍、無電鍍敷、化學氣相沈積、物理氣相沈積、濺鍍或原子層沈積。所使用的金屬可以是提供適合的接觸特性的任一種金屬，諸如鎢或銅。一金屬內襯，諸如鉭或氮化鉭內襯，通常先於金屬而被沈積。一CMP製程用以移除任一種過量金屬且完成溝槽接點200之製作。
接點側壁間隔物804在閘極102與溝槽接點200之間提供一附加保護層。最終溝槽接點200具有一比使用習知製程而形成的溝槽接點200相對較窄的寬度，從而減小CTG短路之可能性。且閘極102與溝槽接點200之間的附加絕緣層減小寄生電容。
第8D至8F圖繪示當接點未對準時接點側壁間隔物804之製作。第8D圖繪示已蝕刻穿過ILD層110a及110b下達至擴散區106的一未對準接觸溝槽開口800。依據本發明之一實施態樣，絕緣帽層300防止金屬閘極102在此蝕刻製程期間暴露。第8D圖中還繪示有一已在接觸溝槽開口800之底部形成的矽化物層802。用於矽化物層802的製程已在上文提供。
第8E圖繪示依據本發明之一實施態樣沿接觸溝槽開口800之側壁而形成的一對接點側壁間隔物804。接點側壁間隔物804可藉由沈積及蝕刻一絕緣材料之一保形層而形成，如上文所說明者。
一金屬沈積製程接著被實施以填充接觸溝槽開口800且形成溝槽接點200，如第8F圖中所示者。同樣，接點側壁間隔物804在閘極102與溝槽接點200之間提供一附加保護層。接點側壁間隔物804在最終溝槽接點200與金屬閘極102之間提供更大間距，從而減小CTG短路之可能性。且閘極102與溝槽接點200之間的附加絕緣層減小寄生電容。
第9A至9D圖繪示用以形成一依據本發明之一實 施態樣的絕緣體帽層的另一製程。第9A圖繪示兩個具有金屬閘極102及閘極介電層104的MOS電晶體。閘極層102可包括兩層或更多層(圖未示)，諸如功函數金屬層及填充金屬層。儘管所示之閘極介電層104對應於一替換金屬閘極製程，以下製程也可與使用一前閘極方法而形成的電晶體配合使用。
一金屬帽900形成於金屬閘極102頂上，如第9A圖中所示者。依據本發明之實施態樣，金屬帽900使用一選擇性的沈積製程而形成。某些選擇性沈積製程包括但不限於無電鍍敷及化學氣相沈積。可被選擇性沈積的金屬包括但不限於鈷、鎳、鉑、銅、多晶矽、鎢、鈀、銀、金及其他貴金屬。熟於此技者將瞭解的是選擇使用一無電製程還是一CVD製程將依金屬閘極102之組成與用在金屬帽900中的特定金屬而定。在一範例中，若金屬閘極102之頂部由銅金屬組成，則鈷金屬可以無電方式沈積於銅上。在另一範例中，鎢或多晶矽可藉由CVD而沈積在用在金屬閘極102中的幾乎任一種金屬上。在另一範例中，若金屬閘極102之頂部由一貴金屬組成，則大多數金屬可使用一無電製程而沈積在貴金屬上。熟於此技者將瞭解的是，一般來說，無電製程需要基體金屬及欲被沈積金屬兩者皆為貴金屬。因此，諸如鈷、鎳、銅、鉑、鈀、金及銀的金屬之組合是可能的。
轉而參照第9B圖，一ILD層902毯覆沈積於ILD110a及金屬帽900上。一CMP製程接著用以使ILD層902及金 屬帽900平坦化且使它們的頂面實質上是平坦的。這是為了在ILD沈積之後暴露金屬帽900之頂面。
接下來，如第9C圖中所示者，一蝕刻製程用以從ILD層902內移除金屬帽900。在一實施態樣中，一濕式蝕刻化學品可被應用以移除金屬帽900。依據本發明之實施態樣，所使用的蝕刻化學品必須對ILD層902及金屬閘極102具選擇性。這使金屬帽900在對ILD層902及金屬閘極102影響最小之下被移除。移除金屬帽900使ILD層902內產生空隙904。
轉而參照第9D圖，一絕緣層，諸如氮化矽層，可被沈積及平坦化以填入空隙904，從而形成自我對準絕緣帽層906。此絕緣層通常沈積為填充空隙904且覆蓋ILD層902的一毯覆層。一平坦化製程接著用以移除空隙904外部的所有過量材料。這將絕緣材料局限至空隙904，從而形成絕緣帽層906。絕緣體帽層906可由包括但不限於下列的材料形成：氮化矽、氧化矽、碳化矽、摻雜有碳的氮化矽、氮氧化矽、其他氮化物材料、其他碳化物材料、氧化鋁、其他氧化物材料、其他金屬氧化物及低k介電材料。唯一的限制條件為用在絕緣體帽層906中的材料不同於用在ILD層902中的金屬。
第10A至10G圖繪示一依據本發明之一實施態樣，在溝槽接點200頂上形成一自我對準金屬銷、且在溝槽接點200頂上形成進一步使金屬銷與金屬閘極102絕緣的一對絕緣間隔物的製程。第10A圖繪示兩個具有金屬閘極102 及閘極介電層104的MOS電晶體。一溝槽接點200形成於二MOS電晶體之間。
一金屬帽900形成於溝槽接點200頂上，如第10A圖中所示者。依據本發明之實施態樣，金屬帽900使用一選擇性沈積製程而形成。如上文所提到者，選擇性沈積製程包括但不限於無電鍍敷及化學氣相沈積。上文所述與金屬閘極102一起使用之相同的金屬及製程也可在此與溝槽接點200一起使用。所使用的選擇性沈積製程及用在金屬帽900中的金屬將依用在溝槽接點200中的金屬而定。
依據本發明之實施態樣，一選擇性沈積製程被選擇，其將僅在溝槽接點200而不在金屬閘極102上沈積金屬。這可藉由在溝槽接點200及金屬閘極102中使用不同類型的金屬而完成。例如，若鋁用在金屬閘極102中且一貴金屬用在溝槽接點200中，則一選擇性沈積製程可用以僅在溝槽接點200中的貴金屬上沈積金屬帽900。上述貴金屬之相同組合在此也可行。在本發明之某些實施態樣中，當一種活性金屬，諸如鋁、鎢、鉬、鈦、鉭、氮化鈦或多晶矽使用在金屬閘極102中時，一種貴金屬，諸如鈷、鎳、銅、鉑、鈀、金及銀可用在溝槽接點200中。
轉而參照第10B圖，一ILD層902毯覆沈積在ILD110a及金屬帽900上。一CMP製程接著使ILD層902及金屬帽900二者平坦化且使它們的頂面實質上是平坦的。這是為了在ILD沈積之後暴露金屬帽900之頂面。
接下來，如第10C圖中所示者，一蝕刻製程用以 僅從ILD層902內移除金屬帽900。所使用的蝕刻化學品必須是對ILD層902與溝槽接點200皆具選擇性。這使金屬帽900在對ILD層902及溝槽接點200影響最小之下被移除。移除金屬帽900使ILD層902內產生一空隙904。
轉而參照第10D圖，一絕緣層906可毯覆沈積在ILD層902上方及空隙904內。絕緣層906可由包括但不限於下列的材料形成：氮化矽、氧化矽、碳化矽、摻雜有碳的氮化矽、氮氧化矽、其他氮化物材料、其他碳化物材料、氧化鋁、其他氧化物材料、其他金屬氧化物及低k介電材料，包括與用在ILD層902中的材料相同或類似之材料。
接下來，一蝕刻製程，諸如各向異性蝕刻製程，被應用以蝕刻絕緣層906且形成間隔物1000。這在第10E圖中繪示。該蝕刻製程也在二間隔物1000之間產生一溝槽1002。
轉而參照第10F圖，一金屬沈積製程用以在間隔物1000之間之溝槽1002中且在溝槽接點200頂上沈積一自我對準金屬銷1004。在某些實施態樣中，此金屬沈積製程可以是另一選擇性的沈積製程，而在其他實施態樣中，此金屬沈積製程不需要是一選擇性製程。最終，如第10G圖中所示者，一絕緣層可被沈積及平坦化以形成一ILD層1006。金屬銷1004之頂部也被平坦化以與ILD層1006齊平。依據本發明之實施態樣，自我對準金屬銷1004藉由間隔物1000防止與閘極之短路。
因此，此處描述的本發明實施態樣形成自我對準 至閘極的蝕刻中止結構，其防止接點蝕刻暴露閘極而造成閘極與接點短路。即使在接點圖案覆蓋在閘極上的情況下，一接點與閘極短路也不會發生。本發明之實施態樣還解決諸如溝槽接點與閘極之間之寄生電容、介質崩潰或接點與閘極之直接短路及閘極接點圖案化期間接點矽化物降級的問題。
因此，使用一絕緣體帽層可實現自我對準接點，這提供一穩健的可製造程序。本發明使對圖案化限制更為堅固的較寬接點之初始圖案化成為可能。較寬接點對一穿通接點矽化物流程也是理想的。這不僅消除了接點與閘極短路的一主要的良率限制因素，而且還減少了接點圖案化的主要限制條件且容許更多變化性。從一微影術的角度來看，使用一絕緣體帽層增大對準窗且容許更多的臨界尺寸變化性。從一蝕刻的觀點來看，使用一絕緣體帽層使MOS電晶體製程能夠更加容許不同輪廓、不同的臨界尺寸及溝槽接點形成期間ILD之過蝕刻。
本發明例示實施態樣的以上說明，包括摘要中之記述，並非詳盡無遺或將本發明限制為所揭露之精確形式。雖然本發明之特定實施態樣及範例在本文為了說明目的而被描述，在相關技藝中具有通常知識者將認識到的是在本發明範圍內做各種不同的等效修改是可能的。
本發明可根據上述詳細說明作此類修改。使用在以下申請專利範圍中的用詞不應被理解為將本發明限制到說明書及申請專利範圍中所揭露之特定實施態樣。反之， 本發明之範圍應完全由要依據已確立的申請專利範圍解釋原則解釋的以下申請專利範圍決定。

Claims (22)

  1. 一種積體電路結構，其包含：一基板，其包含矽；一閘極結構，其在該基板上方，該閘極結構包含一閘極介電質以及一閘極電極；一第一介電閘極間隔物，其鄰接該閘極結構之一第一側；一第二介電閘極間隔物，其鄰接該閘極結構之一第二側；一第一源極或汲極區，其在該閘極結構之該第一側；一第二源極或汲極區，其在該閘極結構之該第二側；一導電接觸結構，其在該第一源極或汲極區上；一第一介電層，其在該閘極結構之一部分上，該第一介電層具有在該導電接觸結構之一部分上之一開口；一第一介電接觸間隔物，其沿該第一介電層之該開口之一第一側壁延伸；一第二介電接觸間隔物，其沿該第一介電層之該開口之一第二側壁延伸；一金屬結構，其在該第一介電接觸間隔物與該第二介電接觸間隔物之間，該金屬結構與該導電接觸結構之該部分接觸；以及 一第二介電層，其在該第一介電層上。
  2. 如請求項1之積體電路結構，其中該金屬結構係穿過並且在該第一介電層上方。
  3. 如請求項2之積體電路結構，其中該第一介電層上方之該金屬結構之一部分具有大於與該導電接觸結構接觸之該金屬結構之一部分之一寬度的一寬度。
  4. 如請求項1之積體電路結構，其中該第二介電層具有與該金屬結構之一頂面共平面的一頂面。
  5. 如請求項1之積體電路結構，其中導電接觸結構具有與該閘極結構之該閘極電極之一頂面共平面的一頂面。
  6. 如請求項1之積體電路結構，其進一步包含橫向地在該第一介電閘極間隔物與該導電接觸結構之間的一介電材料。
  7. 如請求項6之積體電路結構，其中該第一介電層係在該閘極電極、該介電材料、以及該第一與第二介電閘極間隔物上。
  8. 一種積體電路結構，其包含：一基板，其包含矽；一閘極結構，其在該基板上方，該閘極結構包含一閘極介電質以及一閘極電極；一第一間隔物，其鄰接該閘極結構之一第一側；一第二間隔物，其鄰接該閘極結構之一第二側；一第一擴散區，其在該閘極結構之該第一側；一第二擴散區，其在該閘極結構之該第二側； 一導電接觸結構，其在該第一擴散區上；一第一介電層，其在該閘極結構之一部分上，該第一介電層具有在該導電接觸結構之一部分上之一開口；一第三間隔物，其沿著該第一介電層之該開口之一第一側壁延伸；一第四間隔物，其沿著該第一介電層之該開口之一第二側壁延伸；一金屬銷，其在該第三間隔物與該第四間隔物之間，該金屬銷係與該導電接觸結構之該部分接觸；以及一第二介電層，其在該第一介電層上。
  9. 如請求項8之積體電路結構，其中該金屬銷係穿過並且在該第一介電層上方。
  10. 如請求項9之積體電路結構，其中該第一介電層上方之該金屬銷之一部分具有大於與該導電接觸結構接觸之該金屬銷之一部分之一寬度的一寬度。
  11. 如請求項8之積體電路結構，其中該第二介電層具有與該金屬銷之一頂面共平面之一頂面。
  12. 如請求項8之積體電路結構，其中該導電接觸結構具有與該閘極結構之該閘極電極之一頂面共平面之一頂面。
  13. 如請求項8之積體電路結構，其進一步包含橫向地在該第一間隔物與該導電接觸結構之間的一介電材料。
  14. 如請求項13之積體電路結構，其中該第一介電層係在該閘極電極、該介電材料以及該第一與第二間隔物上。
  15. 一種製造一積體電路結構之方法，該方法包含： 一基板包含矽；於包含矽之基板上方形成一閘極結構，該閘極結構包含一閘極介電質以及一閘極電極；形成鄰接該閘極結構之一第一側之一第一介電閘極間隔物；形成鄰接該閘極結構之一第二側之一第二介電閘極間隔物；在該閘極結構之該第一側形成一第一源極或汲極區；在該閘極結構之該第二側形成一第二源極或汲極區；在該第一源極或汲極區上形成一導電接觸結構；在該閘極結構之一部分上形成一第一介電層；在該第一介電層中形成一開口，該開口在該導電接觸結構上；在該第一介電層上以及在該第一介電層中之該開口中形成一絕緣層；蝕刻該絕緣層，用以形成沿著該第一介電層之該開口之一第一側壁延伸之一第一介電接觸間隔物、用以形成沿著該第一介電層之該開口之一第二側壁延伸之一第二介電接觸間隔物、以及用以暴露該接觸結構之一部分；形成一金屬結構於該第一介電接觸間隔物與該第二介電接觸間隔物之間，該金屬結構與該導電接觸結構 之該部分接觸；以及在該第一介電層上形成一第二介電層。
  16. 如請求項15所述之方法，其中形成該金屬結構包含：形成一金屬於該第一介電接觸間隔物與該第二介電接觸間隔物之間，該金屬更進一步於該第一介電層之一部分上方並且覆蓋在該第一介電層之該部分上；以及平坦化該金屬以形成該金屬結構。
  17. 如請求項15所述之方法，其中形成該金屬結構以及該第二介電層包含：形成一金屬於該第一介電接觸間隔物與該第二介電接觸間隔物之間，該金屬更進一步於該第一介電層之一部分上方並且覆蓋在該第一介電層之該部分上；形成一第二絕緣層於該第一介電層上，該第二絕緣層具有一開口，該金屬係在該開口中；以及平坦化該第二絕緣層以及該金屬以形成該金屬結構以及該第二介電層。
  18. 如請求項15所述之方法，其中形成該金屬結構以及該第二介電層包含：形成一金屬於該第一介電接觸間隔物與該第二介電間隔物之間，該金屬更進一步於該第一介電層之一部分上方並且覆蓋在該第一介電層之該部分上；形成一第二絕緣層於該第一介電層以及該金屬之上；平坦化該第二絕緣層以及該金屬以形成該金屬結 構以及該第二介電層。
  19. 如請求項18所述之方法，其中該第二介電層具有與該金屬結構之一頂面共平面之一頂面。
  20. 如請求項15所述之方法，其中該金屬結構係穿過並且在該第一介電層上方。
  21. 如請求項20所述之方法，其中在該第一介電層上方之該金屬結構之一部分具有大於與該導電接觸結構接觸之該金屬結構之一部分之一寬度的一寬度。
  22. 如請求項15所述之方法，其中該導電接觸結構具有與該閘極結構之該閘極電極之一頂面共平面之一頂面。
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