JP2012181916A - 複数の独立したシリアルリンクメモリ - Google Patents
複数の独立したシリアルリンクメモリ Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
- G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/30—Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
Abstract
【解決手段】一例では、リンクがバンクと独立している、複数のシリアルデータリンクおよび複数のメモリバンクを備えるフラッシュメモリ装置が開示される。エコー信号ラインを使用して、フラッシュメモリ装置をデイジーチェーン構成においてカスケードし、メモリ装置間で連続的に通信してもよい。さらに、単一リンクを使用して複数のリンクをエミュレートする仮想複数リンク構成が記載されている。
【選択図】図1A
Description
104 シリアルデータリンクインターフェイス
106 メモリバンク
108 メモリバンク
110 制御モジュール
120 シリアルデータリンクインターフェイス
122 メモリバンク
124 メモリバンク
126 制御モジュール
132 シリアルデータリンク
134 シリアルデータリンク
136 シリアルデータリンク
138 シリアルデータリンク
140 メモリバンク
142 メモリバンク
144 メモリバンク
146 メモリバンク
150 制御モジュール
200 メモリ装置
202 メモリバンクA
204 メモリバンクB
205 インターフェイス回路
206 アドレスおよびデータパススイッチ回路
207 インターフェイス回路
208 制御インターフェイス
210 ステータス/IDレジスタ回路
212 検出アンプおよびページバッファ回路ブロック
212 回路内列デコーダ
212 回路内ページレジスタ
214 行デコーダブロック
216 制御およびプレデコーダ回路ブロック
216 ページレジスタ
218 検出アンプおよびページバッファ回路ブロック
220 行デコーダブロック
222 制御およびプレデコーダ回路ブロック
224 レジスタブロック
228 コマンドインタプリタ
230 シリアルデータリンク
230 データパス制御モジュール
232 入力シリアル-パラレルレジスタブロック
234 出力パラレル-シリアルレジスタブロック
236 シリアルデータリンク
238 出力パラレル-シリアルレジスタブロック
238 制御モジュール
240 入力シリアル-パラレルレジスタブロック
242 入力バッファ
244 出力ドライバ
246 フリップフロップ回路
248 インバータ
250 マルチプレクサ(MUX)
252 AND倫理ゲート
254 入力コントローラ
256 コマンドレジスタ
258 一時レジスタ
260 シリアルデータレジスタ
262 コマンドインタプリタ
264 スイッチコントローラ
266 スイッチ回路
268 列アドレスレジスタ
270 行/バンクアドレスレジスタ
272 データレジスタ
274 スイッチサブ回路
276 スイッチサブ回路
278 入力マルチプレクサ
280 出力マルチプレクサ
282 第1のパラレル-シリアルレジスタ
284 第2のパラレル-シリアルレジスタ
286 マルチプレクサ
288 ステータスレジスタ
290 IDレジスタ
292 出力マルチプレクサ
294 ORゲート
296 シリアル出力制御回路
302 チップ選択(CS#)信号
304 シリアルクロック(SCLK)信号
306 入力ポートイネーブル(IPEx)信号
308 シリアル入力(SIPx)ポート
310 出力ポートイネーブル(OPEx)信号
312 シリアル出力ピン
314 「ページ読み取り」メモリコマンド
316 「ステータスの読み取り」メモリコマンド
318 時刻
320 「ページ読み取り」コマンド
322 出力データ
402 「ランダムデータ読み取り」コマンド
404 データ
502 「シリアルデータ入力」コマンド
504 「ページ開始」コマンド
602 コマンドデータ
604 「ステータスの読み取り」コマンド
802 「ページ読み取り」操作
804 「ページ読み取り」操作
806 出力データ
808 出力データ
810 「ページ読み取り」コマンド
812 「ページプログラム」コマンド
814 「消去」コマンド
816 「ページプログラム」コマンド
818 読み取りコマンド
1100 標準パッケージ
1202 「ページプログラム」コマンド
1204 「ステータスの読み取り」コマンド
1208 「ページ読み取り」コマンド
1210 「ステータスの読み取り」コマンド
1212 期間
1214 「ページ読み取り」コマンド
1300 デイジーチェーンカスケード構成
1300 メモリ装置
1402 「ページ読み取り」メモリコマンド
Claims (7)
- 半導体メモリ装置におけるシリアルデータリンクインターフェイスと複数のメモリバンクとの間のデータ転送を制御する方法であって、
(a)シリアルデータリンクインターフェイスでデータストリームを受信するステップと、
(b)第1のメモリバンク識別子を抽出するために、前記データストリームを構文解析するステップと、
(c)第1のメモリバンクが利用されていることを示すように、前記第1のメモリバンクに対応させて第1のメモリバンクステータスインジケータを更新するステップと、
(d)前記シリアルデータリンクインターフェイスと前記第1のメモリバンクとの間にデータを送るステップと
を含む方法。 - 前記(c)が、ステータスレジスタにおいてビット値を設定するステップをさらに含む請求項1に記載の方法。
- 前記(d)の後、前記メモリバンクステータスインジケータを、前記メモリバンクがもはや使用されていないことを示すように更新するステップをさらに含む請求項1に記載の方法。
- (e)前記シリアルリンクインターフェイスで第2のデータストリームを受信するステップと、
(f)第2のメモリバンク識別子を抽出するために、前記第2のデータストリームを構文解析するステップと、
(i)前記第2のメモリバンクが利用されていることを示すように、前記第2のメモリバンク識別子に対応させてメモリバンクステータスインジケータを更新するステップと、
(j)(d)が実行される期間と少なくとも重なる期間中、前記シリアルリンクインターフェイスと前記第2のメモリバンクとの間にデータを送るステップと
をさらに含む請求項1に記載の方法。 - (d)および(j)が別々の処理スレッドを使用して行われる請求項1に記載の方法。
- (e)第2のメモリバンクに格納されているデータの要求を前記シリアルリンクインターフェイスから受信するステップと、
(f)前記第2のメモリバンクに対応するメモリバンクステータスインジケータを、前記第2のメモリバンクが使用されていることを示すように更新するステップと、
(g)(d)が実行される期間と少なくとも重なる期間中、前記第2のメモリバンクと前記シリアルリンクインターフェイスとの間にデータを送るステップと
をさらに含む請求項1に記載の方法。 - (d)および(g)が別々の処理スレッドを使用して行われる請求項6に記載の方法。
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US72236805P | 2005-09-30 | 2005-09-30 | |
US60/722,368 | 2005-09-30 | ||
US11/324,023 | 2005-12-30 | ||
US11/324,023 US7652922B2 (en) | 2005-09-30 | 2005-12-30 | Multiple independent serial link memory |
Related Parent Applications (1)
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JP2008532550A Division JP2009510656A (ja) | 2005-09-30 | 2006-09-29 | 複数の独立したシリアルリンクメモリ |
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JP2013158682A Division JP2013251045A (ja) | 2005-09-30 | 2013-07-31 | 複数の独立したシリアルリンクメモリ |
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JP2012181916A true JP2012181916A (ja) | 2012-09-20 |
JP2012181916A5 JP2012181916A5 (ja) | 2013-02-28 |
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JP2008532550A Withdrawn JP2009510656A (ja) | 2005-09-30 | 2006-09-29 | 複数の独立したシリアルリンクメモリ |
JP2012116380A Pending JP2012181916A (ja) | 2005-09-30 | 2012-05-22 | 複数の独立したシリアルリンクメモリ |
JP2013158682A Pending JP2013251045A (ja) | 2005-09-30 | 2013-07-31 | 複数の独立したシリアルリンクメモリ |
JP2015097836A Pending JP2015164090A (ja) | 2005-09-30 | 2015-05-13 | 複数の独立したシリアルリンクメモリ |
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JP2008532550A Withdrawn JP2009510656A (ja) | 2005-09-30 | 2006-09-29 | 複数の独立したシリアルリンクメモリ |
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JP2013158682A Pending JP2013251045A (ja) | 2005-09-30 | 2013-07-31 | 複数の独立したシリアルリンクメモリ |
JP2015097836A Pending JP2015164090A (ja) | 2005-09-30 | 2015-05-13 | 複数の独立したシリアルリンクメモリ |
Country Status (10)
Country | Link |
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US (8) | US7652922B2 (ja) |
EP (3) | EP1932157B1 (ja) |
JP (4) | JP2009510656A (ja) |
KR (1) | KR101154148B1 (ja) |
CN (2) | CN103985404A (ja) |
AT (1) | ATE533158T1 (ja) |
CA (1) | CA2623747C (ja) |
HK (1) | HK1202974A1 (ja) |
TW (2) | TWI545569B (ja) |
WO (1) | WO2007036047A1 (ja) |
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