ATE520086T1 - Speicheranordnung für mehrprozessorsysteme - Google Patents

Speicheranordnung für mehrprozessorsysteme

Info

Publication number
ATE520086T1
ATE520086T1 AT06762309T AT06762309T ATE520086T1 AT E520086 T1 ATE520086 T1 AT E520086T1 AT 06762309 T AT06762309 T AT 06762309T AT 06762309 T AT06762309 T AT 06762309T AT E520086 T1 ATE520086 T1 AT E520086T1
Authority
AT
Austria
Prior art keywords
memory
queue
functional unit
queues
arrangement
Prior art date
Application number
AT06762309T
Other languages
English (en)
Inventor
Bingfeng Mei
Suk Kim
Osman Allam
Original Assignee
Imec
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imec, Samsung Electronics Co Ltd filed Critical Imec
Application granted granted Critical
Publication of ATE520086T1 publication Critical patent/ATE520086T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
AT06762309T 2005-06-30 2006-06-30 Speicheranordnung für mehrprozessorsysteme ATE520086T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69550605P 2005-06-30 2005-06-30
PCT/EP2006/006375 WO2007003370A2 (en) 2005-06-30 2006-06-30 A memory arrangement for multi-processor systems

Publications (1)

Publication Number Publication Date
ATE520086T1 true ATE520086T1 (de) 2011-08-15

Family

ID=37106271

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06762309T ATE520086T1 (de) 2005-06-30 2006-06-30 Speicheranordnung für mehrprozessorsysteme

Country Status (5)

Country Link
EP (2) EP2317446A1 (de)
JP (1) JP5117383B2 (de)
KR (1) KR100990902B1 (de)
AT (1) ATE520086T1 (de)
WO (1) WO2007003370A2 (de)

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US7747833B2 (en) 2005-09-30 2010-06-29 Mosaid Technologies Incorporated Independent link and bank selection
US20070076502A1 (en) 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
KR101260632B1 (ko) 2005-09-30 2013-05-03 모사이드 테크놀로지스 인코퍼레이티드 출력 제어 메모리
US11948629B2 (en) 2005-09-30 2024-04-02 Mosaid Technologies Incorporated Non-volatile memory device with concurrent bank operations
KR101388134B1 (ko) * 2007-10-01 2014-04-23 삼성전자주식회사 뱅크 충돌 방지 장치 및 방법
EP2110757A1 (de) 2008-04-14 2009-10-21 Imec Vorrichtung und Verfahren zur Parallelisierung von Mehrträger-Demodulation
CN101547209B (zh) * 2009-05-15 2012-01-04 杭州华三通信技术有限公司 一种信息表项的更新方法和设备
KR101553651B1 (ko) 2009-10-13 2015-09-17 삼성전자 주식회사 다중 뱅크 메모리 액세스 장치
KR101738641B1 (ko) 2010-12-17 2017-05-23 삼성전자주식회사 멀티 코어 시스템의 프로그램 컴파일 장치 및 방법
KR101862799B1 (ko) 2011-12-12 2018-05-31 삼성전자주식회사 메모리 컨트롤러 및 메모리 컨트롤 방법
WO2013100783A1 (en) 2011-12-29 2013-07-04 Intel Corporation Method and system for control signalling in a data path module
US9274964B2 (en) * 2012-02-02 2016-03-01 Qualcomm Incorporated Multi-bank cache memory
JP6115564B2 (ja) * 2012-03-13 2017-04-19 日本電気株式会社 データ処理システム、半導体集積回路およびその制御方法
US9507541B2 (en) * 2012-12-25 2016-11-29 Nec Corporation Computation device, computation method, and medium
KR20140131781A (ko) * 2013-05-06 2014-11-14 삼성전자주식회사 메모리 제어 장치 및 방법
US10331583B2 (en) 2013-09-26 2019-06-25 Intel Corporation Executing distributed memory operations using processing elements connected by distributed channels
JP6331944B2 (ja) * 2014-10-07 2018-05-30 富士通株式会社 情報処理装置、メモリ制御装置及び情報処理装置の制御方法
US11086816B2 (en) 2017-09-28 2021-08-10 Intel Corporation Processors, methods, and systems for debugging a configurable spatial accelerator
US11307873B2 (en) 2018-04-03 2022-04-19 Intel Corporation Apparatus, methods, and systems for unstructured data flow in a configurable spatial accelerator with predicate propagation and merging
US10567307B2 (en) 2018-04-27 2020-02-18 Avago Technologies International Sales Pte. Limited Traffic management for high-bandwidth switching
US10686714B2 (en) * 2018-04-27 2020-06-16 Avago Technologies International Sales Pte. Limited Traffic management for high-bandwidth switching
US10891240B2 (en) 2018-06-30 2021-01-12 Intel Corporation Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator
US11200186B2 (en) 2018-06-30 2021-12-14 Intel Corporation Apparatuses, methods, and systems for operations in a configurable spatial accelerator
US10853073B2 (en) 2018-06-30 2020-12-01 Intel Corporation Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator
KR102140374B1 (ko) * 2018-07-30 2020-07-31 숭실대학교산학협력단 블록체인 지갑 시스템의 캐시 부 채널 공격 방지 장치 및 방법, 상기 방법을 수행하기 위한 기록 매체
US10915471B2 (en) 2019-03-30 2021-02-09 Intel Corporation Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator
US11037050B2 (en) * 2019-06-29 2021-06-15 Intel Corporation Apparatuses, methods, and systems for memory interface circuit arbitration in a configurable spatial accelerator
US12086080B2 (en) 2020-09-26 2024-09-10 Intel Corporation Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits

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US5214769A (en) * 1987-12-24 1993-05-25 Fujitsu Limited Multiprocessor control system
JPH03257534A (ja) * 1990-03-07 1991-11-18 Nec Corp メモリ割り当て方式
US5293607A (en) * 1991-04-03 1994-03-08 Hewlett-Packard Company Flexible N-way memory interleaving
JPH06314264A (ja) * 1993-05-06 1994-11-08 Nec Corp セルフ・ルーティング・クロスバー・スイッチ
US6564304B1 (en) * 2000-09-01 2003-05-13 Ati Technologies Inc. Memory processing system and method for accessing memory including reordering memory requests to reduce mode switching
EP1362288B1 (de) * 2000-11-03 2006-04-05 Broadcom Corporation Vorrichtung und verfahren zum pipeline-mehrfachspeicherzugriff
US6963962B2 (en) * 2002-04-11 2005-11-08 Analog Devices, Inc. Memory system for supporting multiple parallel accesses at very high frequencies
JP4566738B2 (ja) * 2002-05-24 2010-10-20 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ コンピュータメモリ装置

Also Published As

Publication number Publication date
EP1896983B1 (de) 2011-08-10
WO2007003370A3 (en) 2007-04-05
KR20080025053A (ko) 2008-03-19
JP2008545187A (ja) 2008-12-11
JP5117383B2 (ja) 2013-01-16
EP1896983A2 (de) 2008-03-12
EP2317446A1 (de) 2011-05-04
KR100990902B1 (ko) 2010-11-01
WO2007003370A2 (en) 2007-01-11

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