EP2329496A4 - Serial-connected memory system with output delay adjustment - Google Patents

Serial-connected memory system with output delay adjustment

Info

Publication number
EP2329496A4
EP2329496A4 EP09817125A EP09817125A EP2329496A4 EP 2329496 A4 EP2329496 A4 EP 2329496A4 EP 09817125 A EP09817125 A EP 09817125A EP 09817125 A EP09817125 A EP 09817125A EP 2329496 A4 EP2329496 A4 EP 2329496A4
Authority
EP
European Patent Office
Prior art keywords
serial
memory system
delay adjustment
output delay
connected memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09817125A
Other languages
German (de)
French (fr)
Other versions
EP2329496A1 (en
Inventor
Hakjune Oh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Novachips Canada Inc
Original Assignee
Conversant Intellectual Property Management Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US12/241,832 priority Critical patent/US8181056B2/en
Priority to US12/241,960 priority patent/US8161313B2/en
Application filed by Conversant Intellectual Property Management Inc filed Critical Conversant Intellectual Property Management Inc
Priority to PCT/CA2009/001271 priority patent/WO2010037205A1/en
Publication of EP2329496A1 publication Critical patent/EP2329496A1/en
Publication of EP2329496A4 publication Critical patent/EP2329496A4/en
Application status is Withdrawn legal-status Critical

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/32Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066Output synchronization
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069I/O lines read out arrangements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222Clock generating, synchronizing or distributing circuits within memory device
EP09817125A 2008-09-30 2009-09-17 Serial-connected memory system with output delay adjustment Withdrawn EP2329496A4 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/241,832 US8181056B2 (en) 2008-09-30 2008-09-30 Serial-connected memory system with output delay adjustment
US12/241,960 US8161313B2 (en) 2008-09-30 2008-09-30 Serial-connected memory system with duty cycle correction
PCT/CA2009/001271 WO2010037205A1 (en) 2008-09-30 2009-09-17 Serial-connected memory system with output delay adjustment

Publications (2)

Publication Number Publication Date
EP2329496A1 EP2329496A1 (en) 2011-06-08
EP2329496A4 true EP2329496A4 (en) 2012-06-13

Family

ID=42072981

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09817125A Withdrawn EP2329496A4 (en) 2008-09-30 2009-09-17 Serial-connected memory system with output delay adjustment

Country Status (6)

Country Link
EP (1) EP2329496A4 (en)
JP (2) JP2012504263A (en)
KR (1) KR20110081958A (en)
CN (1) CN102165529B (en)
TW (1) TW201027556A (en)
WO (1) WO2010037205A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8665665B2 (en) * 2011-03-30 2014-03-04 Mediatek Inc. Apparatus and method to adjust clock duty cycle of memory
US9257164B2 (en) * 2013-03-14 2016-02-09 Altera Corporation Circuits and methods for DQS autogating
JP6232313B2 (en) * 2014-02-25 2017-11-15 新日本無線株式会社 Synchronous serial communication method and a slave device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6950956B2 (en) * 1999-10-19 2005-09-27 Rambus Inc. Integrated circuit with timing adjustment mechanism and method
US20060136618A1 (en) * 2004-07-30 2006-06-22 International Business Machines Corporation System, method and storage medium for a multi-mode memory buffer device
WO2007106766A2 (en) * 2006-03-16 2007-09-20 Rambus Inc. Signaling system with adaptive timing calibration
US20080028123A1 (en) * 2006-07-26 2008-01-31 Gerald Keith Bartley Computer System Having Daisy Chained Memory Chips

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000148674A (en) * 1998-11-09 2000-05-30 Sharp Corp Method for transmitting serial data
US6839393B1 (en) * 1999-07-14 2005-01-04 Rambus Inc. Apparatus and method for controlling a master/slave system via master device synchronization
JP2003140962A (en) * 2001-10-30 2003-05-16 Mitsubishi Electric Corp Signal transmit/receive system
JP3843002B2 (en) * 2001-11-26 2006-11-08 株式会社ルネサステクノロジ Variable delay circuits and systems lsi using the variable delay circuit
US7308524B2 (en) 2003-01-13 2007-12-11 Silicon Pipe, Inc Memory chain
US7307461B2 (en) * 2003-09-12 2007-12-11 Rambus Inc. System and method for adaptive duty cycle optimization
US7533218B2 (en) * 2003-11-17 2009-05-12 Sun Microsystems, Inc. Memory system topology
US6980042B2 (en) * 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
US7747833B2 (en) 2005-09-30 2010-06-29 Mosaid Technologies Incorporated Independent link and bank selection
US7352219B2 (en) * 2005-08-30 2008-04-01 Infineon Technologies Ag Duty cycle corrector
US7652922B2 (en) 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
TWI446356B (en) 2005-09-30 2014-07-21 Mosaid Technologies Inc Memory with output control and system thereof
US20070076502A1 (en) 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
US8069328B2 (en) 2006-03-28 2011-11-29 Mosaid Technologies Incorporated Daisy chain cascade configuration recognition technique
CN101506895B (en) * 2006-08-22 2012-06-27 莫塞德技术公司 Scalable memory system
JP4952177B2 (en) * 2006-10-02 2012-06-13 富士通株式会社 Storage device
US8140803B2 (en) * 2007-01-09 2012-03-20 International Business Machines Corporation Structure for reducing latency associated with read operations in a memory system
CN101617371B (en) * 2007-02-16 2014-03-26 莫塞德技术公司 Non-volatile semiconductor memory having multiple external power supplies

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6950956B2 (en) * 1999-10-19 2005-09-27 Rambus Inc. Integrated circuit with timing adjustment mechanism and method
US20060136618A1 (en) * 2004-07-30 2006-06-22 International Business Machines Corporation System, method and storage medium for a multi-mode memory buffer device
WO2007106766A2 (en) * 2006-03-16 2007-09-20 Rambus Inc. Signaling system with adaptive timing calibration
US20080028123A1 (en) * 2006-07-26 2008-01-31 Gerald Keith Bartley Computer System Having Daisy Chained Memory Chips

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2010037205A1 *

Also Published As

Publication number Publication date
KR20110081958A (en) 2011-07-15
WO2010037205A1 (en) 2010-04-08
TW201027556A (en) 2010-07-16
CN102165529B (en) 2014-12-31
CN102165529A (en) 2011-08-24
JP2012504263A (en) 2012-02-16
JP5599852B2 (en) 2014-10-01
JP2013008386A (en) 2013-01-10
EP2329496A1 (en) 2011-06-08

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RIC1 Classification (correction)

Ipc: G11C 16/32 20060101ALI20120510BHEP

Ipc: G06F 13/42 20060101ALI20120510BHEP

Ipc: G11C 7/22 20060101AFI20120510BHEP

17Q First examination report

Effective date: 20130917

RAP1 Transfer of rights of an ep published application

Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.

RAP1 Transfer of rights of an ep published application

Owner name: NOVACHIPS CANADA INC.

18D Deemed to be withdrawn

Effective date: 20150512