TWI436433B - 形成高鍺濃度的矽鍺應力源的方法及積體電路電晶體結構 - Google Patents

形成高鍺濃度的矽鍺應力源的方法及積體電路電晶體結構 Download PDF

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TWI436433B
TWI436433B TW099124883A TW99124883A TWI436433B TW I436433 B TWI436433 B TW I436433B TW 099124883 A TW099124883 A TW 099124883A TW 99124883 A TW99124883 A TW 99124883A TW I436433 B TWI436433 B TW I436433B
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germanium
source
ruthenium
drain
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TW201118959A (en
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Chih Hao Chang
Jeff J Xu
Chien Hsun Wang
Chih Chieh Yeh
Chih Hsiang Chang
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Taiwan Semiconductor Mfg
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Description

形成高鍺濃度的矽鍺應力源的方法及積體電路電晶體結構
本發明關於積體電路，特別是關於半導體電晶體結構中的矽鍺源極汲極應力源(SiGe source-drain stressor)。
應變工程(Strain engineering)被應用在半導體製程中以提昇元件的性能。藉由調整電晶體通道中的應變可提昇電子或電洞的遷移率從而提昇通道(channel)的導電率。
在互補式金氧半導體技術(CMOS technology)中，P通道金氧半導體(P-channel Metal-Oxide Semiconductor，PMOS)與N通道金氧半導體(N-channel Metal-Oxide Semiconductor，NMOS)對於不同種類的應變會有不同的反應。具體而言，藉由對通道施加壓縮應變可使PMOS的性能最佳化，反之，拉伸應變有利於NMOS。一般是用由任一莫耳比的矽與鍺所構成的矽鍺(Si1-x Gex )作為CMOS電晶體中的應變矽的一應變誘導層(strain-inducing layer)。
應變矽為一矽層，且該矽層中的矽原子被拉伸而超過其正常的原子間距(inter atomic distance)。舉例來說，可藉由將該矽層放置在一矽鍺基板上來達成。因為矽層中的原子會與其下方的矽鍺層的原子對齊，而矽鍺層的原子間距大於塊狀矽結體中的原子間距，因此，矽原子之間的連結變長從而導致應變矽。
目前，PMOS應變可藉由底切(undercut)源極/汲極區以及在底切區中磊晶成長矽鍺膜的方式來實現。矽鍺膜之較大晶格常數提供矽通道單軸應變。鍺的濃度愈高，則應變愈大，從而有較佳的性能。然而，併入矽鍺膜中的鍺受限於磊晶製程。利用習知的磊晶方法難以製作鍺濃度非常高的矽鍺膜，習知的磊晶方法對於表面預處理(surface preparation)、所使用的前驅物以及成長環境非常敏感。要去符合持續增加的鍺濃度需求以及隨著磊晶成長要保持適當地控制矽鍺的輪廓以作為PMOS中的矽鍺源極/汲極(S/D)是有挑戰性的。
本發明提出一種形成矽鍺應力源的方法如下所述。沈積一第一矽鍺層於一半導體基板上的一源極區與一汲極區之至少其中之一中，半導體基板具有位於源極區與汲極區之間的一通道。使第一矽鍺層的一頂部轉變成一氧化層以及使第一矽鍺層的一底部轉變成一第二矽鍺層，其中第二矽鍺層的鍺濃度高於第一矽鍺層的鍺濃度。
本發明提出一種形成矽鍺應力源的方法如下所述。沈積一第一矽鍺層於一半導體基板上的一源極區與一汲極區之至少其中之一中，半導體基板具有位於源極區與汲極區之間的一通道。於第一矽鍺層上沈積一矽蓋層。進行一熱氧化以使第一矽鍺層的一頂部轉變成一氧化層以及使第一矽鍺層的一底部轉變成一第二矽鍺層，其中第二矽鍺層的鍺百分比高於第一矽鍺層的鍺百分比。
本發明提出一種積體電路電晶體結構包括一半導體基板、一第一矽鍺層以及一通道。第一矽鍺層位於半導體基板上的一源極區與一汲極區之至少其中之一中，其中第一矽鍺層的鍺濃度為大於或等於50%。通道位於源極區與汲極區之間。
為使本發明之上述目的、特徵和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下。
以下將詳細討論目前幾個較佳的實施例的製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以在多種特定的情況下實施。文中所討論的特定實施例僅用以說明以特定的方式去製作與使用本發明，非用以限制本發明之範圍。
此處，提供一具有高鍺濃度的矽鍺應力源的製作方法。該方法使一具有低鍺濃度的矽鍺膜轉變成一具有高鍺濃度的矽鍺膜，而毋須磊晶形成一高鍺濃度的源極/汲極。藉由擁有分開的氧化步驟與擴散步驟作為濃縮製程(condensation process)，可形成以及適當地控制高鍺濃度的矽鍺輪廓。此方法可應用至位於塊狀矽或是絕緣層上覆矽(silicon on insulator，SOI)上的平面型及鰭式場效電晶體元件。在本發明之各種圖式與介紹的實施例中，相同的元件符號係用以標示相同的元件。
第1A圖-第1C圖繪示本發明一實施例之具有高鍺濃度的矽鍺應力源的一示範製程。在第1A圖中，一矽鍺膜層106與一矽蓋層108沈積於矽基板102(基板102亦可為矽鍺基板或是在矽基板上的鬆弛矽鍺膜)上，並位於源極/汲極區中的間隔層116的旁邊。閘極118下方的通道區104可包括矽或矽鍺通道。矽蓋層108可作為氧化的起點。一般而言，若是沒有矽蓋層108，則矽鍺膜的氧化品質可能偏低且可能難以控制氧化前線(oxidation front)。起初具有矽蓋層108可有助於形成一均勻的氧化層112(如第1B圖所示)，並使整個濃縮輪廓更容易控制。
在第1B圖中，進行低溫熱氧化(乾式或濕式，較佳是濕式以降低溫度)以於底部界面形成一局部的高鍺百分比(濃度)的矽鍺膜層110，而且，在此步驟中，極少或是完全沒有鍺擴散穿過矽鍺/矽界面而進入基板102中。矽鍺膜層106的頂部與矽蓋層108轉變為氧化層112，而矽鍺膜層106的底部轉變為高鍺百分比的矽鍺膜層110。此熱氧化步驟亦可包括至少二階段，各階段具有不同的溫度與持續時間，以確保極少或是沒有鍺在此步驟的製程中擴散。舉例來說，第一階段可為一小時750℃的熱氧化，第二階段可為二小時600℃的熱氧化。一般來說，500℃-850℃的熱氧化製程可用來作為低溫熱氧化。
在第1C圖中，進行熱擴散以形成具有所需輪廓與深度的矽鍺應力源114。之後，移除頂氧化層112並繼續進行一般的製程。假如可以確定一最佳溫度以同時達到氧化與所需的擴散輪廓，則可結合該氧化與熱擴散步驟並同時進行。
矽鍺膜層106具有一矽鍺組成比率(Si：Ge=1-x：x，即Si1-x Gex )，而濃縮的矽鍺應力源膜114具有一矽鍺組成比率(Si：Ge=1-y：y，即Si1-y Gey )。其中x與y代表在各矽鍺膜中鍺的百分比(y>x)。矽鍺應力源層114具有比沈積的矽鍺膜層106高的鍺濃度，並提供通道104單軸的壓縮應變。
藉由分別的(低溫)氧化步驟與鍺擴散步驟作為濃縮製程，可從原本具有低鍺濃度百分比的沈積矽鍺膜106在矽鍺源極/汲極應力源膜114中形成鍺濃度較高的輪廓並可適當地控制。不會引起鍺擴散的低溫熱氧化(例如低於800℃時x<0.5以及低於600℃時x接近1，其中x是Si1-x Gex 中的數字)可得到一局部的非擴散高鍺百分比之矽鍺膜110。舉例來說，這可以透過高水蒸汽壓的濕式氧化來達成。
該氧化與擴散之二步驟製程消除了習知濃縮製程中對於絕緣層上覆矽基板的需求，習知濃縮製程是依靠氧化物來阻擋不受控制的鍺擴散。本發明所揭露的實施例亦可應用在三維(three-dimensional，3D)的結構。濃縮的高鍺濃度矽鍺應力源區114自然地接近表面通道104，以致於在元件通道上產生有效的應變。再者，若是沒有來自於源極/汲極所助長的應力(例如使用本發明所揭露的實施例)，則高鍺百分比的矽鍺通道(例如Si0.5 Ge0.5 )元件上之運作本身的表現是無法與傳統的單軸應變的矽元件媲美的。
第2A圖-第2F圖繪示本發明一實施例之一具有應變的源極汲極(SSD)的平面元件的製程。在第2A圖中，製程是始於具有應變的源極汲極以及矽鍺磊晶層(SiGe epi layer)202。基板102、通道104、介電層204、閘極206以及間隙壁(sidewall spacer)208亦表示於第2A圖中。在第2B圖中，一矽鍺膜106(其鍺濃度可以是高於或是低於矽鍺磊晶層202的鍺濃度)沈積於矽鍺磊晶層202的頂部上。一矽蓋層108可視需要而沈積於矽鍺膜106的頂部上以利於均勻地氧化(如第2C圖所示)。在經過第2D圖的低溫氧化之後，形成高鍺百分比的矽鍺膜110與氧化層112。在第2E圖中，進行熱擴散以形成一濃縮的高鍺濃度矽鍺應力源膜114。矽鍺膜114的鍺濃度高於原本的矽鍺磊晶層202的鍺濃度。在第2F圖中，可移除氧化層112。
第3A圖-第3F圖繪示本發明另一實施例之一無應變的源極汲極(SSD)的平面元件的製程。在第3A圖中，製程是在不具有應變的源極汲極的情況下開始的。基板102、通道層104、介電層204、閘極206以及間隙壁208表示於第3A圖中。在第3B圖中，一矽鍺膜106沈積在通道層104的頂部上。一矽蓋層108可視需要而沈積在矽鍺膜106的頂部上以利於均勻地氧化(如第3C圖所示)。在經過圖3D的低溫氧化之後，形成高鍺百分比的矽鍺膜110以及氧化層112。在第3E圖中，進行熱擴散以形成一濃縮的高鍺濃度矽鍺應力源114。在第3F圖中，可移除氧化層112。
第4A圖-第4F圖繪示本發明一實施例之具有應變的源極汲極的鰭式場效電晶體(Fin Field-effect transistor，FinFET)元件的製程。第4A圖繪示基板102上的矽源極/汲極鰭狀區402以及淺溝槽隔離區(shallow trench isolation)406之沿著一閘極方向的剖面圖。在第4B圖中，在矽基板102的頂部上的矽源極/汲極鰭狀區402上進行非等向性(anisotropic)之具有應變的源極汲極蝕刻以及矽鍺磊晶成長製程，以形成矽鍺膜層106。在第4C圖中，一矽蓋層108可視需要而沈積在矽鍺膜106的頂部上以利於均勻地氧化。在經過第4D圖的低溫氧化之後，高鍺百分比的矽鍺膜110以及氧化層112形成在鰭狀區404上。在第4E圖中，進行熱擴散以形成一濃縮的高鍺濃度矽鍺應力源114。矽鍺應力源114的鍺濃度高於矽鍺膜106的鍺濃度。也有可能的是，整個源極/汲極區404都均勻地轉變成較高鍺濃度的矽鍺(例如404=114)。在第4F圖中，可移除氧化層112。
第5A圖-第5F圖繪示本發明另一實施例之無應變的源極汲極的鰭式場效電晶體元件的製程。第5A圖繪示基板102上的矽源極/汲極鰭狀區402以及淺溝槽隔離區406之沿著一閘極方向的剖面圖。在第5B圖中，一矽鍺膜層106成長在矽源極/汲極鰭狀區402上，且矽源極/汲極鰭狀區402位於矽基板102的頂部上。在第5C圖中，一矽蓋層108可視需要而沈積在矽鍺膜106的頂部上以利於均勻地氧化。在經過第5D圖的低溫氧化之後，高鍺百分比的矽鍺膜110以及氧化層112形成於鰭狀區402上。在第5E圖中，進行熱擴散以形成一濃縮的高鍺濃度矽鍺應力源114。矽鍺應力源114的鍺濃度高於矽鍺膜106的鍺濃度。再者，有可能的是，整個矽源極/汲極鰭狀區402都均勻地轉變成鍺濃度較高的矽鍺。在第5F圖中，可移除氧化層112。
本發明所揭露的實施例的優點特徵包括達成使更高的單軸壓應力施加於通道上而毋須再進行一次矽鍺製程，故可減輕以磊晶的方式形成鍺濃度越來越高的矽鍺膜的壓力，並除去臨界厚度(critical thickness)的限制，即具有應變的源極汲極的深度。再者，本方法可由鍺濃度較高的矽鍺源極/汲極提供一單軸應變於矽鍺通道上，此外，可由矽鍺通道提供雙軸應變於矽基板上(例如具有矽鍺源極/汲極的Si0.5 Ge0.5 通道，其鍺含量大於50%)。
在一些實施例中，形成具有高鍺濃度的矽鍺應力源的方法包括提供一半導體基板，該半導體基板具有一源極區、一汲極區以及位於該源極區與該汲極區之間的一通道；沈積矽鍺膜層於該源極區及/或該汲極區上；進行低溫熱氧化以形成一氧化層於該沈積的矽鍺膜層的頂部並將該沈積的矽鍺膜層的底部轉換成一高鍺百分比的矽鍺膜且無鍺擴散入矽基板；進行熱擴散以從該轉換的高鍺百分比矽鍺膜層形成矽鍺應力源，其中該矽鍺應力源於通道上提供單軸壓應變；以及移除該氧化層。
該方法可更包括在進行低溫熱氧化之前於該矽鍺膜層上沈積一額外的矽蓋層。可利用一高水蒸氣壓的濕式氧化製程進行低溫熱氧化，在此僅用以舉例說明並非用以限定。低溫熱氧化可具有至少二階段，該二階段具有不同的溫度與持續時間。低溫熱氧化與熱擴散可為二個分開的步驟或者是可同時進行。一額外的矽鍺膜層可以傳統的磊晶法或是前述的濃縮法沈積在矽鍺源極區及/或汲極區上。該沈積的矽鍺膜的鍺濃度可高於或低於矽鍺源極/汲極的鍺濃度。在經過本發明的製程之後，矽鍺源極/汲極區中的鍺濃度將高於其之前的鍺濃度。
在一些實施例中，通道可包括矽鍺。矽基板可於矽鍺通道上提供雙軸應變。利用本發明所述的方法，矽鍺應力源的鍺濃度可高於通道的鍺濃度，以由應力源提供一額外的單軸應變。舉例來說，通道可包括Si0.5 Ge0.5 及/或矽鍺應力源可具有大於50%的鍺。
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102．．．基板、矽基板
104．．．通道、通道區、通道層
106．．．矽鍺膜、矽鍺膜層
108．．．矽蓋層
110．．．矽鍺膜、矽鍺膜層
112．．．氧化層、頂氧化層
114．．．矽鍺膜、矽鍺應力源、矽鍺應力源膜、矽鍺應力源層、矽鍺應力源區
116．．．間隔層
118．．．閘極
202．．．矽鍺磊晶層
204‧‧‧介電層
206‧‧‧閘極
208‧‧‧間隙壁
402‧‧‧鰭狀區、矽源極/汲極鰭狀區
404‧‧‧鰭狀區、源極/汲極區
406‧‧‧淺溝槽隔離區
第1A圖-第1C圖繪示本發明一實施例之具有高鍺濃度的矽鍺應力源的一示範製程。
第2A圖-第2F圖繪示本發明一實施例之一具有應變的源極汲極(SSD)的平面元件的製程。
第3A圖-第3F圖繪示本發明另一實施例之一無應變的源極汲極的平面元件的製程。
第4A圖-第4F圖繪示本發明一實施例之具有應變的源極汲極的鰭式場效電晶體(Fin Field-effect transistor，FinFET)或三閘極元件的製程。
第5A圖-第5F圖繪示本發明另一實施例之無應變的源極汲極的鰭式場效電晶體或三閘極元件的製程。
102．．．基板、矽基板
104．．．通道、通道區、通道層
112．．．氧化層、頂氧化層
114．．．矽鍺膜、矽鍺應力源、矽鍺應力源膜、矽鍺應力源層、矽鍺應力源區
116．．．間隔層
118．．．閘極

Claims (5)

  1. 一種形成矽鍺應力源的方法，包括：沈積一第一矽鍺層於一半導體基板上的一源極區及/或一汲極區中，該半導體基板具有位於該源極區與該汲極區之間的一通道；進行一熱氧化製程以使該第一矽鍺層的一頂部轉變成一氧化層並使該第一矽鍺層的一底部轉變成一第二矽鍺層，其中該第二矽鍺層的鍺濃度高於該第一矽鍺層的鍺濃度；以及在該熱氧化製程之後，進行一熱擴散製程以由該第二矽鍺層形成一矽鍺應力源。
  2. 如申請專利範圍第1項所述之形成矽鍺應力源的方法，更包括：在使該第一矽鍺層的該頂部轉變成該氧化層並使該第一矽鍺層的該底部轉變成該第二矽鍺層之前，於該第一矽鍺層上沈積一矽蓋層。
  3. 如申請專利範圍第1項所述之形成矽鍺應力源的方法，其中該熱氧化包括至少二階段，各階段使用不同的溫度與持續時間。
  4. 如申請專利範圍第1項所述之形成矽鍺應力源的方法，其中該熱氧化的製程溫度約為600℃-800℃。
  5. 一種形成矽鍺應力源的方法，包括：沈積一第一矽鍺層於一半導體基板上的一源極區及/或一汲極區中，該半導體基板具有位於該源極區與該汲極區之間的一通道； 於該第一矽鍺層上沈積一矽蓋層；進行一熱氧化以使該第一矽鍺層的一頂部以及該矽蓋層轉變成一氧化層以及使該第一矽鍺層的一底部轉變成一第二矽鍺層，其中該第二矽鍺層的鍺百分比高於該第一矽鍺層的鍺百分比；以及在該熱氧化製程之後，進行一熱擴散製程以由該第二矽鍺層形成一矽鍺應力源。
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