JP4413580B2 - 素子形成用基板の製造方法 - Google Patents
素子形成用基板の製造方法 Download PDFInfo
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- JP4413580B2 JP4413580B2 JP2003374571A JP2003374571A JP4413580B2 JP 4413580 B2 JP4413580 B2 JP 4413580B2 JP 2003374571 A JP2003374571 A JP 2003374571A JP 2003374571 A JP2003374571 A JP 2003374571A JP 4413580 B2 JP4413580 B2 JP 4413580B2
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- 239000000758 substrate Substances 0.000 title claims description 21
- 238000000034 method Methods 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000010409 thin film Substances 0.000 claims description 39
- 239000010408 film Substances 0.000 claims description 34
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 33
- 239000013078 crystal Substances 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 14
- 238000007254 oxidation reaction Methods 0.000 claims description 14
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000002844 melting Methods 0.000 claims description 8
- 230000008018 melting Effects 0.000 claims description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000009089 cytolysis Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Description
T.Tezuka, N.Sugiyama, S.Takahi, Appl.Phys.Lett. 79,p1798(2001)
11…Si基板
12…絶縁膜
13…Si薄膜層
14…単結晶歪みGe薄膜層
15…SiGe層
16…Si酸化膜
21…ゲート絶縁膜
22…ゲート電極
23…ソース領域
24…ドレイン領域
Claims (1)
- 絶縁膜上の単結晶Si層上にGe組成が60%以下の単結晶SiGe層を形成する工程と、
前記Si層及びSiGe層を前記SiGe層の融点以下の温度に加熱して酸化し、且つ酸化時の加熱温度を最初は1000℃以上の温度に設定し、徐々に温度を下げながら、最終的に850℃以下の温度に設定することにより、該Si層及びSiGe層に対し前記絶縁膜と反対側にSi酸化膜を形成すると共に、前記絶縁膜側に厚さが2nm以上で3nm以下の圧縮歪みを有する単結晶Ge薄膜層を形成する工程と、
を含むことを特徴とする素子形成用基板の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003374571A JP4413580B2 (ja) | 2003-11-04 | 2003-11-04 | 素子形成用基板の製造方法 |
US10/979,885 US20050098234A1 (en) | 2003-11-04 | 2004-11-03 | Element fabrication substrate |
US11/510,745 US7557018B2 (en) | 2003-11-04 | 2006-08-28 | Element fabrication substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003374571A JP4413580B2 (ja) | 2003-11-04 | 2003-11-04 | 素子形成用基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005142217A JP2005142217A (ja) | 2005-06-02 |
JP4413580B2 true JP4413580B2 (ja) | 2010-02-10 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2003374571A Expired - Lifetime JP4413580B2 (ja) | 2003-11-04 | 2003-11-04 | 素子形成用基板の製造方法 |
Country Status (2)
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US (2) | US20050098234A1 (ja) |
JP (1) | JP4413580B2 (ja) |
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FR2868202B1 (fr) * | 2004-03-25 | 2006-05-26 | Commissariat Energie Atomique | Procede de preparation d'une couche de dioxyde de silicium par oxydation a haute temperature sur un substrat presentant au moins en surface du germanium ou un alliage sicicium- germanium. |
JP4157496B2 (ja) | 2004-06-08 | 2008-10-01 | 株式会社東芝 | 半導体装置及びその製造方法 |
TWI463526B (zh) * | 2004-06-24 | 2014-12-01 | Ibm | 改良具應力矽之cmos元件的方法及以該方法製備而成的元件 |
KR101131418B1 (ko) * | 2004-12-07 | 2012-04-03 | 주성엔지니어링(주) | 반도체 소자 및 이의 제조 방법 |
US7655511B2 (en) | 2005-11-03 | 2010-02-02 | International Business Machines Corporation | Gate electrode stress control for finFET performance enhancement |
US7635620B2 (en) | 2006-01-10 | 2009-12-22 | International Business Machines Corporation | Semiconductor device structure having enhanced performance FET device |
US20070158743A1 (en) * | 2006-01-11 | 2007-07-12 | International Business Machines Corporation | Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners |
JP2007194336A (ja) * | 2006-01-18 | 2007-08-02 | Sumco Corp | 半導体ウェーハの製造方法 |
FR2898215B1 (fr) * | 2006-03-01 | 2008-05-16 | Commissariat Energie Atomique | Procede de fabrication d'un substrat par condensation germanium |
JP2007319988A (ja) * | 2006-06-01 | 2007-12-13 | National Institute For Materials Science | Iv族半導体ナノ細線の製造方法並びに構造制御方法 |
DE602007000665D1 (de) * | 2006-06-12 | 2009-04-23 | St Microelectronics Sa | Verfahren zur Herstellung von auf Si1-yGey basierenden Zonen mit unterschiedlichen Ge-Gehalten auf ein und demselben Substrat mittels Kondensation von Germanium |
FR2902234B1 (fr) * | 2006-06-12 | 2008-10-10 | Commissariat Energie Atomique | PROCEDE DE REALISATION DE ZONES A BASE DE Si1-yGey DE DIFFERENTES TENEURS EN Ge SUR UN MEME SUBSTRAT PAR CONDENSATION DE GERMANIUM |
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FR2913527B1 (fr) * | 2007-03-05 | 2009-05-22 | Commissariat Energie Atomique | Procede de fabrication d'un substrat mixte et utilisation du substrat pour la realisation de circuits cmos |
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FR2925979A1 (fr) * | 2007-12-27 | 2009-07-03 | Commissariat Energie Atomique | PROCEDE DE FABRICATION D'UN SUBSTRAT SEMICONDUCTEUR SUR ISOLANT COMPRENANT UNE ETAPE D'ENRICHISSEMENT EN Ge LOCALISE |
DE102009010883B4 (de) * | 2009-02-27 | 2011-05-26 | Amd Fab 36 Limited Liability Company & Co. Kg | Einstellen eines nicht-Siliziumanteils in einer Halbleiterlegierung während der FET-Transistorherstellung mittels eines Zwischenoxidationsprozesses |
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US6607948B1 (en) * | 1998-12-24 | 2003-08-19 | Kabushiki Kaisha Toshiba | Method of manufacturing a substrate using an SiGe layer |
JP3712599B2 (ja) | 2000-08-25 | 2005-11-02 | 株式会社東芝 | 半導体装置及び半導体基板 |
JP3998408B2 (ja) * | 2000-09-29 | 2007-10-24 | 株式会社東芝 | 半導体装置及びその製造方法 |
KR100495023B1 (ko) * | 2000-12-28 | 2005-06-14 | 가부시끼가이샤 도시바 | 반도체 장치 및 그 제조 방법 |
JP3647777B2 (ja) * | 2001-07-06 | 2005-05-18 | 株式会社東芝 | 電界効果トランジスタの製造方法及び集積回路素子 |
WO2003015142A2 (en) * | 2001-08-06 | 2003-02-20 | Massachusetts Institute Of Technology | Formation of planar strained layers |
WO2004068556A2 (en) * | 2003-01-27 | 2004-08-12 | Amberwave Systems Corporation | Semiconductor structures with structural homogeneity |
US7169226B2 (en) * | 2003-07-01 | 2007-01-30 | International Business Machines Corporation | Defect reduction by oxidation of silicon |
US7084460B2 (en) * | 2003-11-03 | 2006-08-01 | International Business Machines Corporation | Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates |
FR2868202B1 (fr) * | 2004-03-25 | 2006-05-26 | Commissariat Energie Atomique | Procede de preparation d'une couche de dioxyde de silicium par oxydation a haute temperature sur un substrat presentant au moins en surface du germanium ou un alliage sicicium- germanium. |
JP4427489B2 (ja) * | 2005-06-13 | 2010-03-10 | 株式会社東芝 | 半導体装置の製造方法 |
FR2893446B1 (fr) * | 2005-11-16 | 2008-02-15 | Soitec Silicon Insulator Techn | TRAITEMENT DE COUCHE DE SiGe POUR GRAVURE SELECTIVE |
FR2898215B1 (fr) * | 2006-03-01 | 2008-05-16 | Commissariat Energie Atomique | Procede de fabrication d'un substrat par condensation germanium |
-
2003
- 2003-11-04 JP JP2003374571A patent/JP4413580B2/ja not_active Expired - Lifetime
-
2004
- 2004-11-03 US US10/979,885 patent/US20050098234A1/en not_active Abandoned
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2006
- 2006-08-28 US US11/510,745 patent/US7557018B2/en active Active
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US7557018B2 (en) | 2009-07-07 |
US20060292835A1 (en) | 2006-12-28 |
US20050098234A1 (en) | 2005-05-12 |
JP2005142217A (ja) | 2005-06-02 |
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