JP2006501672A - 改善されたキャリア移動度を有するフィンfetとその形成方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 87
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 81
- 239000010703 silicon Substances 0.000 claims abstract description 80
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 69
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims description 60
- 239000004065 semiconductor Substances 0.000 claims description 31
- 239000001257 hydrogen Substances 0.000 claims description 11
- 229910052739 hydrogen Inorganic materials 0.000 claims description 11
- 125000004435 hydrogen atom Chemical group [H]* 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 8
- 238000000137 annealing Methods 0.000 claims description 7
- 239000002019 doping agent Substances 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- OQNXPQOQCWVVHP-UHFFFAOYSA-N [Si].O=[Ge] Chemical compound [Si].O=[Ge] OQNXPQOQCWVVHP-UHFFFAOYSA-N 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- 125000006850 spacer group Chemical group 0.000 claims description 2
- 239000013078 crystal Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 59
- 230000008569 process Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 238000009499 grossing Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- QUZPNFFHZPRKJD-UHFFFAOYSA-N germane Chemical compound [GeH4] QUZPNFFHZPRKJD-UHFFFAOYSA-N 0.000 description 1
- 229910052986 germanium hydride Inorganic materials 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
図3に本発明の一実施形態に従って形成されたフィンFETのゲート及びチャネル領域の断面図が示される。図3に見られるようにこの構造は、歪みシリコン34のエピタキシャル層が上に成長するシリコンゲルマニウムチャネル領域32を含む。比較的幅の広い格子のゲルマニウム原子が存在する結果として、シリコンゲルマニウムチャネル領域32のシリコンゲルマニウム格子に、概して真性シリコン格子よりも比較的幅広い間隙が開けられる。シリコン原子の格子が比較的幅広い間隙のシリコンゲルマニウムの格子に合わせられるので、引張歪みがシリコン層に形成される。このシリコン原子は、必然的に互いが引っ張られる。シリコン格子に実行された引張歪み量は、シリコンゲルマニウム格子のゲルマニウムの比率に応じて増大する。結果として、シリコンゲルマニウムチャネル領域32に成長したエピタキシャルシリコン層34が、引張歪みを受ける。シリコン格子への引張歪みの実行は、この6価電子帯のうち4価電子帯のエネルギーの増大を生じさせ、2価電子帯のエネルギーの減少を生じさせる。量子効果の結果として、電子が歪みシリコンの比較的低エネルギー帯を通過するとき、実効的には30%少ない重量になる。加えて、電子が衝突するシリコン原子の核からの振動エネルギーが小さくなるので、リラックスシリコンにおける場合より、散乱が500〜1000分の1となる。結果として、キャリア移動度が、リラックスシリコンと比較して歪みシリコンにおいて劇的に増大するので、電子移動度においては80%又はそれ以上、正孔移動度において20%かそれ以上の増大が可能となる。移動度におけるこの増大は、界磁電流150万ボルト/cmまで持続することが見出されている。これらのファクターが、デバイスサイズを更に減少することなく、デバイス速度35%の増大を可能にし、あるいはパフォーマンスを軽減することなく電力消費を25%削減すると考えられる。
Claims (10)
- 誘電層(40)を含む基板を有し、
前記誘電層(40)上に形成されたフィンFET体(46)を有し、前記フィンFET体(46)は、ソース領域、ドレイン領域、及びこれらソース領域とドレイン領域の間に延びるチャネル領域とを有し、
前記フィンFET体の少なくとも前記チャネル領域の表面部に形成された歪みシリコン層(34)を有し、
前記チャネル領域の表面部に形成された前記歪みシリコン層(34)を覆うように少なくとも前記チャネル領域上に形成されたゲート絶縁膜(36)を有し、かつ、
前記チャネル領域のサイドウォールと上部を囲み、前記ゲート絶縁膜と前記歪みシリコン層によって前記チャネル領域から分離される導電ゲート(48)を含む、
シリコンオンインシュレータ(SOI)MOSFETデバイス。 - 前記フィンFET体(46)は、シリコンゲルマニウムである、
請求項1記載のデバイス。 - 前記フィンFET体(46)は、第1フィンFET体を含み、
前記デバイスは、更に、
前記誘電層に形成された第2フィンFET体を含み、第2フィンFET体は、第2ソース領域と第2ドレイン領域を含み、第2ソース領域と第2ドレイン領域の間に延びるチャネル領域を有し、
前記第2チャネル領域の表面部に形成された歪みシリコン層を含み、
前記第2チャネル領域の表面部に形成された前記歪みシリコンを覆うために少なくとも前記第2チャネル領域上に形成されたゲート絶縁膜を含み、且つ、
前記第2チャネル領域のサイドウォールと表面上部を囲み、前記ゲート絶縁膜と前記歪みシリコン層によって前記第2チャネル領域から分離され、前記第1フィンFET体の前記チャネル領域を囲む前記導電ゲートに電気的に接続される第2導電ゲート、
前記第1フィンFET体の前記ソースとドレインとは第1ドーパントでドープされており、前記第2フィンFET体の前記ソースとドレインは前記第1ドーパントに相補的に第2ドーパントでドープされている、
請求項1記載のデバイス。 - 更に、前記導電ゲートのサイドウォールに形成されたスペーサを含む、
請求項1記載のデバイス。 - SOIMOSFETデバイスを形成するための方法であって、
誘電層を覆う半導体層(42)を含むSOI基板(40)を用意し、
ソース領域、ドレイン領域、及びこれらソース領域とドレイン領域との間に延びるチャネル領域を含むフィンFET体(46)を形成するために前記半導体層(42)をパターニングし、
少なくとも前記チャネル領域の表面部上に歪みシリコン層(34)を形成し、
前記チャネル領域上に成長した前記歪みシリコン(34)を覆うために前記チャネル領域に成長した少なくとも前記歪みシリコン(34)上にゲート絶縁膜(36)を形成し、
前記チャネル領域のサイドウォールと上部を囲み、前記ゲート絶縁層(36)と前記歪みシリコン(34)によって前記チャネル領域から分離される導電ゲートを形成することを含む、
方法。 - 前記半導体層(42)は、シリコンゲルマニウムであり、前記フィンFET体(46)は、シリコンゲルマニウムである、
請求項5記載の方法。 - 前記フィンFET体(46)は、第1フィンFET体を含み、且つ、
前記方法は、更に、
第2ソース領域と第2ドレイン領域を含み、第2ソース領域と第2ドレイン領域の間に延びる第2チャネル領域を有する第2フィンFET体を形成するために前記半導体層をパターニングし、同時に前記第1フィンFET体をパターニングし、
第2フィンFET体の少なくとも前記第2チャネル領域の表面上に歪みシリコン層を形成し、同時に前記第1フィンFET体に歪み層を成長させ、
前記第2チャネル領域に成長した前記歪みシリコンを覆うために前記第2フィンFET体の前記第2チャネル領域に成長した少なくとも前記歪みシリコン上にゲート絶縁膜を形成し、同時に前記第1フィンFET体上に前記導電ゲートを形成し、
前記第1フィンFET体上に前記導電ゲートを形成し、
前記第1フィンFET体の前記導電ゲートと前記第2第1フィンFET体の前記導電ゲートは、電気的に接続される、
請求項5記載の方法。 - 前記フィンFET体(46)は、前記ソース領域とドレイン領域に延びる少なくとも第1と第2チャネル領域を有する、
請求項5記載の方法。 - 誘電層を覆う半導体層を含むSOI基板の用意では、
シリコンゲルマニウム層を含む基板を用意し、
前記シリコンゲルマニウムに酸素を注入し、且つ、
前記シリコンゲルマニウム層に埋め込みシリコンゲルマニウム酸化膜を形成するために前記基板をアニーリングすることが含まれる、
請求項5記載の方法。 - 誘電層を覆う半導体層を含むSOI基板の用意では、
シリコンゲルマニウム層を含む第1基板を用意し、
前記シリコンゲルマニウム層内に高濃度水素領域を形成するために前記シリコンゲルマニウム層に水素を注入し、
第2半導体基板の酸化膜に前記第1基板を接着し、
前記高濃度水素領域における前記第1基板を破砕するために前記接着された第1及び第2基板をアニーリングし、
前記酸化膜に接着されたシリコンゲルマニウム層を有する前記第2基板を生成するために前記第1基板を除去することが含まれる、
請求項5記載の方法。
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US41522602P | 2002-09-30 | 2002-09-30 | |
US10/335,474 US6800910B2 (en) | 2002-09-30 | 2002-12-31 | FinFET device incorporating strained silicon in the channel region |
PCT/US2003/028660 WO2004032246A1 (en) | 2002-09-30 | 2003-09-12 | Finfet having improved carrier mobility and method of its formation |
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EP (1) | EP1547156B1 (ja) |
JP (1) | JP2006501672A (ja) |
KR (1) | KR101020811B1 (ja) |
CN (1) | CN100524827C (ja) |
AU (1) | AU2003266149A1 (ja) |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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CN109920846B (zh) * | 2019-03-11 | 2023-11-03 | 长江存储科技有限责任公司 | 晶体管及其形成方法、存储器 |
CN111509048A (zh) * | 2020-04-28 | 2020-08-07 | 上海华力集成电路制造有限公司 | N型鳍式晶体管及其制造方法 |
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- 2003-09-12 AU AU2003266149A patent/AU2003266149A1/en not_active Abandoned
- 2003-09-12 DE DE60335391T patent/DE60335391D1/de not_active Expired - Lifetime
- 2003-09-12 JP JP2004541537A patent/JP2006501672A/ja active Pending
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- 2003-09-12 KR KR1020057005284A patent/KR101020811B1/ko active IP Right Grant
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JP2011103487A (ja) * | 2003-03-17 | 2011-05-26 | Samsung Electronics Co Ltd | 半導体素子及びトランジスタ |
JP2014220522A (ja) * | 2003-03-17 | 2014-11-20 | 三星電子株式会社Samsung Electronics Co.,Ltd. | 半導体素子 |
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Also Published As
Publication number | Publication date |
---|---|
WO2004032246A1 (en) | 2004-04-15 |
CN100524827C (zh) | 2009-08-05 |
CN1685523A (zh) | 2005-10-19 |
TW200414452A (en) | 2004-08-01 |
KR101020811B1 (ko) | 2011-03-09 |
AU2003266149A1 (en) | 2004-04-23 |
TWI364095B (en) | 2012-05-11 |
US20040061178A1 (en) | 2004-04-01 |
DE60335391D1 (de) | 2011-01-27 |
EP1547156B1 (en) | 2010-12-15 |
KR20050047129A (ko) | 2005-05-19 |
EP1547156A1 (en) | 2005-06-29 |
US6800910B2 (en) | 2004-10-05 |
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